Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/roland/infiniband
* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/roland/infiniband: IB/mlx4: Make sure RQ allocation is always valid RDMA/cma: Fix initialization of next_port IB/mlx4: Fix zeroing of rnr_retry value in ib_modify_qp() mlx4_core: Don't set MTT address in dMPT entries with PA set mlx4_core: Check firmware command interface revision IB/mthca, mlx4_core: Fix typo in comment mlx4_core: Free catastrophic error MSI-X interrupt with correct dev_id mlx4_core: Initialize ctx_list and ctx_lock earlier mlx4_core: Fix CQ context layout
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Коммит
99f9f3d49c
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@ -2773,8 +2773,8 @@ static int cma_init(void)
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int ret;
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get_random_bytes(&next_port, sizeof next_port);
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next_port = (next_port % (sysctl_local_port_range[1] -
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sysctl_local_port_range[0])) +
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next_port = ((unsigned int) next_port %
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(sysctl_local_port_range[1] - sysctl_local_port_range[0])) +
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sysctl_local_port_range[0];
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cma_wq = create_singlethread_workqueue("rdma_cm");
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if (!cma_wq)
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@ -189,18 +189,28 @@ static int send_wqe_overhead(enum ib_qp_type type)
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}
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static int set_rq_size(struct mlx4_ib_dev *dev, struct ib_qp_cap *cap,
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struct mlx4_ib_qp *qp)
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int is_user, int has_srq, struct mlx4_ib_qp *qp)
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{
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/* Sanity check RQ size before proceeding */
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if (cap->max_recv_wr > dev->dev->caps.max_wqes ||
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cap->max_recv_sge > dev->dev->caps.max_rq_sg)
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return -EINVAL;
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qp->rq.max = cap->max_recv_wr ? roundup_pow_of_two(cap->max_recv_wr) : 0;
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if (has_srq) {
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/* QPs attached to an SRQ should have no RQ */
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if (cap->max_recv_wr)
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return -EINVAL;
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qp->rq.wqe_shift = ilog2(roundup_pow_of_two(cap->max_recv_sge *
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sizeof (struct mlx4_wqe_data_seg)));
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qp->rq.max_gs = (1 << qp->rq.wqe_shift) / sizeof (struct mlx4_wqe_data_seg);
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qp->rq.max = qp->rq.max_gs = 0;
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} else {
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/* HW requires >= 1 RQ entry with >= 1 gather entry */
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if (is_user && (!cap->max_recv_wr || !cap->max_recv_sge))
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return -EINVAL;
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qp->rq.max = roundup_pow_of_two(max(1, cap->max_recv_wr));
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qp->rq.max_gs = roundup_pow_of_two(max(1, cap->max_recv_sge));
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qp->rq.wqe_shift = ilog2(qp->rq.max_gs * sizeof (struct mlx4_wqe_data_seg));
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}
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cap->max_recv_wr = qp->rq.max;
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cap->max_recv_sge = qp->rq.max_gs;
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@ -285,7 +295,7 @@ static int create_qp_common(struct mlx4_ib_dev *dev, struct ib_pd *pd,
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qp->sq.head = 0;
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qp->sq.tail = 0;
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err = set_rq_size(dev, &init_attr->cap, qp);
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err = set_rq_size(dev, &init_attr->cap, !!pd->uobject, !!init_attr->srq, qp);
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if (err)
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goto err;
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@ -762,11 +772,6 @@ static int __mlx4_ib_modify_qp(struct ib_qp *ibqp,
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optpar |= MLX4_QP_OPTPAR_PKEY_INDEX;
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}
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if (attr_mask & IB_QP_RNR_RETRY) {
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context->params1 |= cpu_to_be32(attr->rnr_retry << 13);
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optpar |= MLX4_QP_OPTPAR_RNR_RETRY;
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}
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if (attr_mask & IB_QP_AV) {
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if (mlx4_set_path(dev, &attr->ah_attr, &context->pri_path,
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attr_mask & IB_QP_PORT ? attr->port_num : qp->port)) {
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@ -802,6 +807,12 @@ static int __mlx4_ib_modify_qp(struct ib_qp *ibqp,
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context->pd = cpu_to_be32(to_mpd(ibqp->pd)->pdn);
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context->params1 = cpu_to_be32(MLX4_IB_ACK_REQ_FREQ << 28);
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if (attr_mask & IB_QP_RNR_RETRY) {
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context->params1 |= cpu_to_be32(attr->rnr_retry << 13);
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optpar |= MLX4_QP_OPTPAR_RNR_RETRY;
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}
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if (attr_mask & IB_QP_RETRY_CNT) {
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context->params1 |= cpu_to_be32(attr->retry_cnt << 16);
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optpar |= MLX4_QP_OPTPAR_RETRY_COUNT;
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@ -772,7 +772,7 @@ int mthca_QUERY_FW(struct mthca_dev *dev, u8 *status)
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MTHCA_GET(dev->fw_ver, outbox, QUERY_FW_VER_OFFSET);
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/*
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* FW subminor version is at more signifant bits than minor
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* FW subminor version is at more significant bits than minor
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* version, so swap here.
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*/
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dev->fw_ver = (dev->fw_ver & 0xffff00000000ull) |
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@ -61,7 +61,7 @@ struct mlx4_cq_context {
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__be32 solicit_producer_index;
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__be32 consumer_index;
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__be32 producer_index;
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u8 reserved6[2];
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u32 reserved6[2];
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__be64 db_rec_addr;
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};
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@ -490,9 +490,11 @@ static void mlx4_free_irqs(struct mlx4_dev *dev)
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if (eq_table->have_irq)
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free_irq(dev->pdev->irq, dev);
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for (i = 0; i < MLX4_NUM_EQ; ++i)
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for (i = 0; i < MLX4_EQ_CATAS; ++i)
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if (eq_table->eq[i].have_irq)
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free_irq(eq_table->eq[i].irq, eq_table->eq + i);
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if (eq_table->eq[MLX4_EQ_CATAS].have_irq)
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free_irq(eq_table->eq[MLX4_EQ_CATAS].irq, dev);
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}
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static int __devinit mlx4_map_clr_int(struct mlx4_dev *dev)
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@ -37,6 +37,10 @@
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#include "fw.h"
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#include "icm.h"
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enum {
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MLX4_COMMAND_INTERFACE_REV = 1
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};
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extern void __buggy_use_of_MLX4_GET(void);
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extern void __buggy_use_of_MLX4_PUT(void);
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@ -452,10 +456,12 @@ int mlx4_QUERY_FW(struct mlx4_dev *dev)
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u32 *outbox;
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int err = 0;
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u64 fw_ver;
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u16 cmd_if_rev;
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u8 lg;
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#define QUERY_FW_OUT_SIZE 0x100
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#define QUERY_FW_VER_OFFSET 0x00
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#define QUERY_FW_CMD_IF_REV_OFFSET 0x0a
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#define QUERY_FW_MAX_CMD_OFFSET 0x0f
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#define QUERY_FW_ERR_START_OFFSET 0x30
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#define QUERY_FW_ERR_SIZE_OFFSET 0x38
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MLX4_GET(fw_ver, outbox, QUERY_FW_VER_OFFSET);
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/*
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* FW subminor version is at more signifant bits than minor
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* FW subminor version is at more significant bits than minor
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* version, so swap here.
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*/
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dev->caps.fw_ver = (fw_ver & 0xffff00000000ull) |
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((fw_ver & 0xffff0000ull) >> 16) |
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((fw_ver & 0x0000ffffull) << 16);
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MLX4_GET(cmd_if_rev, outbox, QUERY_FW_CMD_IF_REV_OFFSET);
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if (cmd_if_rev != MLX4_COMMAND_INTERFACE_REV) {
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mlx4_err(dev, "Installed FW has unsupported "
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"command interface revision %d.\n",
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cmd_if_rev);
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mlx4_err(dev, "(Installed FW version is %d.%d.%03d)\n",
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(int) (dev->caps.fw_ver >> 32),
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(int) (dev->caps.fw_ver >> 16) & 0xffff,
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(int) dev->caps.fw_ver & 0xffff);
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mlx4_err(dev, "This driver version supports only revision %d.\n",
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MLX4_COMMAND_INTERFACE_REV);
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err = -ENODEV;
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goto out;
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}
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MLX4_GET(lg, outbox, QUERY_FW_MAX_CMD_OFFSET);
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cmd->max_cmds = 1 << lg;
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mlx4_dbg(dev, "FW version %d.%d.%03d, max commands %d\n",
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mlx4_dbg(dev, "FW version %d.%d.%03d (cmd intf rev %d), max commands %d\n",
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(int) (dev->caps.fw_ver >> 32),
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(int) (dev->caps.fw_ver >> 16) & 0xffff,
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(int) dev->caps.fw_ver & 0xffff,
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cmd->max_cmds);
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cmd_if_rev, cmd->max_cmds);
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MLX4_GET(fw->catas_offset, outbox, QUERY_FW_ERR_START_OFFSET);
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MLX4_GET(fw->catas_size, outbox, QUERY_FW_ERR_SIZE_OFFSET);
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@ -135,9 +135,6 @@ int mlx4_register_device(struct mlx4_dev *dev)
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struct mlx4_priv *priv = mlx4_priv(dev);
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struct mlx4_interface *intf;
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INIT_LIST_HEAD(&priv->ctx_list);
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spin_lock_init(&priv->ctx_lock);
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mutex_lock(&intf_mutex);
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list_add_tail(&priv->dev_list, &dev_list);
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@ -787,6 +787,8 @@ static int __devinit mlx4_init_one(struct pci_dev *pdev,
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dev = &priv->dev;
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dev->pdev = pdev;
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INIT_LIST_HEAD(&priv->ctx_list);
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spin_lock_init(&priv->ctx_lock);
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/*
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* Now reset the HCA before we touch the PCI capabilities or
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@ -324,15 +324,17 @@ int mlx4_mr_enable(struct mlx4_dev *dev, struct mlx4_mr *mr)
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MLX4_MPT_FLAG_MIO |
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MLX4_MPT_FLAG_REGION |
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mr->access);
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if (mr->mtt.order < 0)
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mpt_entry->flags |= cpu_to_be32(MLX4_MPT_FLAG_PHYSICAL);
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mpt_entry->key = cpu_to_be32(key_to_hw_index(mr->key));
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mpt_entry->pd = cpu_to_be32(mr->pd);
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mpt_entry->start = cpu_to_be64(mr->iova);
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mpt_entry->length = cpu_to_be64(mr->size);
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mpt_entry->entity_size = cpu_to_be32(mr->mtt.page_shift);
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mpt_entry->mtt_seg = cpu_to_be64(mlx4_mtt_addr(dev, &mr->mtt));
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if (mr->mtt.order < 0) {
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mpt_entry->flags |= cpu_to_be32(MLX4_MPT_FLAG_PHYSICAL);
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mpt_entry->mtt_seg = 0;
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} else
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mpt_entry->mtt_seg = cpu_to_be64(mlx4_mtt_addr(dev, &mr->mtt));
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err = mlx4_SW2HW_MPT(dev, mailbox,
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key_to_hw_index(mr->key) & (dev->caps.num_mpts - 1));
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