pinctrl: cherryview: Introduce helpers to IO with common registers
Pin control device and effectively the single community in it has a set of common registers. It's good to have a helpers to IO on them. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
This commit is contained in:
Родитель
4e7293e3a2
Коммит
99fd651227
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@ -598,6 +598,20 @@ static const struct chv_community *chv_communities[] = {
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*/
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static DEFINE_RAW_SPINLOCK(chv_lock);
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static u32 chv_pctrl_readl(struct chv_pinctrl *pctrl, unsigned int offset)
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{
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return readl(pctrl->regs + offset);
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}
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static void chv_pctrl_writel(struct chv_pinctrl *pctrl, unsigned int offset, u32 value)
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{
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void __iomem *reg = pctrl->regs + offset;
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/* Write and simple read back to confirm the bus transferring done */
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writel(value, reg);
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readl(reg);
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}
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static void __iomem *chv_padreg(struct chv_pinctrl *pctrl, unsigned int offset,
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unsigned int reg)
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{
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@ -1264,7 +1278,7 @@ static void chv_gpio_irq_ack(struct irq_data *d)
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intr_line = chv_readl(pctrl, pin, CHV_PADCTRL0);
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intr_line &= CHV_PADCTRL0_INTSEL_MASK;
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intr_line >>= CHV_PADCTRL0_INTSEL_SHIFT;
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chv_writel(BIT(intr_line), pctrl->regs + CHV_INTSTAT);
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chv_pctrl_writel(pctrl, CHV_INTSTAT, BIT(intr_line));
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raw_spin_unlock(&chv_lock);
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}
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@ -1283,12 +1297,12 @@ static void chv_gpio_irq_mask_unmask(struct irq_data *d, bool mask)
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intr_line &= CHV_PADCTRL0_INTSEL_MASK;
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intr_line >>= CHV_PADCTRL0_INTSEL_SHIFT;
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value = readl(pctrl->regs + CHV_INTMASK);
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value = chv_pctrl_readl(pctrl, CHV_INTMASK);
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if (mask)
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value &= ~BIT(intr_line);
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else
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value |= BIT(intr_line);
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chv_writel(value, pctrl->regs + CHV_INTMASK);
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chv_pctrl_writel(pctrl, CHV_INTMASK, value);
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raw_spin_unlock_irqrestore(&chv_lock, flags);
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}
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@ -1419,7 +1433,7 @@ static void chv_gpio_irq_handler(struct irq_desc *desc)
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chained_irq_enter(chip, desc);
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raw_spin_lock_irqsave(&chv_lock, flags);
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pending = readl(pctrl->regs + CHV_INTSTAT);
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pending = chv_pctrl_readl(pctrl, CHV_INTSTAT);
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raw_spin_unlock_irqrestore(&chv_lock, flags);
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for_each_set_bit(intr_line, &pending, pctrl->community->nirqs) {
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@ -1514,12 +1528,11 @@ static int chv_gpio_irq_init_hw(struct gpio_chip *chip)
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* Mask all interrupts the community is able to generate
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* but leave the ones that can only generate GPEs unmasked.
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*/
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chv_writel(GENMASK(31, pctrl->community->nirqs),
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pctrl->regs + CHV_INTMASK);
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chv_pctrl_writel(pctrl, CHV_INTMASK, GENMASK(31, pctrl->community->nirqs));
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}
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/* Clear all interrupts */
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chv_writel(0xffff, pctrl->regs + CHV_INTSTAT);
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chv_pctrl_writel(pctrl, CHV_INTSTAT, 0xffff);
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return 0;
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}
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@ -1618,9 +1631,9 @@ static acpi_status chv_pinctrl_mmio_access_handler(u32 function,
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raw_spin_lock_irqsave(&chv_lock, flags);
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if (function == ACPI_WRITE)
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chv_writel((u32)(*value), pctrl->regs + (u32)address);
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chv_pctrl_writel(pctrl, address, *value);
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else if (function == ACPI_READ)
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*value = readl(pctrl->regs + (u32)address);
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*value = chv_pctrl_readl(pctrl, address);
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else
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ret = AE_BAD_PARAMETER;
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@ -1718,7 +1731,7 @@ static int chv_pinctrl_suspend_noirq(struct device *dev)
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raw_spin_lock_irqsave(&chv_lock, flags);
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pctrl->saved_intmask = readl(pctrl->regs + CHV_INTMASK);
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pctrl->saved_intmask = chv_pctrl_readl(pctrl, CHV_INTMASK);
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for (i = 0; i < pctrl->community->npins; i++) {
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const struct pinctrl_pin_desc *desc;
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@ -1754,7 +1767,7 @@ static int chv_pinctrl_resume_noirq(struct device *dev)
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* registers because we don't know in which state BIOS left them
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* upon exiting suspend.
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*/
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chv_writel(0, pctrl->regs + CHV_INTMASK);
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chv_pctrl_writel(pctrl, CHV_INTMASK, 0x0000);
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for (i = 0; i < pctrl->community->npins; i++) {
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const struct pinctrl_pin_desc *desc;
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@ -1791,8 +1804,8 @@ static int chv_pinctrl_resume_noirq(struct device *dev)
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* Now that all pins are restored to known state, we can restore
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* the interrupt mask register as well.
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*/
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chv_writel(0xffff, pctrl->regs + CHV_INTSTAT);
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chv_writel(pctrl->saved_intmask, pctrl->regs + CHV_INTMASK);
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chv_pctrl_writel(pctrl, CHV_INTSTAT, 0xffff);
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chv_pctrl_writel(pctrl, CHV_INTMASK, pctrl->saved_intmask);
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raw_spin_unlock_irqrestore(&chv_lock, flags);
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