fbdev: sh_mobile_lcdc: Split LCDC start code from sh_mobile_lcdc_start
Splitting the LCDC start code from clock, MERAM and panel management will make the code usable by runtime PM. Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
This commit is contained in:
Laurent Pinchart
Родитель
505c7de51f
Коммит
9a217e3444
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@ -435,48 +435,42 @@ static void sh_mobile_lcdc_geometry(struct sh_mobile_lcdc_chan *ch)
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lcdc_write_chan(ch, LDHAJR, tmp);
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}
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static int sh_mobile_lcdc_start(struct sh_mobile_lcdc_priv *priv)
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/*
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* __sh_mobile_lcdc_start - Configure and tart the LCDC
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* @priv: LCDC device
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*
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* Configure all enabled channels and start the LCDC device. All external
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* devices (clocks, MERAM, panels, ...) are not touched by this function.
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*/
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static void __sh_mobile_lcdc_start(struct sh_mobile_lcdc_priv *priv)
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{
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struct sh_mobile_lcdc_chan *ch;
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struct sh_mobile_lcdc_board_cfg *board_cfg;
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unsigned long tmp;
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int bpp = 0;
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unsigned long ldddsr;
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int k, m, ret;
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int k, m;
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/* enable clocks before accessing the hardware */
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for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
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if (priv->ch[k].enabled) {
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sh_mobile_lcdc_clk_on(priv);
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if (!bpp)
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bpp = priv->ch[k].info->var.bits_per_pixel;
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}
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}
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/* Enable LCDC channels. Read data from external memory, avoid using the
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* BEU for now.
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*/
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lcdc_write(priv, _LDCNT2R, priv->ch[0].enabled | priv->ch[1].enabled);
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/* reset */
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lcdc_write(priv, _LDCNT2R, lcdc_read(priv, _LDCNT2R) | LDCNT2R_BR);
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lcdc_wait_bit(priv, _LDCNT2R, LDCNT2R_BR, 0);
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/* enable LCDC channels */
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tmp = lcdc_read(priv, _LDCNT2R);
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tmp |= priv->ch[0].enabled;
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tmp |= priv->ch[1].enabled;
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lcdc_write(priv, _LDCNT2R, tmp);
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/* read data from external memory, avoid using the BEU for now */
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lcdc_write(priv, _LDCNT2R, lcdc_read(priv, _LDCNT2R) & ~LDCNT2R_MD);
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/* stop the lcdc first */
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/* Stop the LCDC first and disable all interrupts. */
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sh_mobile_lcdc_start_stop(priv, 0);
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lcdc_write(priv, _LDINTR, 0);
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/* configure clocks */
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/* Configure power supply, dot clocks and start them. */
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tmp = priv->lddckr;
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for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
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ch = &priv->ch[k];
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if (!priv->ch[k].enabled)
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if (!ch->enabled)
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continue;
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if (!bpp)
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bpp = ch->info->var.bits_per_pixel;
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/* Power supply */
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lcdc_write_chan(ch, LDPMR, 0);
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m = ch->cfg.clock_divider;
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if (!m)
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continue;
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@ -493,187 +487,186 @@ static int sh_mobile_lcdc_start(struct sh_mobile_lcdc_priv *priv)
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}
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lcdc_write(priv, _LDDCKR, tmp);
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/* start dotclock again */
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lcdc_write(priv, _LDDCKSTPR, 0);
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lcdc_wait_bit(priv, _LDDCKSTPR, ~0, 0);
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/* interrupts are disabled to begin with */
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lcdc_write(priv, _LDINTR, 0);
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/* Setup geometry, format, frame buffer memory and operation mode. */
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for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
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ch = &priv->ch[k];
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if (!ch->enabled)
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continue;
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sh_mobile_lcdc_geometry(ch);
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/* power supply */
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lcdc_write_chan(ch, LDPMR, 0);
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board_cfg = &ch->cfg.board_cfg;
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if (board_cfg->setup_sys) {
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ret = board_cfg->setup_sys(board_cfg->board_data,
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ch, &sh_mobile_lcdc_sys_bus_ops);
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if (ret)
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return ret;
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}
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}
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/* word and long word swap */
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ldddsr = lcdc_read(priv, _LDDDSR);
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if (priv->ch[0].info->var.nonstd)
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ldddsr |= LDDDSR_LS | LDDDSR_WS | LDDDSR_BS;
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else {
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switch (bpp) {
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case 16:
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ldddsr |= LDDDSR_LS | LDDDSR_WS;
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break;
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case 24:
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ldddsr |= LDDDSR_LS | LDDDSR_WS | LDDDSR_BS;
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break;
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case 32:
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ldddsr |= LDDDSR_LS;
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break;
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}
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}
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lcdc_write(priv, _LDDDSR, ldddsr);
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for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
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unsigned long base_addr_y;
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unsigned long base_addr_c = 0;
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int pitch;
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ch = &priv->ch[k];
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if (!priv->ch[k].enabled)
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continue;
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/* set bpp format in PKF[4:0] */
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tmp = lcdc_read_chan(ch, LDDFR);
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tmp &= ~(LDDFR_CF0 | LDDFR_CC | LDDFR_YF_MASK | LDDFR_PKF_MASK);
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if (ch->info->var.nonstd) {
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tmp |= (ch->info->var.nonstd << 16);
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tmp = (ch->info->var.nonstd << 16);
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switch (ch->info->var.bits_per_pixel) {
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case 12:
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tmp |= LDDFR_YF_420;
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break;
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case 16:
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tmp |= LDDFR_YF_422;
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break;
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case 24:
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default:
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tmp |= LDDFR_YF_444;
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break;
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}
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} else {
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switch (ch->info->var.bits_per_pixel) {
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case 16:
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tmp |= LDDFR_PKF_RGB16;
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tmp = LDDFR_PKF_RGB16;
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break;
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case 24:
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tmp |= LDDFR_PKF_RGB24;
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tmp = LDDFR_PKF_RGB24;
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break;
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case 32:
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tmp |= LDDFR_PKF_ARGB32;
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default:
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tmp = LDDFR_PKF_ARGB32;
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break;
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}
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}
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lcdc_write_chan(ch, LDDFR, tmp);
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lcdc_write_chan(ch, LDMLSR, ch->pitch);
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lcdc_write_chan(ch, LDSA1R, ch->base_addr_y);
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if (ch->info->var.nonstd)
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lcdc_write_chan(ch, LDSA2R, ch->base_addr_c);
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base_addr_y = ch->info->fix.smem_start;
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base_addr_c = base_addr_y +
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ch->info->var.xres *
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ch->info->var.yres_virtual;
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pitch = ch->info->fix.line_length;
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/* When using deferred I/O mode, configure the LCDC for one-shot
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* operation and enable the frame end interrupt. Otherwise use
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* continuous read mode.
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*/
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if (ch->ldmt1r_value & LDMT1R_IFM &&
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ch->cfg.sys_bus_cfg.deferred_io_msec) {
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lcdc_write_chan(ch, LDSM1R, LDSM1R_OS);
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lcdc_write(priv, _LDINTR, LDINTR_FE);
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} else {
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lcdc_write_chan(ch, LDSM1R, 0);
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}
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}
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/* test if we can enable meram */
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if (ch->cfg.meram_cfg && priv->meram_dev &&
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priv->meram_dev->ops) {
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struct sh_mobile_meram_cfg *cfg;
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struct sh_mobile_meram_info *mdev;
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unsigned long icb_addr_y, icb_addr_c;
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int icb_pitch;
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int pf;
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/* Word and long word swap. */
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if (priv->ch[0].info->var.nonstd)
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tmp = LDDDSR_LS | LDDDSR_WS | LDDDSR_BS;
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else {
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switch (bpp) {
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case 16:
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tmp = LDDDSR_LS | LDDDSR_WS;
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break;
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case 24:
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tmp = LDDDSR_LS | LDDDSR_WS | LDDDSR_BS;
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break;
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case 32:
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default:
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tmp = LDDDSR_LS;
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break;
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}
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}
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lcdc_write(priv, _LDDDSR, tmp);
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cfg = ch->cfg.meram_cfg;
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mdev = priv->meram_dev;
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/* we need to de-init configured ICBs before we
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* we can re-initialize them.
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*/
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if (ch->meram_enabled)
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mdev->ops->meram_unregister(mdev, cfg);
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/* Enable the display output. */
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lcdc_write(priv, _LDCNT1R, LDCNT1R_DE);
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sh_mobile_lcdc_start_stop(priv, 1);
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priv->started = 1;
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}
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static int sh_mobile_lcdc_start(struct sh_mobile_lcdc_priv *priv)
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{
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struct sh_mobile_meram_info *mdev = priv->meram_dev;
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struct sh_mobile_lcdc_board_cfg *board_cfg;
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struct sh_mobile_lcdc_chan *ch;
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unsigned long tmp;
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int ret;
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int k;
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/* enable clocks before accessing the hardware */
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for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
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if (priv->ch[k].enabled)
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sh_mobile_lcdc_clk_on(priv);
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}
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/* reset */
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lcdc_write(priv, _LDCNT2R, lcdc_read(priv, _LDCNT2R) | LDCNT2R_BR);
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lcdc_wait_bit(priv, _LDCNT2R, LDCNT2R_BR, 0);
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for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
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ch = &priv->ch[k];
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if (!ch->enabled)
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continue;
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board_cfg = &ch->cfg.board_cfg;
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if (board_cfg->setup_sys) {
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ret = board_cfg->setup_sys(board_cfg->board_data, ch,
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&sh_mobile_lcdc_sys_bus_ops);
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if (ret)
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return ret;
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}
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}
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/* Compute frame buffer base address and pitch for each channel. */
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for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
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struct sh_mobile_meram_cfg *cfg;
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int pixelformat;
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ch = &priv->ch[k];
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if (!ch->enabled)
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continue;
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ch->base_addr_y = ch->info->fix.smem_start;
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ch->base_addr_c = ch->base_addr_y
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+ ch->info->var.xres
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* ch->info->var.yres_virtual;
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ch->pitch = ch->info->fix.line_length;
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/* Enable MERAM if possible. */
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cfg = ch->cfg.meram_cfg;
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if (mdev == NULL || mdev->ops == NULL || cfg == NULL)
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continue;
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/* we need to de-init configured ICBs before we can
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* re-initialize them.
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*/
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if (ch->meram_enabled) {
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mdev->ops->meram_unregister(mdev, cfg);
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ch->meram_enabled = 0;
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if (ch->info->var.nonstd) {
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if (ch->info->var.bits_per_pixel == 24)
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pf = SH_MOBILE_MERAM_PF_NV24;
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else
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pf = SH_MOBILE_MERAM_PF_NV;
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} else {
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pf = SH_MOBILE_MERAM_PF_RGB;
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}
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ret = mdev->ops->meram_register(mdev, cfg, pitch,
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ch->info->var.yres,
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pf,
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base_addr_y,
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base_addr_c,
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&icb_addr_y,
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&icb_addr_c,
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&icb_pitch);
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if (!ret) {
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/* set LDSA1R value */
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base_addr_y = icb_addr_y;
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pitch = icb_pitch;
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/* set LDSA2R value if required */
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if (base_addr_c)
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base_addr_c = icb_addr_c;
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ch->meram_enabled = 1;
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}
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}
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/* point out our frame buffer */
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lcdc_write_chan(ch, LDSA1R, base_addr_y);
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if (ch->info->var.nonstd)
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lcdc_write_chan(ch, LDSA2R, base_addr_c);
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if (!ch->info->var.nonstd)
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pixelformat = SH_MOBILE_MERAM_PF_RGB;
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else if (ch->info->var.bits_per_pixel == 24)
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pixelformat = SH_MOBILE_MERAM_PF_NV24;
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else
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pixelformat = SH_MOBILE_MERAM_PF_NV;
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/* set line size */
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lcdc_write_chan(ch, LDMLSR, pitch);
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ret = mdev->ops->meram_register(mdev, cfg, ch->pitch,
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ch->info->var.yres, pixelformat,
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ch->base_addr_y, ch->base_addr_c,
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&ch->base_addr_y, &ch->base_addr_c,
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&ch->pitch);
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if (!ret)
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ch->meram_enabled = 1;
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}
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/* Start the LCDC. */
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__sh_mobile_lcdc_start(priv);
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/* Setup deferred I/O, tell the board code to enable the panels, and
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* turn backlight on.
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*/
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for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
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ch = &priv->ch[k];
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if (!ch->enabled)
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continue;
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/* setup deferred io if SYS bus */
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tmp = ch->cfg.sys_bus_cfg.deferred_io_msec;
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if (ch->ldmt1r_value & LDMT1R_IFM && tmp) {
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ch->defio.deferred_io = sh_mobile_lcdc_deferred_io;
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ch->defio.delay = msecs_to_jiffies(tmp);
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ch->info->fbdefio = &ch->defio;
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fb_deferred_io_init(ch->info);
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/* one-shot mode */
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lcdc_write_chan(ch, LDSM1R, LDSM1R_OS);
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/* enable "Frame End Interrupt Enable" bit */
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lcdc_write(priv, _LDINTR, LDINTR_FE);
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} else {
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/* continuous read mode */
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lcdc_write_chan(ch, LDSM1R, 0);
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}
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}
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/* display output */
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lcdc_write(priv, _LDCNT1R, LDCNT1R_DE);
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/* start the lcdc */
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sh_mobile_lcdc_start_stop(priv, 1);
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priv->started = 1;
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/* tell the board code to enable the panel */
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for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
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ch = &priv->ch[k];
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if (!ch->enabled)
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continue;
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board_cfg = &ch->cfg.board_cfg;
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if (board_cfg->display_on && try_module_get(board_cfg->owner)) {
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@ -18,6 +18,13 @@ struct sh_mobile_lcdc_priv;
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struct fb_info;
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struct backlight_device;
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/*
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* struct sh_mobile_lcdc_chan - LCDC display channel
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*
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* @base_addr_y: Frame buffer viewport base address (luma component)
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* @base_addr_c: Frame buffer viewport base address (chroma component)
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* @pitch: Frame buffer line pitch
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*/
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struct sh_mobile_lcdc_chan {
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struct sh_mobile_lcdc_priv *lcdc;
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unsigned long *reg_offs;
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@ -40,6 +47,10 @@ struct sh_mobile_lcdc_chan {
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int blank_status;
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struct mutex open_lock; /* protects the use counter */
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int meram_enabled;
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unsigned long base_addr_y;
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unsigned long base_addr_c;
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unsigned int pitch;
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};
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#endif
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