cpufreq: remove blackfin driver
The blackfin architecture is getting removed, so this driver is now obsolete. Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Acked-by: Rafael J. Wysocki <rafael@kernel.org> Acked-by: Aaron Wu <aaron.wu@analog.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
Родитель
1e81bf79e3
Коммит
9a3daf58f9
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@ -100,7 +100,6 @@ obj-$(CONFIG_POWERNV_CPUFREQ) += powernv-cpufreq.o
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##################################################################################
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# Other platform drivers
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obj-$(CONFIG_BFIN_CPU_FREQ) += blackfin-cpufreq.o
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obj-$(CONFIG_BMIPS_CPUFREQ) += bmips-cpufreq.o
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obj-$(CONFIG_CRIS_MACH_ARTPEC3) += cris-artpec3-cpufreq.o
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obj-$(CONFIG_ETRAXFS) += cris-etraxfs-cpufreq.o
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@ -1,217 +0,0 @@
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/*
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* Blackfin core clock scaling
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*
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* Copyright 2008-2011 Analog Devices Inc.
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*
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* Licensed under the GPL-2 or later.
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/types.h>
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#include <linux/init.h>
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#include <linux/clk.h>
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#include <linux/cpufreq.h>
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#include <linux/fs.h>
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#include <linux/delay.h>
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#include <asm/blackfin.h>
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#include <asm/time.h>
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#include <asm/dpmc.h>
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/* this is the table of CCLK frequencies, in Hz */
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/* .driver_data is the entry in the auxiliary dpm_state_table[] */
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static struct cpufreq_frequency_table bfin_freq_table[] = {
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{
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.frequency = CPUFREQ_TABLE_END,
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.driver_data = 0,
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},
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{
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.frequency = CPUFREQ_TABLE_END,
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.driver_data = 1,
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},
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{
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.frequency = CPUFREQ_TABLE_END,
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.driver_data = 2,
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},
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{
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.frequency = CPUFREQ_TABLE_END,
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.driver_data = 0,
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},
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};
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static struct bfin_dpm_state {
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unsigned int csel; /* system clock divider */
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unsigned int tscale; /* change the divider on the core timer interrupt */
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} dpm_state_table[3];
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#if defined(CONFIG_CYCLES_CLOCKSOURCE)
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/*
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* normalized to maximum frequency offset for CYCLES,
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* used in time-ts cycles clock source, but could be used
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* somewhere also.
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*/
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unsigned long long __bfin_cycles_off;
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unsigned int __bfin_cycles_mod;
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#endif
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/**************************************************************************/
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static void __init bfin_init_tables(unsigned long cclk, unsigned long sclk)
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{
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unsigned long csel, min_cclk;
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int index;
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/* Anomaly 273 seems to still exist on non-BF54x w/dcache turned on */
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#if ANOMALY_05000273 || ANOMALY_05000274 || \
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(!(defined(CONFIG_BF54x) || defined(CONFIG_BF60x)) \
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&& defined(CONFIG_BFIN_EXTMEM_DCACHEABLE))
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min_cclk = sclk * 2;
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#else
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min_cclk = sclk;
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#endif
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#ifndef CONFIG_BF60x
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csel = ((bfin_read_PLL_DIV() & CSEL) >> 4);
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#else
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csel = bfin_read32(CGU0_DIV) & 0x1F;
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#endif
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for (index = 0; (cclk >> index) >= min_cclk && csel <= 3 && index < 3; index++, csel++) {
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bfin_freq_table[index].frequency = cclk >> index;
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#ifndef CONFIG_BF60x
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dpm_state_table[index].csel = csel << 4; /* Shift now into PLL_DIV bitpos */
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#else
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dpm_state_table[index].csel = csel;
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#endif
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dpm_state_table[index].tscale = (TIME_SCALE >> index) - 1;
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pr_debug("cpufreq: freq:%d csel:0x%x tscale:%d\n",
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bfin_freq_table[index].frequency,
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dpm_state_table[index].csel,
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dpm_state_table[index].tscale);
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}
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return;
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}
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static void bfin_adjust_core_timer(void *info)
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{
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unsigned int tscale;
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unsigned int index = *(unsigned int *)info;
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/* we have to adjust the core timer, because it is using cclk */
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tscale = dpm_state_table[index].tscale;
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bfin_write_TSCALE(tscale);
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return;
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}
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static unsigned int bfin_getfreq_khz(unsigned int cpu)
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{
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/* Both CoreA/B have the same core clock */
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return get_cclk() / 1000;
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}
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#ifdef CONFIG_BF60x
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static int cpu_set_cclk(int cpu, unsigned long new)
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{
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struct clk *clk;
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int ret;
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clk = clk_get(NULL, "CCLK");
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if (IS_ERR(clk))
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return -ENODEV;
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ret = clk_set_rate(clk, new);
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clk_put(clk);
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return ret;
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}
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#endif
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static int bfin_target(struct cpufreq_policy *policy, unsigned int index)
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{
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#ifndef CONFIG_BF60x
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unsigned int plldiv;
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#endif
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static unsigned long lpj_ref;
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static unsigned int lpj_ref_freq;
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unsigned int old_freq, new_freq;
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int ret = 0;
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#if defined(CONFIG_CYCLES_CLOCKSOURCE)
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cycles_t cycles;
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#endif
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old_freq = bfin_getfreq_khz(0);
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new_freq = bfin_freq_table[index].frequency;
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#ifndef CONFIG_BF60x
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plldiv = (bfin_read_PLL_DIV() & SSEL) | dpm_state_table[index].csel;
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bfin_write_PLL_DIV(plldiv);
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#else
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ret = cpu_set_cclk(policy->cpu, new_freq * 1000);
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if (ret != 0) {
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WARN_ONCE(ret, "cpufreq set freq failed %d\n", ret);
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return ret;
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}
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#endif
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on_each_cpu(bfin_adjust_core_timer, &index, 1);
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#if defined(CONFIG_CYCLES_CLOCKSOURCE)
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cycles = get_cycles();
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SSYNC();
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cycles += 10; /* ~10 cycles we lose after get_cycles() */
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__bfin_cycles_off += (cycles << __bfin_cycles_mod) - (cycles << index);
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__bfin_cycles_mod = index;
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#endif
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if (!lpj_ref_freq) {
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lpj_ref = loops_per_jiffy;
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lpj_ref_freq = old_freq;
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}
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if (new_freq != old_freq) {
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loops_per_jiffy = cpufreq_scale(lpj_ref,
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lpj_ref_freq, new_freq);
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}
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return ret;
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}
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static int __bfin_cpu_init(struct cpufreq_policy *policy)
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{
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unsigned long cclk, sclk;
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cclk = get_cclk() / 1000;
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sclk = get_sclk() / 1000;
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if (policy->cpu == CPUFREQ_CPU)
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bfin_init_tables(cclk, sclk);
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policy->cpuinfo.transition_latency = 50000; /* 50us assumed */
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return cpufreq_table_validate_and_show(policy, bfin_freq_table);
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}
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static struct cpufreq_driver bfin_driver = {
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.verify = cpufreq_generic_frequency_table_verify,
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.target_index = bfin_target,
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.get = bfin_getfreq_khz,
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.init = __bfin_cpu_init,
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.name = "bfin cpufreq",
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.attr = cpufreq_generic_attr,
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};
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static int __init bfin_cpu_init(void)
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{
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return cpufreq_register_driver(&bfin_driver);
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}
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static void __exit bfin_cpu_exit(void)
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{
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cpufreq_unregister_driver(&bfin_driver);
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}
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MODULE_AUTHOR("Michael Hennerich <hennerich@blackfin.uclinux.org>");
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MODULE_DESCRIPTION("cpufreq driver for Blackfin");
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MODULE_LICENSE("GPL");
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module_init(bfin_cpu_init);
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module_exit(bfin_cpu_exit);
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