MIPS: OCTEON: Use correct CSR to soft reset
Also delete unused cvmx_reset_octeon() This fixes reboot for Octeon III boards Signed-off-by: Chandrakala Chavva <cchavva@caviumnetworks.com> Signed-off-by: Aleksey Makarov <aleksey.makarov@auriga.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Cc: David Daney <david.daney@cavium.com> Patchwork: https://patchwork.linux-mips.org/patch/9471/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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@ -413,7 +413,10 @@ static void octeon_restart(char *command)
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mb();
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while (1)
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cvmx_write_csr(CVMX_CIU_SOFT_RST, 1);
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if (OCTEON_IS_OCTEON3())
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cvmx_write_csr(CVMX_RST_SOFT_RST, 1);
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else
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cvmx_write_csr(CVMX_CIU_SOFT_RST, 1);
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}
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@ -436,14 +436,6 @@ static inline uint64_t cvmx_get_cycle_global(void)
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/***************************************************************************/
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static inline void cvmx_reset_octeon(void)
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{
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union cvmx_ciu_soft_rst ciu_soft_rst;
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ciu_soft_rst.u64 = 0;
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ciu_soft_rst.s.soft_rst = 1;
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cvmx_write_csr(CVMX_CIU_SOFT_RST, ciu_soft_rst.u64);
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}
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/* Return the number of cores available in the chip */
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static inline uint32_t cvmx_octeon_num_cores(void)
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{
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