ixgbe: Add support for the new ethtool n-tuple programming interface
This patch adds n-tuple filter programming to 82599. Signed-off-by: Peter P Waskiewicz Jr <peter.p.waskiewicz.jr@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Родитель
15682bc488
Коммит
9a713e7c7c
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@ -453,6 +453,10 @@ extern s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 pballoc);
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extern s32 ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw,
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struct ixgbe_atr_input *input,
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u8 queue);
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extern s32 ixgbe_fdir_add_perfect_filter_82599(struct ixgbe_hw *hw,
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struct ixgbe_atr_input *input,
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struct ixgbe_atr_input_masks *input_masks,
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u16 soft_id, u8 queue);
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extern s32 ixgbe_atr_set_vlan_id_82599(struct ixgbe_atr_input *input,
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u16 vlan_id);
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extern s32 ixgbe_atr_set_src_ipv4_82599(struct ixgbe_atr_input *input,
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@ -1439,6 +1439,9 @@ s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 pballoc)
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/* Send interrupt when 64 filters are left */
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fdirctrl |= 4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT;
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/* Initialize the drop queue to Rx queue 127 */
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fdirctrl |= (127 << IXGBE_FDIRCTRL_DROP_Q_SHIFT);
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switch (pballoc) {
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case IXGBE_FDIR_PBALLOC_64K:
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/* 2k - 1 perfect filters */
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@ -1628,6 +1631,7 @@ static u16 ixgbe_atr_compute_hash_82599(struct ixgbe_atr_input *atr_input,
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* ixgbe_atr_set_vlan_id_82599 - Sets the VLAN id in the ATR input stream
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* @input: input stream to modify
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* @vlan: the VLAN id to load
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* @vlan_mask: bitwise mask for the VLAN
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**/
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s32 ixgbe_atr_set_vlan_id_82599(struct ixgbe_atr_input *input, u16 vlan)
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{
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@ -1641,6 +1645,7 @@ s32 ixgbe_atr_set_vlan_id_82599(struct ixgbe_atr_input *input, u16 vlan)
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* ixgbe_atr_set_src_ipv4_82599 - Sets the source IPv4 address
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* @input: input stream to modify
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* @src_addr: the IP address to load
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* @src_addr_mask: bitwise mask for the source IP address
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**/
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s32 ixgbe_atr_set_src_ipv4_82599(struct ixgbe_atr_input *input, u32 src_addr)
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{
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@ -1658,6 +1663,7 @@ s32 ixgbe_atr_set_src_ipv4_82599(struct ixgbe_atr_input *input, u32 src_addr)
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* ixgbe_atr_set_dst_ipv4_82599 - Sets the destination IPv4 address
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* @input: input stream to modify
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* @dst_addr: the IP address to load
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* @dst_addr_mask: bitwise mask for the destination IP address
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**/
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s32 ixgbe_atr_set_dst_ipv4_82599(struct ixgbe_atr_input *input, u32 dst_addr)
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{
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@ -1680,8 +1686,8 @@ s32 ixgbe_atr_set_dst_ipv4_82599(struct ixgbe_atr_input *input, u32 dst_addr)
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* @src_addr_4: the fourth 4 bytes of the IP address to load
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**/
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s32 ixgbe_atr_set_src_ipv6_82599(struct ixgbe_atr_input *input,
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u32 src_addr_1, u32 src_addr_2,
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u32 src_addr_3, u32 src_addr_4)
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u32 src_addr_1, u32 src_addr_2,
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u32 src_addr_3, u32 src_addr_4)
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{
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input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET] = src_addr_4 & 0xff;
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input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 1] =
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@ -1723,8 +1729,8 @@ s32 ixgbe_atr_set_src_ipv6_82599(struct ixgbe_atr_input *input,
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* @dst_addr_4: the fourth 4 bytes of the IP address to load
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**/
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s32 ixgbe_atr_set_dst_ipv6_82599(struct ixgbe_atr_input *input,
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u32 dst_addr_1, u32 dst_addr_2,
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u32 dst_addr_3, u32 dst_addr_4)
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u32 dst_addr_1, u32 dst_addr_2,
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u32 dst_addr_3, u32 dst_addr_4)
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{
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input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET] = dst_addr_4 & 0xff;
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input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 1] =
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@ -1761,6 +1767,7 @@ s32 ixgbe_atr_set_dst_ipv6_82599(struct ixgbe_atr_input *input,
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* ixgbe_atr_set_src_port_82599 - Sets the source port
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* @input: input stream to modify
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* @src_port: the source port to load
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* @src_port_mask: bitwise mask for the source port
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**/
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s32 ixgbe_atr_set_src_port_82599(struct ixgbe_atr_input *input, u16 src_port)
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{
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@ -1774,6 +1781,7 @@ s32 ixgbe_atr_set_src_port_82599(struct ixgbe_atr_input *input, u16 src_port)
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* ixgbe_atr_set_dst_port_82599 - Sets the destination port
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* @input: input stream to modify
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* @dst_port: the destination port to load
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* @dst_port_mask: bitwise mask for the destination port
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**/
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s32 ixgbe_atr_set_dst_port_82599(struct ixgbe_atr_input *input, u16 dst_port)
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{
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@ -1802,7 +1810,7 @@ s32 ixgbe_atr_set_flex_byte_82599(struct ixgbe_atr_input *input, u16 flex_byte)
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* @vm_pool: the Virtual Machine pool to load
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**/
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s32 ixgbe_atr_set_vm_pool_82599(struct ixgbe_atr_input *input,
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u8 vm_pool)
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u8 vm_pool)
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{
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input->byte_stream[IXGBE_ATR_VM_POOL_OFFSET] = vm_pool;
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@ -1826,8 +1834,7 @@ s32 ixgbe_atr_set_l4type_82599(struct ixgbe_atr_input *input, u8 l4type)
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* @input: input stream to search
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* @vlan: the VLAN id to load
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**/
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static s32 ixgbe_atr_get_vlan_id_82599(struct ixgbe_atr_input *input,
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u16 *vlan)
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static s32 ixgbe_atr_get_vlan_id_82599(struct ixgbe_atr_input *input, u16 *vlan)
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{
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*vlan = input->byte_stream[IXGBE_ATR_VLAN_OFFSET];
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*vlan |= input->byte_stream[IXGBE_ATR_VLAN_OFFSET + 1] << 8;
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@ -2083,23 +2090,26 @@ s32 ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw,
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* ixgbe_fdir_add_perfect_filter_82599 - Adds a perfect filter
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* @hw: pointer to hardware structure
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* @input: input bitstream
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* @input_masks: bitwise masks for relevant fields
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* @soft_id: software index into the silicon hash tables for filter storage
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* @queue: queue index to direct traffic to
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*
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* Note that the caller to this function must lock before calling, since the
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* hardware writes must be protected from one another.
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**/
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s32 ixgbe_fdir_add_perfect_filter_82599(struct ixgbe_hw *hw,
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struct ixgbe_atr_input *input,
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u16 soft_id,
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u8 queue)
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struct ixgbe_atr_input *input,
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struct ixgbe_atr_input_masks *input_masks,
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u16 soft_id, u8 queue)
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{
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u32 fdircmd = 0;
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u32 fdirhash;
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u32 src_ipv4, dst_ipv4;
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u32 src_ipv4 = 0, dst_ipv4 = 0;
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u32 src_ipv6_1, src_ipv6_2, src_ipv6_3, src_ipv6_4;
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u16 src_port, dst_port, vlan_id, flex_bytes;
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u16 bucket_hash;
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u8 l4type;
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u8 fdirm = 0;
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/* Get our input values */
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ixgbe_atr_get_l4type_82599(input, &l4type);
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@ -2154,7 +2164,6 @@ s32 ixgbe_fdir_add_perfect_filter_82599(struct ixgbe_hw *hw,
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/* IPv4 */
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ixgbe_atr_get_src_ipv4_82599(input, &src_ipv4);
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IXGBE_WRITE_REG(hw, IXGBE_FDIRIPSA, src_ipv4);
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}
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ixgbe_atr_get_dst_ipv4_82599(input, &dst_ipv4);
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@ -2163,7 +2172,78 @@ s32 ixgbe_fdir_add_perfect_filter_82599(struct ixgbe_hw *hw,
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IXGBE_WRITE_REG(hw, IXGBE_FDIRVLAN, (vlan_id |
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(flex_bytes << IXGBE_FDIRVLAN_FLEX_SHIFT)));
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IXGBE_WRITE_REG(hw, IXGBE_FDIRPORT, (src_port |
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(dst_port << IXGBE_FDIRPORT_DESTINATION_SHIFT)));
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(dst_port << IXGBE_FDIRPORT_DESTINATION_SHIFT)));
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/*
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* Program the relevant mask registers. If src/dst_port or src/dst_addr
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* are zero, then assume a full mask for that field. Also assume that
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* a VLAN of 0 is unspecified, so mask that out as well. L4type
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* cannot be masked out in this implementation.
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*
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* This also assumes IPv4 only. IPv6 masking isn't supported at this
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* point in time.
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*/
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if (src_ipv4 == 0)
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IXGBE_WRITE_REG(hw, IXGBE_FDIRSIP4M, 0xffffffff);
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else
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IXGBE_WRITE_REG(hw, IXGBE_FDIRSIP4M, input_masks->src_ip_mask);
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if (dst_ipv4 == 0)
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IXGBE_WRITE_REG(hw, IXGBE_FDIRDIP4M, 0xffffffff);
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else
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IXGBE_WRITE_REG(hw, IXGBE_FDIRDIP4M, input_masks->dst_ip_mask);
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switch (l4type & IXGBE_ATR_L4TYPE_MASK) {
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case IXGBE_ATR_L4TYPE_TCP:
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if (src_port == 0)
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IXGBE_WRITE_REG(hw, IXGBE_FDIRTCPM, 0xffff);
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else
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IXGBE_WRITE_REG(hw, IXGBE_FDIRTCPM,
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input_masks->src_port_mask);
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if (dst_port == 0)
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IXGBE_WRITE_REG(hw, IXGBE_FDIRTCPM,
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(IXGBE_READ_REG(hw, IXGBE_FDIRTCPM) |
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(0xffff << 16)));
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else
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IXGBE_WRITE_REG(hw, IXGBE_FDIRTCPM,
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(IXGBE_READ_REG(hw, IXGBE_FDIRTCPM) |
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(input_masks->dst_port_mask << 16)));
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break;
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case IXGBE_ATR_L4TYPE_UDP:
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if (src_port == 0)
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IXGBE_WRITE_REG(hw, IXGBE_FDIRUDPM, 0xffff);
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else
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IXGBE_WRITE_REG(hw, IXGBE_FDIRUDPM,
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input_masks->src_port_mask);
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if (dst_port == 0)
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IXGBE_WRITE_REG(hw, IXGBE_FDIRUDPM,
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(IXGBE_READ_REG(hw, IXGBE_FDIRUDPM) |
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(0xffff << 16)));
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else
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IXGBE_WRITE_REG(hw, IXGBE_FDIRUDPM,
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(IXGBE_READ_REG(hw, IXGBE_FDIRUDPM) |
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(input_masks->src_port_mask << 16)));
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break;
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default:
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/* this already would have failed above */
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break;
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}
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/* Program the last mask register, FDIRM */
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if (input_masks->vlan_id_mask || !vlan_id)
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/* Mask both VLAN and VLANP - bits 0 and 1 */
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fdirm |= 0x3;
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if (input_masks->data_mask || !flex_bytes)
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/* Flex bytes need masking, so mask the whole thing - bit 4 */
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fdirm |= 0x10;
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/* Now mask VM pool and destination IPv6 - bits 5 and 2 */
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fdirm |= 0x24;
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IXGBE_WRITE_REG(hw, IXGBE_FDIRM, fdirm);
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fdircmd |= IXGBE_FDIRCMD_CMD_ADD_FLOW;
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fdircmd |= IXGBE_FDIRCMD_FILTER_UPDATE;
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@ -979,6 +979,9 @@ static int ixgbe_get_sset_count(struct net_device *netdev, int sset)
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return IXGBE_TEST_LEN;
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case ETH_SS_STATS:
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return IXGBE_STATS_LEN;
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case ETH_SS_NTUPLE_FILTERS:
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return (ETHTOOL_MAX_NTUPLE_LIST_ENTRY *
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ETHTOOL_MAX_NTUPLE_STRING_PER_ENTRY);
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default:
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return -EOPNOTSUPP;
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}
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@ -2150,23 +2153,124 @@ static int ixgbe_set_coalesce(struct net_device *netdev,
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static int ixgbe_set_flags(struct net_device *netdev, u32 data)
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{
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struct ixgbe_adapter *adapter = netdev_priv(netdev);
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bool need_reset = false;
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ethtool_op_set_flags(netdev, data);
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if (!(adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE))
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return 0;
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/* if state changes we need to update adapter->flags and reset */
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if ((!!(data & ETH_FLAG_LRO)) !=
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(!!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED))) {
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adapter->flags2 ^= IXGBE_FLAG2_RSC_ENABLED;
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need_reset = true;
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}
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/*
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* Check if Flow Director n-tuple support was enabled or disabled. If
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* the state changed, we need to reset.
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*/
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if ((adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) &&
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(!(data & ETH_FLAG_NTUPLE))) {
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/* turn off Flow Director perfect, set hash and reset */
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adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
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adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
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need_reset = true;
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} else if ((!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)) &&
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(data & ETH_FLAG_NTUPLE)) {
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/* turn off Flow Director hash, enable perfect and reset */
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adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
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adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
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need_reset = true;
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} else {
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/* no state change */
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}
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if (need_reset) {
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if (netif_running(netdev))
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ixgbe_reinit_locked(adapter);
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else
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ixgbe_reset(adapter);
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}
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return 0;
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return 0;
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}
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static int ixgbe_set_rx_ntuple(struct net_device *dev,
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struct ethtool_rx_ntuple *cmd)
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{
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struct ixgbe_adapter *adapter = netdev_priv(dev);
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struct ethtool_rx_ntuple_flow_spec fs = cmd->fs;
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struct ixgbe_atr_input input_struct;
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struct ixgbe_atr_input_masks input_masks;
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int target_queue;
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if (adapter->hw.mac.type == ixgbe_mac_82598EB)
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return -EOPNOTSUPP;
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/*
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* Don't allow programming if the action is a queue greater than
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* the number of online Tx queues.
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*/
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if ((fs.action >= adapter->num_tx_queues) ||
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(fs.action < ETHTOOL_RXNTUPLE_ACTION_DROP))
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return -EINVAL;
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memset(&input_struct, 0, sizeof(struct ixgbe_atr_input));
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memset(&input_masks, 0, sizeof(struct ixgbe_atr_input_masks));
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input_masks.src_ip_mask = fs.m_u.tcp_ip4_spec.ip4src;
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input_masks.dst_ip_mask = fs.m_u.tcp_ip4_spec.ip4dst;
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input_masks.src_port_mask = fs.m_u.tcp_ip4_spec.psrc;
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input_masks.dst_port_mask = fs.m_u.tcp_ip4_spec.pdst;
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input_masks.vlan_id_mask = fs.vlan_tag_mask;
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/* only use the lowest 2 bytes for flex bytes */
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input_masks.data_mask = (fs.data_mask & 0xffff);
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switch (fs.flow_type) {
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case TCP_V4_FLOW:
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ixgbe_atr_set_l4type_82599(&input_struct, IXGBE_ATR_L4TYPE_TCP);
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break;
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case UDP_V4_FLOW:
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ixgbe_atr_set_l4type_82599(&input_struct, IXGBE_ATR_L4TYPE_UDP);
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break;
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case SCTP_V4_FLOW:
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ixgbe_atr_set_l4type_82599(&input_struct, IXGBE_ATR_L4TYPE_SCTP);
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break;
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default:
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return -1;
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}
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/* Mask bits from the inputs based on user-supplied mask */
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ixgbe_atr_set_src_ipv4_82599(&input_struct,
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(fs.h_u.tcp_ip4_spec.ip4src & ~fs.m_u.tcp_ip4_spec.ip4src));
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ixgbe_atr_set_dst_ipv4_82599(&input_struct,
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(fs.h_u.tcp_ip4_spec.ip4dst & ~fs.m_u.tcp_ip4_spec.ip4dst));
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/* 82599 expects these to be byte-swapped for perfect filtering */
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ixgbe_atr_set_src_port_82599(&input_struct,
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((ntohs(fs.h_u.tcp_ip4_spec.psrc)) & ~fs.m_u.tcp_ip4_spec.psrc));
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ixgbe_atr_set_dst_port_82599(&input_struct,
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((ntohs(fs.h_u.tcp_ip4_spec.pdst)) & ~fs.m_u.tcp_ip4_spec.pdst));
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/* VLAN and Flex bytes are either completely masked or not */
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if (!fs.vlan_tag_mask)
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ixgbe_atr_set_vlan_id_82599(&input_struct, fs.vlan_tag);
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if (!input_masks.data_mask)
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/* make sure we only use the first 2 bytes of user data */
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ixgbe_atr_set_flex_byte_82599(&input_struct,
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(fs.data & 0xffff));
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/* determine if we need to drop or route the packet */
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if (fs.action == ETHTOOL_RXNTUPLE_ACTION_DROP)
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target_queue = MAX_RX_QUEUES - 1;
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else
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target_queue = fs.action;
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spin_lock(&adapter->fdir_perfect_lock);
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ixgbe_fdir_add_perfect_filter_82599(&adapter->hw, &input_struct,
|
||||
&input_masks, 0, target_queue);
|
||||
spin_unlock(&adapter->fdir_perfect_lock);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct ethtool_ops ixgbe_ethtool_ops = {
|
||||
|
@ -2204,6 +2308,7 @@ static const struct ethtool_ops ixgbe_ethtool_ops = {
|
|||
.set_coalesce = ixgbe_set_coalesce,
|
||||
.get_flags = ethtool_op_get_flags,
|
||||
.set_flags = ixgbe_set_flags,
|
||||
.set_rx_ntuple = ixgbe_set_rx_ntuple,
|
||||
};
|
||||
|
||||
void ixgbe_set_ethtool_ops(struct net_device *netdev)
|
||||
|
|
|
@ -3253,6 +3253,9 @@ void ixgbe_down(struct ixgbe_adapter *adapter)
|
|||
|
||||
netif_carrier_off(netdev);
|
||||
|
||||
/* clear n-tuple filters that are cached */
|
||||
ethtool_ntuple_flush(netdev);
|
||||
|
||||
if (!pci_channel_offline(adapter->pdev))
|
||||
ixgbe_reset(adapter);
|
||||
ixgbe_clean_all_tx_rings(adapter);
|
||||
|
@ -4187,6 +4190,7 @@ static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
|
|||
{
|
||||
struct ixgbe_hw *hw = &adapter->hw;
|
||||
struct pci_dev *pdev = adapter->pdev;
|
||||
struct net_device *dev = adapter->netdev;
|
||||
unsigned int rss;
|
||||
#ifdef CONFIG_IXGBE_DCB
|
||||
int j;
|
||||
|
@ -4214,10 +4218,18 @@ static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
|
|||
adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82599;
|
||||
adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
|
||||
adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
|
||||
adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
|
||||
if (dev->features & NETIF_F_NTUPLE) {
|
||||
/* Flow Director perfect filter enabled */
|
||||
adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
|
||||
adapter->atr_sample_rate = 0;
|
||||
spin_lock_init(&adapter->fdir_perfect_lock);
|
||||
} else {
|
||||
/* Flow Director hash filters enabled */
|
||||
adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
|
||||
adapter->atr_sample_rate = 20;
|
||||
}
|
||||
adapter->ring_feature[RING_F_FDIR].indices =
|
||||
IXGBE_MAX_FDIR_INDICES;
|
||||
adapter->atr_sample_rate = 20;
|
||||
adapter->fdir_pballoc = 0;
|
||||
#ifdef IXGBE_FCOE
|
||||
adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
|
||||
|
|
|
@ -2129,6 +2129,15 @@ struct ixgbe_atr_input {
|
|||
u8 byte_stream[42];
|
||||
};
|
||||
|
||||
struct ixgbe_atr_input_masks {
|
||||
u32 src_ip_mask;
|
||||
u32 dst_ip_mask;
|
||||
u16 src_port_mask;
|
||||
u16 dst_port_mask;
|
||||
u16 vlan_id_mask;
|
||||
u16 data_mask;
|
||||
};
|
||||
|
||||
enum ixgbe_eeprom_type {
|
||||
ixgbe_eeprom_uninitialized = 0,
|
||||
ixgbe_eeprom_spi,
|
||||
|
|
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