[media] exynos4-is: Add Exynos4x12 FIMC-IS driver
This patch adds a set of core files of the Exynos4x12 FIMC-IS V4L2 driver. This includes main functionality like allocating memory, loading the firmware, FIMC-IS register interface and host CPU <-> IS command and error code definitions. The driver currently exposes a single subdev named FIMC-IS-ISP, which corresponds to the FIMC-IS ISP and DRC IP blocks. The FIMC-IS-ISP subdev currently supports only a subset of user controls. For other controls we need several extensions at the V4L2 API. The supported standard controls are: brightness, contrast, saturation, hue, sharpness, 3a_lock, exposure_time_absolute, white_balance_auto_preset, iso_sensitivity, iso_sensitivity_auto, exposure_metering_mode. Signed-off-by: Younghwan Joo <yhwan.joo@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
This commit is contained in:
Sylwester Nawrocki
Mauro Carvalho Chehab
Родитель
c6e8d96d42
Коммит
9a761e4368
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/*
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* Samsung Exynos4x12 FIMC-IS (Imaging Subsystem) driver
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*
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* FIMC-IS command set definitions
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*
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* Copyright (C) 2013 Samsung Electronics Co., Ltd.
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*
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* Authors: Younghwan Joo <yhwan.joo@samsung.com>
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* Sylwester Nawrocki <s.nawrocki@samsung.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef FIMC_IS_CMD_H_
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#define FIMC_IS_CMD_H_
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#define FIMC_IS_COMMAND_VER 110 /* FIMC-IS command set version 1.10 */
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/* Enumeration of commands beetween the FIMC-IS and the host processor. */
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/* HOST to FIMC-IS */
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#define HIC_PREVIEW_STILL 0x0001
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#define HIC_PREVIEW_VIDEO 0x0002
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#define HIC_CAPTURE_STILL 0x0003
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#define HIC_CAPTURE_VIDEO 0x0004
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#define HIC_STREAM_ON 0x0005
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#define HIC_STREAM_OFF 0x0006
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#define HIC_SET_PARAMETER 0x0007
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#define HIC_GET_PARAMETER 0x0008
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#define HIC_SET_TUNE 0x0009
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#define HIC_GET_STATUS 0x000b
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/* Sensor part */
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#define HIC_OPEN_SENSOR 0x000c
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#define HIC_CLOSE_SENSOR 0x000d
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#define HIC_SIMMIAN_INIT 0x000e
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#define HIC_SIMMIAN_WRITE 0x000f
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#define HIC_SIMMIAN_READ 0x0010
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#define HIC_POWER_DOWN 0x0011
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#define HIC_GET_SET_FILE_ADDR 0x0012
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#define HIC_LOAD_SET_FILE 0x0013
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#define HIC_MSG_CONFIG 0x0014
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#define HIC_MSG_TEST 0x0015
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/* FIMC-IS to HOST */
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#define IHC_GET_SENSOR_NUM 0x1000
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#define IHC_SET_SHOT_MARK 0x1001
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/* parameter1: frame number */
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/* parameter2: confidence level (smile 0~100) */
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/* parameter3: confidence level (blink 0~100) */
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#define IHC_SET_FACE_MARK 0x1002
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/* parameter1: coordinate count */
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/* parameter2: coordinate buffer address */
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#define IHC_FRAME_DONE 0x1003
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/* parameter1: frame start number */
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/* parameter2: frame count */
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#define IHC_AA_DONE 0x1004
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#define IHC_NOT_READY 0x1005
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#define IH_REPLY_DONE 0x2000
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#define IH_REPLY_NOT_DONE 0x2001
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enum fimc_is_scenario {
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IS_SC_PREVIEW_STILL,
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IS_SC_PREVIEW_VIDEO,
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IS_SC_CAPTURE_STILL,
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IS_SC_CAPTURE_VIDEO,
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IS_SC_MAX
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};
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enum fimc_is_sub_scenario {
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IS_SC_SUB_DEFAULT,
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IS_SC_SUB_PS_VTCALL,
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IS_SC_SUB_CS_VTCALL,
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IS_SC_SUB_PV_VTCALL,
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IS_SC_SUB_CV_VTCALL,
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};
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struct is_common_regs {
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u32 hicmd;
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u32 hic_sensorid;
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u32 hic_param[4];
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u32 reserved1[4];
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u32 ihcmd;
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u32 ihc_sensorid;
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u32 ihc_param[4];
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u32 reserved2[4];
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u32 isp_sensor_id;
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u32 isp_param[2];
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u32 reserved3[1];
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u32 scc_sensor_id;
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u32 scc_param[2];
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u32 reserved4[1];
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u32 dnr_sensor_id;
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u32 dnr_param[2];
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u32 reserved5[1];
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u32 scp_sensor_id;
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u32 scp_param[2];
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u32 reserved6[29];
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} __packed;
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struct is_mcuctl_reg {
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u32 mcuctl;
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u32 bboar;
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u32 intgr0;
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u32 intcr0;
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u32 intmr0;
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u32 intsr0;
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u32 intmsr0;
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u32 intgr1;
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u32 intcr1;
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u32 intmr1;
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u32 intsr1;
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u32 intmsr1;
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u32 intcr2;
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u32 intmr2;
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u32 intsr2;
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u32 intmsr2;
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u32 gpoctrl;
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u32 cpoenctlr;
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u32 gpictlr;
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u32 reserved[0xd];
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struct is_common_regs common;
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} __packed;
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#endif /* FIMC_IS_CMD_H_ */
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@ -0,0 +1,272 @@
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/*
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* Samsung Exynos4 SoC series FIMC-IS slave interface driver
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*
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* Error log interface functions
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*
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* Copyright (C) 2011 - 2013 Samsung Electronics Co., Ltd.
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*
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* Authors: Younghwan Joo <yhwan.joo@samsung.com>
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* Sylwester Nawrocki <s.nawrocki@samsung.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include "fimc-is-errno.h"
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const char * const fimc_is_param_strerr(unsigned int error)
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{
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switch (error) {
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case ERROR_COMMON_CMD:
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return "ERROR_COMMON_CMD: Invalid Command";
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case ERROR_COMMON_PARAMETER:
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return "ERROR_COMMON_PARAMETER: Invalid Parameter";
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case ERROR_COMMON_SETFILE_LOAD:
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return "ERROR_COMMON_SETFILE_LOAD: Illegal Setfile Loading";
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case ERROR_COMMON_SETFILE_ADJUST:
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return "ERROR_COMMON_SETFILE_ADJUST: Setfile isn't adjusted";
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case ERROR_COMMON_SETFILE_INDEX:
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return "ERROR_COMMON_SETFILE_INDEX: Invalid setfile index";
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case ERROR_COMMON_INPUT_PATH:
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return "ERROR_COMMON_INPUT_PATH: Input path can be changed in ready state";
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case ERROR_COMMON_INPUT_INIT:
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return "ERROR_COMMON_INPUT_INIT: IP can not start if input path is not set";
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case ERROR_COMMON_OUTPUT_PATH:
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return "ERROR_COMMON_OUTPUT_PATH: Output path can be changed in ready state (stop)";
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case ERROR_COMMON_OUTPUT_INIT:
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return "ERROR_COMMON_OUTPUT_INIT: IP can not start if output path is not set";
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case ERROR_CONTROL_BYPASS:
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return "ERROR_CONTROL_BYPASS";
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case ERROR_OTF_INPUT_FORMAT:
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return "ERROR_OTF_INPUT_FORMAT: Invalid format (DRC: YUV444, FD: YUV444, 422, 420)";
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case ERROR_OTF_INPUT_WIDTH:
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return "ERROR_OTF_INPUT_WIDTH: Invalid width (DRC: 128~8192, FD: 32~8190)";
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case ERROR_OTF_INPUT_HEIGHT:
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return "ERROR_OTF_INPUT_HEIGHT: Invalid bit-width (DRC: 8~12bits, FD: 8bit)";
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case ERROR_OTF_INPUT_BIT_WIDTH:
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return "ERROR_OTF_INPUT_BIT_WIDTH: Invalid bit-width (DRC: 8~12bits, FD: 8bit)";
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case ERROR_DMA_INPUT_WIDTH:
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return "ERROR_DMA_INPUT_WIDTH: Invalid width (DRC: 128~8192, FD: 32~8190)";
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case ERROR_DMA_INPUT_HEIGHT:
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return "ERROR_DMA_INPUT_HEIGHT: Invalid height (DRC: 64~8192, FD: 16~8190)";
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case ERROR_DMA_INPUT_FORMAT:
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return "ERROR_DMA_INPUT_FORMAT: Invalid format (DRC: YUV444 or YUV422, FD: YUV444,422,420)";
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case ERROR_DMA_INPUT_BIT_WIDTH:
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return "ERROR_DMA_INPUT_BIT_WIDTH: Invalid bit-width (DRC: 8~12bits, FD: 8bit)";
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case ERROR_DMA_INPUT_ORDER:
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return "ERROR_DMA_INPUT_ORDER: Invalid order(DRC: YYCbCr,YCbYCr,FD:NO,YYCbCr,YCbYCr,CbCr,CrCb)";
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case ERROR_DMA_INPUT_PLANE:
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return "ERROR_DMA_INPUT_PLANE: Invalid palne (DRC: 3, FD: 1, 2, 3)";
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case ERROR_OTF_OUTPUT_WIDTH:
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return "ERROR_OTF_OUTPUT_WIDTH: Invalid width (DRC: 128~8192)";
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case ERROR_OTF_OUTPUT_HEIGHT:
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return "ERROR_OTF_OUTPUT_HEIGHT: Invalid height (DRC: 64~8192)";
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case ERROR_OTF_OUTPUT_FORMAT:
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return "ERROR_OTF_OUTPUT_FORMAT: Invalid format (DRC: YUV444)";
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case ERROR_OTF_OUTPUT_BIT_WIDTH:
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return "ERROR_OTF_OUTPUT_BIT_WIDTH: Invalid bit-width (DRC: 8~12bits, FD: 8bit)";
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case ERROR_DMA_OUTPUT_WIDTH:
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return "ERROR_DMA_OUTPUT_WIDTH";
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case ERROR_DMA_OUTPUT_HEIGHT:
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return "ERROR_DMA_OUTPUT_HEIGHT";
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case ERROR_DMA_OUTPUT_FORMAT:
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return "ERROR_DMA_OUTPUT_FORMAT";
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case ERROR_DMA_OUTPUT_BIT_WIDTH:
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return "ERROR_DMA_OUTPUT_BIT_WIDTH";
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case ERROR_DMA_OUTPUT_PLANE:
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return "ERROR_DMA_OUTPUT_PLANE";
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case ERROR_DMA_OUTPUT_ORDER:
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return "ERROR_DMA_OUTPUT_ORDER";
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/* Sensor Error(100~199) */
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case ERROR_SENSOR_I2C_FAIL:
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return "ERROR_SENSOR_I2C_FAIL";
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case ERROR_SENSOR_INVALID_FRAMERATE:
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return "ERROR_SENSOR_INVALID_FRAMERATE";
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case ERROR_SENSOR_INVALID_EXPOSURETIME:
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return "ERROR_SENSOR_INVALID_EXPOSURETIME";
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case ERROR_SENSOR_INVALID_SIZE:
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return "ERROR_SENSOR_INVALID_SIZE";
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case ERROR_SENSOR_INVALID_SETTING:
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return "ERROR_SENSOR_INVALID_SETTING";
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case ERROR_SENSOR_ACTURATOR_INIT_FAIL:
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return "ERROR_SENSOR_ACTURATOR_INIT_FAIL";
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case ERROR_SENSOR_INVALID_AF_POS:
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return "ERROR_SENSOR_INVALID_AF_POS";
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case ERROR_SENSOR_UNSUPPORT_FUNC:
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return "ERROR_SENSOR_UNSUPPORT_FUNC";
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case ERROR_SENSOR_UNSUPPORT_PERI:
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return "ERROR_SENSOR_UNSUPPORT_PERI";
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case ERROR_SENSOR_UNSUPPORT_AF:
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return "ERROR_SENSOR_UNSUPPORT_AF";
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/* ISP Error (200~299) */
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case ERROR_ISP_AF_BUSY:
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return "ERROR_ISP_AF_BUSY";
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case ERROR_ISP_AF_INVALID_COMMAND:
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return "ERROR_ISP_AF_INVALID_COMMAND";
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case ERROR_ISP_AF_INVALID_MODE:
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return "ERROR_ISP_AF_INVALID_MODE";
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/* DRC Error (300~399) */
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/* FD Error (400~499) */
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case ERROR_FD_CONFIG_MAX_NUMBER_STATE:
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return "ERROR_FD_CONFIG_MAX_NUMBER_STATE";
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case ERROR_FD_CONFIG_MAX_NUMBER_INVALID:
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return "ERROR_FD_CONFIG_MAX_NUMBER_INVALID";
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case ERROR_FD_CONFIG_YAW_ANGLE_STATE:
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return "ERROR_FD_CONFIG_YAW_ANGLE_STATE";
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case ERROR_FD_CONFIG_YAW_ANGLE_INVALID:
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return "ERROR_FD_CONFIG_YAW_ANGLE_INVALID\n";
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case ERROR_FD_CONFIG_ROLL_ANGLE_STATE:
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return "ERROR_FD_CONFIG_ROLL_ANGLE_STATE";
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case ERROR_FD_CONFIG_ROLL_ANGLE_INVALID:
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return "ERROR_FD_CONFIG_ROLL_ANGLE_INVALID";
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case ERROR_FD_CONFIG_SMILE_MODE_INVALID:
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return "ERROR_FD_CONFIG_SMILE_MODE_INVALID";
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case ERROR_FD_CONFIG_BLINK_MODE_INVALID:
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return "ERROR_FD_CONFIG_BLINK_MODE_INVALID";
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case ERROR_FD_CONFIG_EYES_DETECT_INVALID:
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return "ERROR_FD_CONFIG_EYES_DETECT_INVALID";
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case ERROR_FD_CONFIG_MOUTH_DETECT_INVALID:
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return "ERROR_FD_CONFIG_MOUTH_DETECT_INVALID";
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case ERROR_FD_CONFIG_ORIENTATION_STATE:
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return "ERROR_FD_CONFIG_ORIENTATION_STATE";
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case ERROR_FD_CONFIG_ORIENTATION_INVALID:
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return "ERROR_FD_CONFIG_ORIENTATION_INVALID";
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case ERROR_FD_CONFIG_ORIENTATION_VALUE_INVALID:
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return "ERROR_FD_CONFIG_ORIENTATION_VALUE_INVALID";
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case ERROR_FD_RESULT:
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return "ERROR_FD_RESULT";
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case ERROR_FD_MODE:
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return "ERROR_FD_MODE";
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default:
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return "Unknown";
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}
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}
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const char * const fimc_is_strerr(unsigned int error)
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{
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error &= ~IS_ERROR_TIME_OUT_FLAG;
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switch (error) {
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/* General */
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case IS_ERROR_INVALID_COMMAND:
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return "IS_ERROR_INVALID_COMMAND";
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case IS_ERROR_REQUEST_FAIL:
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return "IS_ERROR_REQUEST_FAIL";
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case IS_ERROR_INVALID_SCENARIO:
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return "IS_ERROR_INVALID_SCENARIO";
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case IS_ERROR_INVALID_SENSORID:
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return "IS_ERROR_INVALID_SENSORID";
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case IS_ERROR_INVALID_MODE_CHANGE:
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return "IS_ERROR_INVALID_MODE_CHANGE";
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case IS_ERROR_INVALID_MAGIC_NUMBER:
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return "IS_ERROR_INVALID_MAGIC_NUMBER";
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case IS_ERROR_INVALID_SETFILE_HDR:
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return "IS_ERROR_INVALID_SETFILE_HDR";
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case IS_ERROR_BUSY:
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return "IS_ERROR_BUSY";
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case IS_ERROR_SET_PARAMETER:
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return "IS_ERROR_SET_PARAMETER";
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case IS_ERROR_INVALID_PATH:
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return "IS_ERROR_INVALID_PATH";
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case IS_ERROR_OPEN_SENSOR_FAIL:
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return "IS_ERROR_OPEN_SENSOR_FAIL";
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case IS_ERROR_ENTRY_MSG_THREAD_DOWN:
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return "IS_ERROR_ENTRY_MSG_THREAD_DOWN";
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case IS_ERROR_ISP_FRAME_END_NOT_DONE:
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return "IS_ERROR_ISP_FRAME_END_NOT_DONE";
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case IS_ERROR_DRC_FRAME_END_NOT_DONE:
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return "IS_ERROR_DRC_FRAME_END_NOT_DONE";
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case IS_ERROR_SCALERC_FRAME_END_NOT_DONE:
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return "IS_ERROR_SCALERC_FRAME_END_NOT_DONE";
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case IS_ERROR_ODC_FRAME_END_NOT_DONE:
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return "IS_ERROR_ODC_FRAME_END_NOT_DONE";
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case IS_ERROR_DIS_FRAME_END_NOT_DONE:
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return "IS_ERROR_DIS_FRAME_END_NOT_DONE";
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case IS_ERROR_TDNR_FRAME_END_NOT_DONE:
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return "IS_ERROR_TDNR_FRAME_END_NOT_DONE";
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case IS_ERROR_SCALERP_FRAME_END_NOT_DONE:
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return "IS_ERROR_SCALERP_FRAME_END_NOT_DONE";
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case IS_ERROR_WAIT_STREAM_OFF_NOT_DONE:
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return "IS_ERROR_WAIT_STREAM_OFF_NOT_DONE";
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case IS_ERROR_NO_MSG_IS_RECEIVED:
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return "IS_ERROR_NO_MSG_IS_RECEIVED";
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case IS_ERROR_SENSOR_MSG_FAIL:
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return "IS_ERROR_SENSOR_MSG_FAIL";
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case IS_ERROR_ISP_MSG_FAIL:
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return "IS_ERROR_ISP_MSG_FAIL";
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case IS_ERROR_DRC_MSG_FAIL:
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return "IS_ERROR_DRC_MSG_FAIL";
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case IS_ERROR_LHFD_MSG_FAIL:
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return "IS_ERROR_LHFD_MSG_FAIL";
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case IS_ERROR_UNKNOWN:
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return "IS_ERROR_UNKNOWN";
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/* Sensor */
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case IS_ERROR_SENSOR_PWRDN_FAIL:
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return "IS_ERROR_SENSOR_PWRDN_FAIL";
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/* ISP */
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case IS_ERROR_ISP_PWRDN_FAIL:
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return "IS_ERROR_ISP_PWRDN_FAIL";
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case IS_ERROR_ISP_MULTIPLE_INPUT:
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return "IS_ERROR_ISP_MULTIPLE_INPUT";
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case IS_ERROR_ISP_ABSENT_INPUT:
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return "IS_ERROR_ISP_ABSENT_INPUT";
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case IS_ERROR_ISP_ABSENT_OUTPUT:
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return "IS_ERROR_ISP_ABSENT_OUTPUT";
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case IS_ERROR_ISP_NONADJACENT_OUTPUT:
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return "IS_ERROR_ISP_NONADJACENT_OUTPUT";
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case IS_ERROR_ISP_FORMAT_MISMATCH:
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return "IS_ERROR_ISP_FORMAT_MISMATCH";
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case IS_ERROR_ISP_WIDTH_MISMATCH:
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return "IS_ERROR_ISP_WIDTH_MISMATCH";
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case IS_ERROR_ISP_HEIGHT_MISMATCH:
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return "IS_ERROR_ISP_HEIGHT_MISMATCH";
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case IS_ERROR_ISP_BITWIDTH_MISMATCH:
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return "IS_ERROR_ISP_BITWIDTH_MISMATCH";
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case IS_ERROR_ISP_FRAME_END_TIME_OUT:
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return "IS_ERROR_ISP_FRAME_END_TIME_OUT";
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/* DRC */
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case IS_ERROR_DRC_PWRDN_FAIL:
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return "IS_ERROR_DRC_PWRDN_FAIL";
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case IS_ERROR_DRC_MULTIPLE_INPUT:
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return "IS_ERROR_DRC_MULTIPLE_INPUT";
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case IS_ERROR_DRC_ABSENT_INPUT:
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return "IS_ERROR_DRC_ABSENT_INPUT";
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case IS_ERROR_DRC_NONADJACENT_INPUT:
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return "IS_ERROR_DRC_NONADJACENT_INPUT";
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case IS_ERROR_DRC_ABSENT_OUTPUT:
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return "IS_ERROR_DRC_ABSENT_OUTPUT";
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case IS_ERROR_DRC_NONADJACENT_OUTPUT:
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return "IS_ERROR_DRC_NONADJACENT_OUTPUT";
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case IS_ERROR_DRC_FORMAT_MISMATCH:
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return "IS_ERROR_DRC_FORMAT_MISMATCH";
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case IS_ERROR_DRC_WIDTH_MISMATCH:
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||||
return "IS_ERROR_DRC_WIDTH_MISMATCH";
|
||||
case IS_ERROR_DRC_HEIGHT_MISMATCH:
|
||||
return "IS_ERROR_DRC_HEIGHT_MISMATCH";
|
||||
case IS_ERROR_DRC_BITWIDTH_MISMATCH:
|
||||
return "IS_ERROR_DRC_BITWIDTH_MISMATCH";
|
||||
case IS_ERROR_DRC_FRAME_END_TIME_OUT:
|
||||
return "IS_ERROR_DRC_FRAME_END_TIME_OUT";
|
||||
|
||||
/* FD */
|
||||
case IS_ERROR_FD_PWRDN_FAIL:
|
||||
return "IS_ERROR_FD_PWRDN_FAIL";
|
||||
case IS_ERROR_FD_MULTIPLE_INPUT:
|
||||
return "IS_ERROR_FD_MULTIPLE_INPUT";
|
||||
case IS_ERROR_FD_ABSENT_INPUT:
|
||||
return "IS_ERROR_FD_ABSENT_INPUT";
|
||||
case IS_ERROR_FD_NONADJACENT_INPUT:
|
||||
return "IS_ERROR_FD_NONADJACENT_INPUT";
|
||||
case IS_ERROR_LHFD_FRAME_END_TIME_OUT:
|
||||
return "IS_ERROR_LHFD_FRAME_END_TIME_OUT";
|
||||
default:
|
||||
return "Unknown";
|
||||
}
|
||||
}
|
||||
|
|
@ -0,0 +1,248 @@
|
|||
/*
|
||||
* Samsung Exynos4 SoC series FIMC-IS slave interface driver
|
||||
*
|
||||
* FIMC-IS error code definition
|
||||
*
|
||||
* Copyright (C) 2011 - 2013 Samsung Electronics Co., Ltd.
|
||||
*
|
||||
* Authors: Younghwan Joo <yhwan.joo@samsung.com>
|
||||
* Sylwester Nawrocki <s.nawrocki@samsung.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#ifndef FIMC_IS_ERR_H_
|
||||
#define FIMC_IS_ERR_H_
|
||||
|
||||
#define IS_ERROR_VER 011 /* IS ERROR VERSION 0.11 */
|
||||
|
||||
enum {
|
||||
IS_ERROR_NONE,
|
||||
|
||||
/* General 1 ~ 99 */
|
||||
IS_ERROR_INVALID_COMMAND,
|
||||
IS_ERROR_REQUEST_FAIL,
|
||||
IS_ERROR_INVALID_SCENARIO,
|
||||
IS_ERROR_INVALID_SENSORID,
|
||||
IS_ERROR_INVALID_MODE_CHANGE,
|
||||
IS_ERROR_INVALID_MAGIC_NUMBER,
|
||||
IS_ERROR_INVALID_SETFILE_HDR,
|
||||
IS_ERROR_BUSY,
|
||||
IS_ERROR_SET_PARAMETER,
|
||||
IS_ERROR_INVALID_PATH,
|
||||
IS_ERROR_OPEN_SENSOR_FAIL,
|
||||
IS_ERROR_ENTRY_MSG_THREAD_DOWN,
|
||||
IS_ERROR_ISP_FRAME_END_NOT_DONE,
|
||||
IS_ERROR_DRC_FRAME_END_NOT_DONE,
|
||||
IS_ERROR_SCALERC_FRAME_END_NOT_DONE,
|
||||
IS_ERROR_ODC_FRAME_END_NOT_DONE,
|
||||
IS_ERROR_DIS_FRAME_END_NOT_DONE,
|
||||
IS_ERROR_TDNR_FRAME_END_NOT_DONE,
|
||||
IS_ERROR_SCALERP_FRAME_END_NOT_DONE,
|
||||
IS_ERROR_WAIT_STREAM_OFF_NOT_DONE,
|
||||
IS_ERROR_NO_MSG_IS_RECEIVED,
|
||||
IS_ERROR_SENSOR_MSG_FAIL,
|
||||
IS_ERROR_ISP_MSG_FAIL,
|
||||
IS_ERROR_DRC_MSG_FAIL,
|
||||
IS_ERROR_SCALERC_MSG_FAIL,
|
||||
IS_ERROR_ODC_MSG_FAIL,
|
||||
IS_ERROR_DIS_MSG_FAIL,
|
||||
IS_ERROR_TDNR_MSG_FAIL,
|
||||
IS_ERROR_SCALERP_MSG_FAIL,
|
||||
IS_ERROR_LHFD_MSG_FAIL,
|
||||
IS_ERROR_LHFD_INTERNAL_STOP,
|
||||
|
||||
/* Sensor 100 ~ 199 */
|
||||
IS_ERROR_SENSOR_PWRDN_FAIL = 100,
|
||||
IS_ERROR_SENSOR_STREAM_ON_FAIL,
|
||||
IS_ERROR_SENSOR_STREAM_OFF_FAIL,
|
||||
|
||||
/* ISP 200 ~ 299 */
|
||||
IS_ERROR_ISP_PWRDN_FAIL = 200,
|
||||
IS_ERROR_ISP_MULTIPLE_INPUT,
|
||||
IS_ERROR_ISP_ABSENT_INPUT,
|
||||
IS_ERROR_ISP_ABSENT_OUTPUT,
|
||||
IS_ERROR_ISP_NONADJACENT_OUTPUT,
|
||||
IS_ERROR_ISP_FORMAT_MISMATCH,
|
||||
IS_ERROR_ISP_WIDTH_MISMATCH,
|
||||
IS_ERROR_ISP_HEIGHT_MISMATCH,
|
||||
IS_ERROR_ISP_BITWIDTH_MISMATCH,
|
||||
IS_ERROR_ISP_FRAME_END_TIME_OUT,
|
||||
|
||||
/* DRC 300 ~ 399 */
|
||||
IS_ERROR_DRC_PWRDN_FAIL = 300,
|
||||
IS_ERROR_DRC_MULTIPLE_INPUT,
|
||||
IS_ERROR_DRC_ABSENT_INPUT,
|
||||
IS_ERROR_DRC_NONADJACENT_INPUT,
|
||||
IS_ERROR_DRC_ABSENT_OUTPUT,
|
||||
IS_ERROR_DRC_NONADJACENT_OUTPUT,
|
||||
IS_ERROR_DRC_FORMAT_MISMATCH,
|
||||
IS_ERROR_DRC_WIDTH_MISMATCH,
|
||||
IS_ERROR_DRC_HEIGHT_MISMATCH,
|
||||
IS_ERROR_DRC_BITWIDTH_MISMATCH,
|
||||
IS_ERROR_DRC_FRAME_END_TIME_OUT,
|
||||
|
||||
/* SCALERC 400 ~ 499 */
|
||||
IS_ERROR_SCALERC_PWRDN_FAIL = 400,
|
||||
|
||||
/* ODC 500 ~ 599 */
|
||||
IS_ERROR_ODC_PWRDN_FAIL = 500,
|
||||
|
||||
/* DIS 600 ~ 699 */
|
||||
IS_ERROR_DIS_PWRDN_FAIL = 600,
|
||||
|
||||
/* TDNR 700 ~ 799 */
|
||||
IS_ERROR_TDNR_PWRDN_FAIL = 700,
|
||||
|
||||
/* SCALERC 800 ~ 899 */
|
||||
IS_ERROR_SCALERP_PWRDN_FAIL = 800,
|
||||
|
||||
/* FD 900 ~ 999 */
|
||||
IS_ERROR_FD_PWRDN_FAIL = 900,
|
||||
IS_ERROR_FD_MULTIPLE_INPUT,
|
||||
IS_ERROR_FD_ABSENT_INPUT,
|
||||
IS_ERROR_FD_NONADJACENT_INPUT,
|
||||
IS_ERROR_LHFD_FRAME_END_TIME_OUT,
|
||||
|
||||
IS_ERROR_UNKNOWN = 1000,
|
||||
};
|
||||
|
||||
#define IS_ERROR_TIME_OUT_FLAG 0x80000000
|
||||
|
||||
/* Set parameter error enum */
|
||||
enum fimc_is_error {
|
||||
/* Common error (0~99) */
|
||||
ERROR_COMMON_NONE = 0,
|
||||
ERROR_COMMON_CMD = 1, /* Invalid command */
|
||||
ERROR_COMMON_PARAMETER = 2, /* Invalid parameter */
|
||||
/* setfile is not loaded before adjusting */
|
||||
ERROR_COMMON_SETFILE_LOAD = 3,
|
||||
/* setfile is not Adjusted before runnng. */
|
||||
ERROR_COMMON_SETFILE_ADJUST = 4,
|
||||
/* Index of setfile is not valid (0~MAX_SETFILE_NUM-1) */
|
||||
ERROR_COMMON_SETFILE_INDEX = 5,
|
||||
/* Input path can be changed in ready state(stop) */
|
||||
ERROR_COMMON_INPUT_PATH = 6,
|
||||
/* IP can not start if input path is not set */
|
||||
ERROR_COMMON_INPUT_INIT = 7,
|
||||
/* Output path can be changed in ready state (stop) */
|
||||
ERROR_COMMON_OUTPUT_PATH = 8,
|
||||
/* IP can not start if output path is not set */
|
||||
ERROR_COMMON_OUTPUT_INIT = 9,
|
||||
|
||||
ERROR_CONTROL_NONE = ERROR_COMMON_NONE,
|
||||
ERROR_CONTROL_BYPASS = 11, /* Enable or Disable */
|
||||
|
||||
ERROR_OTF_INPUT_NONE = ERROR_COMMON_NONE,
|
||||
ERROR_OTF_INPUT_CMD = 21,
|
||||
/* invalid format (DRC: YUV444, FD: YUV444, 422, 420) */
|
||||
ERROR_OTF_INPUT_FORMAT = 22,
|
||||
/* invalid width (DRC: 128~8192, FD: 32~8190) */
|
||||
ERROR_OTF_INPUT_WIDTH = 23,
|
||||
/* invalid height (DRC: 64~8192, FD: 16~8190) */
|
||||
ERROR_OTF_INPUT_HEIGHT = 24,
|
||||
/* invalid bit-width (DRC: 8~12bits, FD: 8bit) */
|
||||
ERROR_OTF_INPUT_BIT_WIDTH = 25,
|
||||
/* invalid FrameTime for ISP */
|
||||
ERROR_OTF_INPUT_USER_FRAMETIIME = 26,
|
||||
|
||||
ERROR_DMA_INPUT_NONE = ERROR_COMMON_NONE,
|
||||
/* invalid width (DRC: 128~8192, FD: 32~8190) */
|
||||
ERROR_DMA_INPUT_WIDTH = 31,
|
||||
/* invalid height (DRC: 64~8192, FD: 16~8190) */
|
||||
ERROR_DMA_INPUT_HEIGHT = 32,
|
||||
/* invalid format (DRC: YUV444 or YUV422, FD: YUV444, 422, 420) */
|
||||
ERROR_DMA_INPUT_FORMAT = 33,
|
||||
/* invalid bit-width (DRC: 8~12bit, FD: 8bit) */
|
||||
ERROR_DMA_INPUT_BIT_WIDTH = 34,
|
||||
/* invalid order(DRC: YYCbCrorYCbYCr, FD:NO,YYCbCr,YCbYCr,CbCr,CrCb) */
|
||||
ERROR_DMA_INPUT_ORDER = 35,
|
||||
/* invalid palne (DRC: 3, FD: 1, 2, 3) */
|
||||
ERROR_DMA_INPUT_PLANE = 36,
|
||||
|
||||
ERROR_OTF_OUTPUT_NONE = ERROR_COMMON_NONE,
|
||||
/* invalid width (DRC: 128~8192) */
|
||||
ERROR_OTF_OUTPUT_WIDTH = 41,
|
||||
/* invalid height (DRC: 64~8192) */
|
||||
ERROR_OTF_OUTPUT_HEIGHT = 42,
|
||||
/* invalid format (DRC: YUV444) */
|
||||
ERROR_OTF_OUTPUT_FORMAT = 43,
|
||||
/* invalid bit-width (DRC: 8~12bits) */
|
||||
ERROR_OTF_OUTPUT_BIT_WIDTH = 44,
|
||||
|
||||
ERROR_DMA_OUTPUT_NONE = ERROR_COMMON_NONE,
|
||||
ERROR_DMA_OUTPUT_WIDTH = 51, /* invalid width */
|
||||
ERROR_DMA_OUTPUT_HEIGHT = 52, /* invalid height */
|
||||
ERROR_DMA_OUTPUT_FORMAT = 53, /* invalid format */
|
||||
ERROR_DMA_OUTPUT_BIT_WIDTH = 54, /* invalid bit-width */
|
||||
ERROR_DMA_OUTPUT_PLANE = 55, /* invalid plane */
|
||||
ERROR_DMA_OUTPUT_ORDER = 56, /* invalid order */
|
||||
|
||||
ERROR_GLOBAL_SHOTMODE_NONE = ERROR_COMMON_NONE,
|
||||
|
||||
/* SENSOR Error(100~199) */
|
||||
ERROR_SENSOR_NONE = ERROR_COMMON_NONE,
|
||||
ERROR_SENSOR_I2C_FAIL = 101,
|
||||
ERROR_SENSOR_INVALID_FRAMERATE,
|
||||
ERROR_SENSOR_INVALID_EXPOSURETIME,
|
||||
ERROR_SENSOR_INVALID_SIZE,
|
||||
ERROR_SENSOR_INVALID_SETTING,
|
||||
ERROR_SENSOR_ACTURATOR_INIT_FAIL,
|
||||
ERROR_SENSOR_INVALID_AF_POS,
|
||||
ERROR_SENSOR_UNSUPPORT_FUNC,
|
||||
ERROR_SENSOR_UNSUPPORT_PERI,
|
||||
ERROR_SENSOR_UNSUPPORT_AF,
|
||||
|
||||
/* ISP Error (200~299) */
|
||||
ERROR_ISP_AF_NONE = ERROR_COMMON_NONE,
|
||||
ERROR_ISP_AF_BUSY = 201,
|
||||
ERROR_ISP_AF_INVALID_COMMAND = 202,
|
||||
ERROR_ISP_AF_INVALID_MODE = 203,
|
||||
ERROR_ISP_FLASH_NONE = ERROR_COMMON_NONE,
|
||||
ERROR_ISP_AWB_NONE = ERROR_COMMON_NONE,
|
||||
ERROR_ISP_IMAGE_EFFECT_NONE = ERROR_COMMON_NONE,
|
||||
ERROR_ISP_ISO_NONE = ERROR_COMMON_NONE,
|
||||
ERROR_ISP_ADJUST_NONE = ERROR_COMMON_NONE,
|
||||
ERROR_ISP_METERING_NONE = ERROR_COMMON_NONE,
|
||||
ERROR_ISP_AFC_NONE = ERROR_COMMON_NONE,
|
||||
|
||||
/* DRC Error (300~399) */
|
||||
|
||||
/* FD Error (400~499) */
|
||||
ERROR_FD_NONE = ERROR_COMMON_NONE,
|
||||
/* Invalid max number (1~16) */
|
||||
ERROR_FD_CONFIG_MAX_NUMBER_STATE = 401,
|
||||
ERROR_FD_CONFIG_MAX_NUMBER_INVALID = 402,
|
||||
ERROR_FD_CONFIG_YAW_ANGLE_STATE = 403,
|
||||
ERROR_FD_CONFIG_YAW_ANGLE_INVALID = 404,
|
||||
ERROR_FD_CONFIG_ROLL_ANGLE_STATE = 405,
|
||||
ERROR_FD_CONFIG_ROLL_ANGLE_INVALID = 406,
|
||||
ERROR_FD_CONFIG_SMILE_MODE_INVALID = 407,
|
||||
ERROR_FD_CONFIG_BLINK_MODE_INVALID = 408,
|
||||
ERROR_FD_CONFIG_EYES_DETECT_INVALID = 409,
|
||||
ERROR_FD_CONFIG_MOUTH_DETECT_INVALID = 410,
|
||||
ERROR_FD_CONFIG_ORIENTATION_STATE = 411,
|
||||
ERROR_FD_CONFIG_ORIENTATION_INVALID = 412,
|
||||
ERROR_FD_CONFIG_ORIENTATION_VALUE_INVALID = 413,
|
||||
/* PARAM_FdResultStr can be only applied in ready-state or stream off */
|
||||
ERROR_FD_RESULT = 414,
|
||||
/* PARAM_FdModeStr can be only applied in ready-state or stream off */
|
||||
ERROR_FD_MODE = 415,
|
||||
/* Scaler Error (500 ~ 599) */
|
||||
ERROR_SCALER_NO_NONE = ERROR_COMMON_NONE,
|
||||
ERROR_SCALER_DMA_OUTSEL = 501,
|
||||
ERROR_SCALER_H_RATIO = 502,
|
||||
ERROR_SCALER_V_RATIO = 503,
|
||||
|
||||
ERROR_SCALER_IMAGE_EFFECT = 510,
|
||||
|
||||
ERROR_SCALER_ROTATE = 520,
|
||||
ERROR_SCALER_FLIP = 521,
|
||||
};
|
||||
|
||||
const char * const fimc_is_strerr(unsigned int error);
|
||||
const char * const fimc_is_param_strerr(unsigned int error);
|
||||
|
||||
#endif /* FIMC_IS_ERR_H_ */
|
||||
|
|
@ -0,0 +1,242 @@
|
|||
/*
|
||||
* Samsung EXYNOS4x12 FIMC-IS (Imaging Subsystem) driver
|
||||
*
|
||||
* Copyright (C) 2012 - 2013 Samsung Electronics Co., Ltd.
|
||||
*
|
||||
* Authors: Younghwan Joo <yhwan.joo@samsung.com>
|
||||
* Sylwester Nawrocki <s.nawrocki@samsung.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
#include <linux/delay.h>
|
||||
|
||||
#include "fimc-is.h"
|
||||
#include "fimc-is-command.h"
|
||||
#include "fimc-is-regs.h"
|
||||
#include "fimc-is-sensor.h"
|
||||
|
||||
void fimc_is_fw_clear_irq1(struct fimc_is *is, unsigned int nr)
|
||||
{
|
||||
mcuctl_write(1UL << nr, is, MCUCTL_REG_INTCR1);
|
||||
}
|
||||
|
||||
void fimc_is_fw_clear_irq2(struct fimc_is *is)
|
||||
{
|
||||
u32 cfg = mcuctl_read(is, MCUCTL_REG_INTSR2);
|
||||
mcuctl_write(cfg, is, MCUCTL_REG_INTCR2);
|
||||
}
|
||||
|
||||
void fimc_is_hw_set_intgr0_gd0(struct fimc_is *is)
|
||||
{
|
||||
mcuctl_write(INTGR0_INTGD(0), is, MCUCTL_REG_INTGR0);
|
||||
}
|
||||
|
||||
int fimc_is_hw_wait_intsr0_intsd0(struct fimc_is *is)
|
||||
{
|
||||
unsigned int timeout = 2000;
|
||||
u32 cfg, status;
|
||||
|
||||
cfg = mcuctl_read(is, MCUCTL_REG_INTSR0);
|
||||
status = INTSR0_GET_INTSD(0, cfg);
|
||||
|
||||
while (status) {
|
||||
cfg = mcuctl_read(is, MCUCTL_REG_INTSR0);
|
||||
status = INTSR0_GET_INTSD(0, cfg);
|
||||
if (timeout == 0) {
|
||||
dev_warn(&is->pdev->dev, "%s timeout\n",
|
||||
__func__);
|
||||
return -ETIME;
|
||||
}
|
||||
timeout--;
|
||||
udelay(1);
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
int fimc_is_hw_wait_intmsr0_intmsd0(struct fimc_is *is)
|
||||
{
|
||||
unsigned int timeout = 2000;
|
||||
u32 cfg, status;
|
||||
|
||||
cfg = mcuctl_read(is, MCUCTL_REG_INTMSR0);
|
||||
status = INTMSR0_GET_INTMSD(0, cfg);
|
||||
|
||||
while (status) {
|
||||
cfg = mcuctl_read(is, MCUCTL_REG_INTMSR0);
|
||||
status = INTMSR0_GET_INTMSD(0, cfg);
|
||||
if (timeout == 0) {
|
||||
dev_warn(&is->pdev->dev, "%s timeout\n",
|
||||
__func__);
|
||||
return -ETIME;
|
||||
}
|
||||
timeout--;
|
||||
udelay(1);
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
int fimc_is_hw_set_param(struct fimc_is *is)
|
||||
{
|
||||
struct is_config_param *cfg = &is->cfg_param[is->scenario_id];
|
||||
|
||||
fimc_is_hw_wait_intmsr0_intmsd0(is);
|
||||
|
||||
mcuctl_write(HIC_SET_PARAMETER, is, MCUCTL_REG_ISSR(0));
|
||||
mcuctl_write(is->sensor_index, is, MCUCTL_REG_ISSR(1));
|
||||
mcuctl_write(is->scenario_id, is, MCUCTL_REG_ISSR(2));
|
||||
|
||||
mcuctl_write(atomic_read(&cfg->p_region_num), is, MCUCTL_REG_ISSR(3));
|
||||
mcuctl_write(cfg->p_region_index1, is, MCUCTL_REG_ISSR(4));
|
||||
mcuctl_write(cfg->p_region_index2, is, MCUCTL_REG_ISSR(5));
|
||||
|
||||
fimc_is_hw_set_intgr0_gd0(is);
|
||||
return 0;
|
||||
}
|
||||
|
||||
int fimc_is_hw_set_tune(struct fimc_is *is)
|
||||
{
|
||||
fimc_is_hw_wait_intmsr0_intmsd0(is);
|
||||
|
||||
mcuctl_write(HIC_SET_TUNE, is, MCUCTL_REG_ISSR(0));
|
||||
mcuctl_write(is->sensor_index, is, MCUCTL_REG_ISSR(1));
|
||||
mcuctl_write(is->h2i_cmd.entry_id, is, MCUCTL_REG_ISSR(2));
|
||||
|
||||
fimc_is_hw_set_intgr0_gd0(is);
|
||||
return 0;
|
||||
}
|
||||
|
||||
#define FIMC_IS_MAX_PARAMS 4
|
||||
|
||||
int fimc_is_hw_get_params(struct fimc_is *is, unsigned int num_args)
|
||||
{
|
||||
int i;
|
||||
|
||||
if (num_args > FIMC_IS_MAX_PARAMS)
|
||||
return -EINVAL;
|
||||
|
||||
is->i2h_cmd.num_args = num_args;
|
||||
|
||||
for (i = 0; i < FIMC_IS_MAX_PARAMS; i++) {
|
||||
if (i < num_args)
|
||||
is->i2h_cmd.args[i] = mcuctl_read(is,
|
||||
MCUCTL_REG_ISSR(12 + i));
|
||||
else
|
||||
is->i2h_cmd.args[i] = 0;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
void fimc_is_hw_set_sensor_num(struct fimc_is *is)
|
||||
{
|
||||
pr_debug("setting sensor index to: %d\n", is->sensor_index);
|
||||
|
||||
mcuctl_write(IH_REPLY_DONE, is, MCUCTL_REG_ISSR(0));
|
||||
mcuctl_write(is->sensor_index, is, MCUCTL_REG_ISSR(1));
|
||||
mcuctl_write(IHC_GET_SENSOR_NUM, is, MCUCTL_REG_ISSR(2));
|
||||
mcuctl_write(FIMC_IS_SENSOR_NUM, is, MCUCTL_REG_ISSR(3));
|
||||
}
|
||||
|
||||
void fimc_is_hw_close_sensor(struct fimc_is *is, unsigned int index)
|
||||
{
|
||||
if (is->sensor_index != index)
|
||||
return;
|
||||
|
||||
fimc_is_hw_wait_intmsr0_intmsd0(is);
|
||||
mcuctl_write(HIC_CLOSE_SENSOR, is, MCUCTL_REG_ISSR(0));
|
||||
mcuctl_write(is->sensor_index, is, MCUCTL_REG_ISSR(1));
|
||||
mcuctl_write(is->sensor_index, is, MCUCTL_REG_ISSR(2));
|
||||
fimc_is_hw_set_intgr0_gd0(is);
|
||||
}
|
||||
|
||||
void fimc_is_hw_get_setfile_addr(struct fimc_is *is)
|
||||
{
|
||||
fimc_is_hw_wait_intmsr0_intmsd0(is);
|
||||
mcuctl_write(HIC_GET_SET_FILE_ADDR, is, MCUCTL_REG_ISSR(0));
|
||||
mcuctl_write(is->sensor_index, is, MCUCTL_REG_ISSR(1));
|
||||
fimc_is_hw_set_intgr0_gd0(is);
|
||||
}
|
||||
|
||||
void fimc_is_hw_load_setfile(struct fimc_is *is)
|
||||
{
|
||||
fimc_is_hw_wait_intmsr0_intmsd0(is);
|
||||
mcuctl_write(HIC_LOAD_SET_FILE, is, MCUCTL_REG_ISSR(0));
|
||||
mcuctl_write(is->sensor_index, is, MCUCTL_REG_ISSR(1));
|
||||
fimc_is_hw_set_intgr0_gd0(is);
|
||||
}
|
||||
|
||||
int fimc_is_hw_change_mode(struct fimc_is *is)
|
||||
{
|
||||
const u8 cmd[] = {
|
||||
HIC_PREVIEW_STILL, HIC_PREVIEW_VIDEO,
|
||||
HIC_CAPTURE_STILL, HIC_CAPTURE_VIDEO,
|
||||
};
|
||||
|
||||
if (WARN_ON(is->scenario_id > ARRAY_SIZE(cmd)))
|
||||
return -EINVAL;
|
||||
|
||||
mcuctl_write(cmd[is->scenario_id], is, MCUCTL_REG_ISSR(0));
|
||||
mcuctl_write(is->sensor_index, is, MCUCTL_REG_ISSR(1));
|
||||
mcuctl_write(is->setfile.sub_index, is, MCUCTL_REG_ISSR(2));
|
||||
fimc_is_hw_set_intgr0_gd0(is);
|
||||
return 0;
|
||||
}
|
||||
|
||||
void fimc_is_hw_stream_on(struct fimc_is *is)
|
||||
{
|
||||
fimc_is_hw_wait_intmsr0_intmsd0(is);
|
||||
mcuctl_write(HIC_STREAM_ON, is, MCUCTL_REG_ISSR(0));
|
||||
mcuctl_write(is->sensor_index, is, MCUCTL_REG_ISSR(1));
|
||||
mcuctl_write(0, is, MCUCTL_REG_ISSR(2));
|
||||
fimc_is_hw_set_intgr0_gd0(is);
|
||||
}
|
||||
|
||||
void fimc_is_hw_stream_off(struct fimc_is *is)
|
||||
{
|
||||
fimc_is_hw_wait_intmsr0_intmsd0(is);
|
||||
mcuctl_write(HIC_STREAM_OFF, is, MCUCTL_REG_ISSR(0));
|
||||
mcuctl_write(is->sensor_index, is, MCUCTL_REG_ISSR(1));
|
||||
fimc_is_hw_set_intgr0_gd0(is);
|
||||
}
|
||||
|
||||
void fimc_is_hw_subip_power_off(struct fimc_is *is)
|
||||
{
|
||||
fimc_is_hw_wait_intmsr0_intmsd0(is);
|
||||
mcuctl_write(HIC_POWER_DOWN, is, MCUCTL_REG_ISSR(0));
|
||||
mcuctl_write(is->sensor_index, is, MCUCTL_REG_ISSR(1));
|
||||
fimc_is_hw_set_intgr0_gd0(is);
|
||||
}
|
||||
|
||||
int fimc_is_itf_s_param(struct fimc_is *is, bool update)
|
||||
{
|
||||
int ret;
|
||||
|
||||
if (update)
|
||||
__is_hw_update_params(is);
|
||||
|
||||
fimc_is_mem_barrier();
|
||||
|
||||
clear_bit(IS_ST_BLOCK_CMD_CLEARED, &is->state);
|
||||
fimc_is_hw_set_param(is);
|
||||
ret = fimc_is_wait_event(is, IS_ST_BLOCK_CMD_CLEARED, 1,
|
||||
FIMC_IS_CONFIG_TIMEOUT);
|
||||
if (ret < 0)
|
||||
dev_err(&is->pdev->dev, "%s() timeout\n", __func__);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
int fimc_is_itf_mode_change(struct fimc_is *is)
|
||||
{
|
||||
int ret;
|
||||
|
||||
clear_bit(IS_ST_CHANGE_MODE, &is->state);
|
||||
fimc_is_hw_change_mode(is);
|
||||
ret = fimc_is_wait_event(is, IS_ST_CHANGE_MODE, 1,
|
||||
FIMC_IS_CONFIG_TIMEOUT);
|
||||
if (!ret < 0)
|
||||
dev_err(&is->pdev->dev, "%s(): mode change (%d) timeout\n",
|
||||
__func__, is->scenario_id);
|
||||
return ret;
|
||||
}
|
||||
|
|
@ -0,0 +1,164 @@
|
|||
/*
|
||||
* Samsung EXYNOS4x12 FIMC-IS (Imaging Subsystem) driver
|
||||
*
|
||||
* Copyright (C) 2013 Samsung Electronics Co., Ltd.
|
||||
*
|
||||
* Authors: Sylwester Nawrocki <s.nawrocki@samsung.com>
|
||||
* Younghwan Joo <yhwan.joo@samsung.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
#ifndef FIMC_IS_REG_H_
|
||||
#define FIMC_IS_REG_H_
|
||||
|
||||
/* WDT_ISP register */
|
||||
#define REG_WDT_ISP 0x00170000
|
||||
|
||||
/* MCUCTL registers base offset */
|
||||
#define MCUCTL_BASE 0x00180000
|
||||
|
||||
/* MCU Controller Register */
|
||||
#define MCUCTL_REG_MCUCTRL (MCUCTL_BASE + 0x00)
|
||||
#define MCUCTRL_MSWRST (1 << 0)
|
||||
|
||||
/* Boot Base Offset Address Register */
|
||||
#define MCUCTL_REG_BBOAR (MCUCTL_BASE + 0x04)
|
||||
|
||||
/* Interrupt Generation Register 0 from Host CPU to VIC */
|
||||
#define MCUCTL_REG_INTGR0 (MCUCTL_BASE + 0x08)
|
||||
/* __n = 0...9 */
|
||||
#define INTGR0_INTGC(__n) (1 << ((__n) + 16))
|
||||
/* __n = 0...5 */
|
||||
#define INTGR0_INTGD(__n) (1 << (__n))
|
||||
|
||||
/* Interrupt Clear Register 0 from Host CPU to VIC */
|
||||
#define MCUCTL_REG_INTCR0 (MCUCTL_BASE + 0x0c)
|
||||
/* __n = 0...9 */
|
||||
#define INTCR0_INTGC(__n) (1 << ((__n) + 16))
|
||||
/* __n = 0...5 */
|
||||
#define INTCR0_INTCD(__n) (1 << ((__n) + 16))
|
||||
|
||||
/* Interrupt Mask Register 0 from Host CPU to VIC */
|
||||
#define MCUCTL_REG_INTMR0 (MCUCTL_BASE + 0x10)
|
||||
/* __n = 0...9 */
|
||||
#define INTMR0_INTMC(__n) (1 << ((__n) + 16))
|
||||
/* __n = 0...5 */
|
||||
#define INTMR0_INTMD(__n) (1 << (__n))
|
||||
|
||||
/* Interrupt Status Register 0 from Host CPU to VIC */
|
||||
#define MCUCTL_REG_INTSR0 (MCUCTL_BASE + 0x14)
|
||||
/* __n (bit number) = 0...4 */
|
||||
#define INTSR0_GET_INTSD(x, __n) (((x) >> (__n)) & 0x1)
|
||||
/* __n (bit number) = 0...9 */
|
||||
#define INTSR0_GET_INTSC(x, __n) (((x) >> ((__n) + 16)) & 0x1)
|
||||
|
||||
/* Interrupt Mask Status Register 0 from Host CPU to VIC */
|
||||
#define MCUCTL_REG_INTMSR0 (MCUCTL_BASE + 0x18)
|
||||
/* __n (bit number) = 0...4 */
|
||||
#define INTMSR0_GET_INTMSD(x, __n) (((x) >> (__n)) & 0x1)
|
||||
/* __n (bit number) = 0...9 */
|
||||
#define INTMSR0_GET_INTMSC(x, __n) (((x) >> ((__n) + 16)) & 0x1)
|
||||
|
||||
/* Interrupt Generation Register 1 from ISP CPU to Host IC */
|
||||
#define MCUCTL_REG_INTGR1 (MCUCTL_BASE + 0x1c)
|
||||
/* __n = 0...9 */
|
||||
#define INTGR1_INTGC(__n) (1 << (__n))
|
||||
|
||||
/* Interrupt Clear Register 1 from ISP CPU to Host IC */
|
||||
#define MCUCTL_REG_INTCR1 (MCUCTL_BASE + 0x20)
|
||||
/* __n = 0...9 */
|
||||
#define INTCR1_INTCC(__n) (1 << (__n))
|
||||
|
||||
/* Interrupt Mask Register 1 from ISP CPU to Host IC */
|
||||
#define MCUCTL_REG_INTMR1 (MCUCTL_BASE + 0x24)
|
||||
/* __n = 0...9 */
|
||||
#define INTMR1_INTMC(__n) (1 << (__n))
|
||||
|
||||
/* Interrupt Status Register 1 from ISP CPU to Host IC */
|
||||
#define MCUCTL_REG_INTSR1 (MCUCTL_BASE + 0x28)
|
||||
/* Interrupt Mask Status Register 1 from ISP CPU to Host IC */
|
||||
#define MCUCTL_REG_INTMSR1 (MCUCTL_BASE + 0x2c)
|
||||
|
||||
/* Interrupt Clear Register 2 from ISP BLK's interrupts to Host IC */
|
||||
#define MCUCTL_REG_INTCR2 (MCUCTL_BASE + 0x30)
|
||||
/* __n = 0...5 */
|
||||
#define INTCR2_INTCC(__n) (1 << ((__n) + 16))
|
||||
|
||||
/* Interrupt Mask Register 2 from ISP BLK's interrupts to Host IC */
|
||||
#define MCUCTL_REG_INTMR2 (MCUCTL_BASE + 0x34)
|
||||
/* __n = 0...25 */
|
||||
#define INTMR2_INTMCIS(__n) (1 << (__n))
|
||||
|
||||
/* Interrupt Status Register 2 from ISP BLK's interrupts to Host IC */
|
||||
#define MCUCTL_REG_INTSR2 (MCUCTL_BASE + 0x38)
|
||||
/* Interrupt Mask Status Register 2 from ISP BLK's interrupts to Host IC */
|
||||
#define MCUCTL_REG_INTMSR2 (MCUCTL_BASE + 0x3c)
|
||||
|
||||
/* General Purpose Output Control Register (0~17) */
|
||||
#define MCUCTL_REG_GPOCTLR (MCUCTL_BASE + 0x40)
|
||||
/* __n = 0...17 */
|
||||
#define GPOCTLR_GPOG(__n) (1 << (__n))
|
||||
|
||||
/* General Purpose Pad Output Enable Register (0~17) */
|
||||
#define MCUCTL_REG_GPOENCTLR (MCUCTL_BASE + 0x44)
|
||||
/* __n = 0...17 */
|
||||
#define GPOENCTLR_GPOEN(__n) (1 << (__n))
|
||||
|
||||
/* General Purpose Input Control Register (0~17) */
|
||||
#define MCUCTL_REG_GPICTLR (MCUCTL_BASE + 0x48)
|
||||
|
||||
/* Shared registers between ISP CPU and the host CPU - ISSRxx */
|
||||
|
||||
/* ISSR(1): Command Host -> IS */
|
||||
/* ISSR(1): Sensor ID for Command, ISSR2...5 = Parameter 1...4 */
|
||||
|
||||
/* ISSR(10): Reply IS -> Host */
|
||||
/* ISSR(11): Sensor ID for Reply, ISSR12...15 = Parameter 1...4 */
|
||||
|
||||
/* ISSR(20): ISP_FRAME_DONE : SENSOR ID */
|
||||
/* ISSR(21): ISP_FRAME_DONE : PARAMETER 1 */
|
||||
|
||||
/* ISSR(24): SCALERC_FRAME_DONE : SENSOR ID */
|
||||
/* ISSR(25): SCALERC_FRAME_DONE : PARAMETER 1 */
|
||||
|
||||
/* ISSR(28): 3DNR_FRAME_DONE : SENSOR ID */
|
||||
/* ISSR(29): 3DNR_FRAME_DONE : PARAMETER 1 */
|
||||
|
||||
/* ISSR(32): SCALERP_FRAME_DONE : SENSOR ID */
|
||||
/* ISSR(33): SCALERP_FRAME_DONE : PARAMETER 1 */
|
||||
|
||||
/* __n = 0...63 */
|
||||
#define MCUCTL_REG_ISSR(__n) (MCUCTL_BASE + 0x80 + ((__n) * 4))
|
||||
|
||||
/* PMU ISP register offsets */
|
||||
#define REG_CMU_RESET_ISP_SYS_PWR_REG 0x1174
|
||||
#define REG_CMU_SYSCLK_ISP_SYS_PWR_REG 0x13b8
|
||||
#define REG_PMU_ISP_ARM_SYS 0x1050
|
||||
#define REG_PMU_ISP_ARM_CONFIGURATION 0x2280
|
||||
#define REG_PMU_ISP_ARM_STATUS 0x2284
|
||||
#define REG_PMU_ISP_ARM_OPTION 0x2288
|
||||
|
||||
void fimc_is_fw_clear_irq1(struct fimc_is *is, unsigned int bit);
|
||||
void fimc_is_fw_clear_irq2(struct fimc_is *is);
|
||||
int fimc_is_hw_get_params(struct fimc_is *is, unsigned int num);
|
||||
|
||||
void fimc_is_hw_set_intgr0_gd0(struct fimc_is *is);
|
||||
int fimc_is_hw_wait_intsr0_intsd0(struct fimc_is *is);
|
||||
int fimc_is_hw_wait_intmsr0_intmsd0(struct fimc_is *is);
|
||||
void fimc_is_hw_set_sensor_num(struct fimc_is *is);
|
||||
void fimc_is_hw_stream_on(struct fimc_is *is);
|
||||
void fimc_is_hw_stream_off(struct fimc_is *is);
|
||||
int fimc_is_hw_set_param(struct fimc_is *is);
|
||||
int fimc_is_hw_change_mode(struct fimc_is *is);
|
||||
|
||||
void fimc_is_hw_close_sensor(struct fimc_is *is, unsigned int index);
|
||||
void fimc_is_hw_get_setfile_addr(struct fimc_is *is);
|
||||
void fimc_is_hw_load_setfile(struct fimc_is *is);
|
||||
void fimc_is_hw_subip_power_off(struct fimc_is *is);
|
||||
|
||||
int fimc_is_itf_s_param(struct fimc_is *is, bool update);
|
||||
int fimc_is_itf_mode_change(struct fimc_is *is);
|
||||
|
||||
#endif /* FIMC_IS_REG_H_ */
|
||||
Разница между файлами не показана из-за своего большого размера
Загрузить разницу
|
|
@ -0,0 +1,345 @@
|
|||
/*
|
||||
* Samsung EXYNOS4x12 FIMC-IS (Imaging Subsystem) driver
|
||||
*
|
||||
* Copyright (C) 2013 Samsung Electronics Co., Ltd.
|
||||
*
|
||||
* Authors: Younghwan Joo <yhwan.joo@samsung.com>
|
||||
* Sylwester Nawrocki <s.nawrocki@samsung.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
#ifndef FIMC_IS_H_
|
||||
#define FIMC_IS_H_
|
||||
|
||||
#include <asm/barrier.h>
|
||||
#include <linux/clk.h>
|
||||
#include <linux/device.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/pinctrl/consumer.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/sizes.h>
|
||||
#include <linux/spinlock.h>
|
||||
#include <linux/types.h>
|
||||
#include <media/videobuf2-core.h>
|
||||
#include <media/v4l2-ctrls.h>
|
||||
|
||||
#include "fimc-isp.h"
|
||||
#include "fimc-is-command.h"
|
||||
#include "fimc-is-sensor.h"
|
||||
#include "fimc-is-param.h"
|
||||
#include "fimc-is-regs.h"
|
||||
|
||||
#define FIMC_IS_DRV_NAME "exynos4-fimc-is"
|
||||
|
||||
#define FIMC_IS_FW_FILENAME "fimc_is_fw.bin"
|
||||
#define FIMC_IS_SETFILE_6A3 "setfile.bin"
|
||||
|
||||
#define FIMC_IS_FW_LOAD_TIMEOUT 1000 /* ms */
|
||||
#define FIMC_IS_POWER_ON_TIMEOUT 1000 /* us */
|
||||
|
||||
#define FIMC_IS_SENSOR_NUM 2
|
||||
|
||||
/* Memory definitions */
|
||||
#define FIMC_IS_CPU_MEM_SIZE (0xa00000)
|
||||
#define FIMC_IS_CPU_BASE_MASK ((1 << 26) - 1)
|
||||
#define FIMC_IS_REGION_SIZE 0x5000
|
||||
|
||||
#define FIMC_IS_DEBUG_REGION_OFFSET 0x0084b000
|
||||
#define FIMC_IS_SHARED_REGION_OFFSET 0x008c0000
|
||||
#define FIMC_IS_FW_INFO_LEN 31
|
||||
#define FIMC_IS_FW_VER_LEN 7
|
||||
#define FIMC_IS_FW_DESC_LEN (FIMC_IS_FW_INFO_LEN + \
|
||||
FIMC_IS_FW_VER_LEN)
|
||||
#define FIMC_IS_SETFILE_INFO_LEN 39
|
||||
|
||||
#define FIMC_IS_EXTRA_MEM_SIZE (FIMC_IS_EXTRA_FW_SIZE + \
|
||||
FIMC_IS_EXTRA_SETFILE_SIZE + 0x1000)
|
||||
#define FIMC_IS_EXTRA_FW_SIZE 0x180000
|
||||
#define FIMC_IS_EXTRA_SETFILE_SIZE 0x4b000
|
||||
|
||||
/* TODO: revisit */
|
||||
#define FIMC_IS_FW_ADDR_MASK ((1 << 26) - 1)
|
||||
#define FIMC_IS_FW_SIZE_MAX (SZ_4M)
|
||||
#define FIMC_IS_FW_SIZE_MIN (SZ_32K)
|
||||
|
||||
#define ATCLK_MCUISP_FREQUENCY 100000000UL
|
||||
#define ACLK_AXI_FREQUENCY 100000000UL
|
||||
|
||||
enum {
|
||||
ISS_CLK_PPMUISPX,
|
||||
ISS_CLK_PPMUISPMX,
|
||||
ISS_CLK_LITE0,
|
||||
ISS_CLK_LITE1,
|
||||
ISS_CLK_MPLL,
|
||||
ISS_CLK_SYSREG,
|
||||
ISS_CLK_ISP,
|
||||
ISS_CLK_DRC,
|
||||
ISS_CLK_FD,
|
||||
ISS_CLK_MCUISP,
|
||||
ISS_CLK_UART,
|
||||
ISS_GATE_CLKS_MAX,
|
||||
ISS_CLK_ISP_DIV0 = ISS_GATE_CLKS_MAX,
|
||||
ISS_CLK_ISP_DIV1,
|
||||
ISS_CLK_MCUISP_DIV0,
|
||||
ISS_CLK_MCUISP_DIV1,
|
||||
ISS_CLK_ACLK200,
|
||||
ISS_CLK_ACLK200_DIV,
|
||||
ISS_CLK_ACLK400MCUISP,
|
||||
ISS_CLK_ACLK400MCUISP_DIV,
|
||||
ISS_CLKS_MAX
|
||||
};
|
||||
|
||||
/* The driver's internal state flags */
|
||||
enum {
|
||||
IS_ST_IDLE,
|
||||
IS_ST_PWR_ON,
|
||||
IS_ST_A5_PWR_ON,
|
||||
IS_ST_FW_LOADED,
|
||||
IS_ST_OPEN_SENSOR,
|
||||
IS_ST_SETFILE_LOADED,
|
||||
IS_ST_INIT_DONE,
|
||||
IS_ST_STREAM_ON,
|
||||
IS_ST_STREAM_OFF,
|
||||
IS_ST_CHANGE_MODE,
|
||||
IS_ST_BLOCK_CMD_CLEARED,
|
||||
IS_ST_SET_ZOOM,
|
||||
IS_ST_PWR_SUBIP_ON,
|
||||
IS_ST_END,
|
||||
};
|
||||
|
||||
enum af_state {
|
||||
FIMC_IS_AF_IDLE = 0,
|
||||
FIMC_IS_AF_SETCONFIG = 1,
|
||||
FIMC_IS_AF_RUNNING = 2,
|
||||
FIMC_IS_AF_LOCK = 3,
|
||||
FIMC_IS_AF_ABORT = 4,
|
||||
FIMC_IS_AF_FAILED = 5,
|
||||
};
|
||||
|
||||
enum af_lock_state {
|
||||
FIMC_IS_AF_UNLOCKED = 0,
|
||||
FIMC_IS_AF_LOCKED = 2
|
||||
};
|
||||
|
||||
enum ae_lock_state {
|
||||
FIMC_IS_AE_UNLOCKED = 0,
|
||||
FIMC_IS_AE_LOCKED = 1
|
||||
};
|
||||
|
||||
enum awb_lock_state {
|
||||
FIMC_IS_AWB_UNLOCKED = 0,
|
||||
FIMC_IS_AWB_LOCKED = 1
|
||||
};
|
||||
|
||||
enum {
|
||||
IS_METERING_CONFIG_CMD,
|
||||
IS_METERING_CONFIG_WIN_POS_X,
|
||||
IS_METERING_CONFIG_WIN_POS_Y,
|
||||
IS_METERING_CONFIG_WIN_WIDTH,
|
||||
IS_METERING_CONFIG_WIN_HEIGHT,
|
||||
IS_METERING_CONFIG_MAX
|
||||
};
|
||||
|
||||
struct is_setfile {
|
||||
const struct firmware *info;
|
||||
int state;
|
||||
u32 sub_index;
|
||||
u32 base;
|
||||
size_t size;
|
||||
};
|
||||
|
||||
struct is_fd_result_header {
|
||||
u32 offset;
|
||||
u32 count;
|
||||
u32 index;
|
||||
u32 curr_index;
|
||||
u32 width;
|
||||
u32 height;
|
||||
};
|
||||
|
||||
struct is_af_info {
|
||||
u16 mode;
|
||||
u32 af_state;
|
||||
u32 af_lock_state;
|
||||
u32 ae_lock_state;
|
||||
u32 awb_lock_state;
|
||||
u16 pos_x;
|
||||
u16 pos_y;
|
||||
u16 prev_pos_x;
|
||||
u16 prev_pos_y;
|
||||
u16 use_af;
|
||||
};
|
||||
|
||||
struct fimc_is_firmware {
|
||||
const struct firmware *f_w;
|
||||
|
||||
dma_addr_t paddr;
|
||||
void *vaddr;
|
||||
unsigned int size;
|
||||
|
||||
char info[FIMC_IS_FW_INFO_LEN + 1];
|
||||
char version[FIMC_IS_FW_VER_LEN + 1];
|
||||
char setfile_info[FIMC_IS_SETFILE_INFO_LEN + 1];
|
||||
u8 state;
|
||||
};
|
||||
|
||||
struct fimc_is_memory {
|
||||
/* physical base address */
|
||||
dma_addr_t paddr;
|
||||
/* virtual base address */
|
||||
void *vaddr;
|
||||
/* total length */
|
||||
unsigned int size;
|
||||
};
|
||||
|
||||
#define FIMC_IS_I2H_MAX_ARGS 12
|
||||
|
||||
struct i2h_cmd {
|
||||
u32 cmd;
|
||||
u32 sensor_id;
|
||||
u16 num_args;
|
||||
u32 args[FIMC_IS_I2H_MAX_ARGS];
|
||||
};
|
||||
|
||||
struct h2i_cmd {
|
||||
u16 cmd_type;
|
||||
u32 entry_id;
|
||||
};
|
||||
|
||||
#define FIMC_IS_DEBUG_MSG 0x3f
|
||||
#define FIMC_IS_DEBUG_LEVEL 3
|
||||
|
||||
struct fimc_is_setfile {
|
||||
const struct firmware *info;
|
||||
unsigned int state;
|
||||
unsigned int size;
|
||||
u32 sub_index;
|
||||
u32 base;
|
||||
};
|
||||
|
||||
struct is_config_param {
|
||||
struct global_param global;
|
||||
struct sensor_param sensor;
|
||||
struct isp_param isp;
|
||||
struct drc_param drc;
|
||||
struct fd_param fd;
|
||||
|
||||
atomic_t p_region_num;
|
||||
unsigned long p_region_index1;
|
||||
unsigned long p_region_index2;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct fimc_is - fimc-is data structure
|
||||
* @pdev: pointer to FIMC-IS platform device
|
||||
* @pctrl: pointer to pinctrl structure for this device
|
||||
* @v4l2_dev: pointer to top the level v4l2_device
|
||||
* @alloc_ctx: videobuf2 memory allocator context
|
||||
* @lock: mutex serializing video device and the subdev operations
|
||||
* @slock: spinlock protecting this data structure and the hw registers
|
||||
* @clocks: FIMC-LITE gate clock
|
||||
* @regs: MCUCTL mmapped registers region
|
||||
* @pmu_regs: PMU ISP mmapped registers region
|
||||
* @irq_queue: interrupt handling waitqueue
|
||||
* @lpm: low power mode flag
|
||||
* @state: internal driver's state flags
|
||||
*/
|
||||
struct fimc_is {
|
||||
struct platform_device *pdev;
|
||||
struct pinctrl *pctrl;
|
||||
struct v4l2_device *v4l2_dev;
|
||||
|
||||
struct fimc_is_firmware fw;
|
||||
struct fimc_is_memory memory;
|
||||
struct firmware *f_w;
|
||||
|
||||
struct fimc_isp isp;
|
||||
struct fimc_is_sensor *sensor;
|
||||
struct fimc_is_setfile setfile;
|
||||
|
||||
struct vb2_alloc_ctx *alloc_ctx;
|
||||
struct v4l2_ctrl_handler ctrl_handler;
|
||||
|
||||
struct mutex lock;
|
||||
spinlock_t slock;
|
||||
|
||||
struct clk *clocks[ISS_CLKS_MAX];
|
||||
bool clk_init;
|
||||
void __iomem *regs;
|
||||
void __iomem *pmu_regs;
|
||||
int irq;
|
||||
wait_queue_head_t irq_queue;
|
||||
u8 lpm;
|
||||
|
||||
unsigned long state;
|
||||
unsigned int sensor_index;
|
||||
|
||||
struct i2h_cmd i2h_cmd;
|
||||
struct h2i_cmd h2i_cmd;
|
||||
struct is_fd_result_header fd_header;
|
||||
|
||||
struct is_config_param cfg_param[IS_SC_MAX];
|
||||
struct is_region *is_p_region;
|
||||
dma_addr_t is_dma_p_region;
|
||||
struct is_share_region *is_shared_region;
|
||||
struct is_af_info af;
|
||||
u32 scenario_id;
|
||||
|
||||
struct dentry *debugfs_entry;
|
||||
};
|
||||
|
||||
static inline struct fimc_is *fimc_isp_to_is(struct fimc_isp *isp)
|
||||
{
|
||||
return container_of(isp, struct fimc_is, isp);
|
||||
}
|
||||
|
||||
static inline void fimc_is_mem_barrier(void)
|
||||
{
|
||||
mb();
|
||||
}
|
||||
|
||||
static inline void fimc_is_set_param_bit(struct fimc_is *is, int num)
|
||||
{
|
||||
struct is_config_param *cfg = &is->cfg_param[is->scenario_id];
|
||||
|
||||
if (num >= 32)
|
||||
set_bit(num - 32, &cfg->p_region_index2);
|
||||
else
|
||||
set_bit(num, &cfg->p_region_index1);
|
||||
}
|
||||
|
||||
static inline void fimc_is_set_param_ctrl_cmd(struct fimc_is *is, int cmd)
|
||||
{
|
||||
is->is_p_region->parameter.isp.control.cmd = cmd;
|
||||
}
|
||||
|
||||
static inline void mcuctl_write(u32 v, struct fimc_is *is, unsigned int offset)
|
||||
{
|
||||
writel(v, is->regs + offset);
|
||||
}
|
||||
|
||||
static inline u32 mcuctl_read(struct fimc_is *is, unsigned int offset)
|
||||
{
|
||||
return readl(is->regs + offset);
|
||||
}
|
||||
|
||||
static inline void pmuisp_write(u32 v, struct fimc_is *is, unsigned int offset)
|
||||
{
|
||||
writel(v, is->pmu_regs + offset);
|
||||
}
|
||||
|
||||
static inline u32 pmuisp_read(struct fimc_is *is, unsigned int offset)
|
||||
{
|
||||
return readl(is->pmu_regs + offset);
|
||||
}
|
||||
|
||||
int fimc_is_wait_event(struct fimc_is *is, unsigned long bit,
|
||||
unsigned int state, unsigned int timeout);
|
||||
int fimc_is_cpu_set_power(struct fimc_is *is, int on);
|
||||
int fimc_is_start_firmware(struct fimc_is *is);
|
||||
int fimc_is_hw_initialize(struct fimc_is *is);
|
||||
void fimc_is_log_dump(const char *level, const void *buf, size_t len);
|
||||
|
||||
#endif /* FIMC_IS_H_ */
|
||||
|
|
@ -0,0 +1,702 @@
|
|||
/*
|
||||
* Samsung EXYNOS4x12 FIMC-IS (Imaging Subsystem) driver
|
||||
*
|
||||
* Copyright (C) 2013 Samsung Electronics Co., Ltd.
|
||||
*
|
||||
* Authors: Sylwester Nawrocki <s.nawrocki@samsung.com>
|
||||
* Younghwan Joo <yhwan.joo@samsung.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
#define pr_fmt(fmt) "%s:%d " fmt, __func__, __LINE__
|
||||
|
||||
#include <linux/device.h>
|
||||
#include <linux/errno.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/list.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/printk.h>
|
||||
#include <linux/pm_runtime.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/types.h>
|
||||
#include <media/v4l2-device.h>
|
||||
|
||||
#include "media-dev.h"
|
||||
#include "fimc-is-command.h"
|
||||
#include "fimc-is-param.h"
|
||||
#include "fimc-is-regs.h"
|
||||
#include "fimc-is.h"
|
||||
|
||||
static int debug = 10;
|
||||
module_param_named(debug_isp, debug, int, S_IRUGO | S_IWUSR);
|
||||
|
||||
static const struct fimc_fmt fimc_isp_formats[FIMC_ISP_NUM_FORMATS] = {
|
||||
{
|
||||
.name = "RAW8 (GRBG)",
|
||||
.fourcc = V4L2_PIX_FMT_SGRBG8,
|
||||
.depth = { 8 },
|
||||
.color = FIMC_FMT_RAW8,
|
||||
.memplanes = 1,
|
||||
.mbus_code = V4L2_MBUS_FMT_SGRBG8_1X8,
|
||||
}, {
|
||||
.name = "RAW10 (GRBG)",
|
||||
.fourcc = V4L2_PIX_FMT_SGRBG10,
|
||||
.depth = { 10 },
|
||||
.color = FIMC_FMT_RAW10,
|
||||
.memplanes = 1,
|
||||
.mbus_code = V4L2_MBUS_FMT_SGRBG10_1X10,
|
||||
}, {
|
||||
.name = "RAW12 (GRBG)",
|
||||
.fourcc = V4L2_PIX_FMT_SGRBG12,
|
||||
.depth = { 12 },
|
||||
.color = FIMC_FMT_RAW12,
|
||||
.memplanes = 1,
|
||||
.mbus_code = V4L2_MBUS_FMT_SGRBG12_1X12,
|
||||
},
|
||||
};
|
||||
|
||||
/**
|
||||
* fimc_isp_find_format - lookup color format by fourcc or media bus code
|
||||
* @pixelformat: fourcc to match, ignored if null
|
||||
* @mbus_code: media bus code to match, ignored if null
|
||||
* @index: index to the fimc_isp_formats array, ignored if negative
|
||||
*/
|
||||
const struct fimc_fmt *fimc_isp_find_format(const u32 *pixelformat,
|
||||
const u32 *mbus_code, int index)
|
||||
{
|
||||
const struct fimc_fmt *fmt, *def_fmt = NULL;
|
||||
unsigned int i;
|
||||
int id = 0;
|
||||
|
||||
if (index >= (int)ARRAY_SIZE(fimc_isp_formats))
|
||||
return NULL;
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(fimc_isp_formats); ++i) {
|
||||
fmt = &fimc_isp_formats[i];
|
||||
if (pixelformat && fmt->fourcc == *pixelformat)
|
||||
return fmt;
|
||||
if (mbus_code && fmt->mbus_code == *mbus_code)
|
||||
return fmt;
|
||||
if (index == id)
|
||||
def_fmt = fmt;
|
||||
id++;
|
||||
}
|
||||
return def_fmt;
|
||||
}
|
||||
|
||||
void fimc_isp_irq_handler(struct fimc_is *is)
|
||||
{
|
||||
is->i2h_cmd.args[0] = mcuctl_read(is, MCUCTL_REG_ISSR(20));
|
||||
is->i2h_cmd.args[1] = mcuctl_read(is, MCUCTL_REG_ISSR(21));
|
||||
|
||||
fimc_is_fw_clear_irq1(is, FIMC_IS_INT_FRAME_DONE_ISP);
|
||||
|
||||
/* TODO: Complete ISP DMA interrupt handler */
|
||||
wake_up(&is->irq_queue);
|
||||
}
|
||||
|
||||
/* Capture subdev media entity operations */
|
||||
static int fimc_is_link_setup(struct media_entity *entity,
|
||||
const struct media_pad *local,
|
||||
const struct media_pad *remote, u32 flags)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct media_entity_operations fimc_is_subdev_media_ops = {
|
||||
.link_setup = fimc_is_link_setup,
|
||||
};
|
||||
|
||||
static int fimc_is_subdev_enum_mbus_code(struct v4l2_subdev *sd,
|
||||
struct v4l2_subdev_fh *fh,
|
||||
struct v4l2_subdev_mbus_code_enum *code)
|
||||
{
|
||||
const struct fimc_fmt *fmt;
|
||||
|
||||
fmt = fimc_isp_find_format(NULL, NULL, code->index);
|
||||
if (!fmt)
|
||||
return -EINVAL;
|
||||
code->code = fmt->mbus_code;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int fimc_isp_subdev_get_fmt(struct v4l2_subdev *sd,
|
||||
struct v4l2_subdev_fh *fh,
|
||||
struct v4l2_subdev_format *fmt)
|
||||
{
|
||||
struct fimc_isp *isp = v4l2_get_subdevdata(sd);
|
||||
struct fimc_is *is = fimc_isp_to_is(isp);
|
||||
struct v4l2_mbus_framefmt *mf = &fmt->format;
|
||||
struct v4l2_mbus_framefmt cur_fmt;
|
||||
|
||||
if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
|
||||
mf = v4l2_subdev_get_try_format(fh, fmt->pad);
|
||||
fmt->format = *mf;
|
||||
return 0;
|
||||
}
|
||||
|
||||
mf->colorspace = V4L2_COLORSPACE_JPEG;
|
||||
|
||||
mutex_lock(&isp->subdev_lock);
|
||||
__is_get_frame_size(is, &cur_fmt);
|
||||
|
||||
if (fmt->pad == FIMC_ISP_SD_PAD_SINK) {
|
||||
/* full camera input frame size */
|
||||
mf->width = cur_fmt.width + FIMC_ISP_CAC_MARGIN_WIDTH;
|
||||
mf->height = cur_fmt.height + FIMC_ISP_CAC_MARGIN_HEIGHT;
|
||||
mf->code = V4L2_MBUS_FMT_SGRBG10_1X10;
|
||||
} else {
|
||||
/* crop size */
|
||||
mf->width = cur_fmt.width;
|
||||
mf->height = cur_fmt.height;
|
||||
mf->code = V4L2_MBUS_FMT_YUV10_1X30;
|
||||
}
|
||||
|
||||
mutex_unlock(&isp->subdev_lock);
|
||||
|
||||
v4l2_dbg(1, debug, sd, "%s: pad%d: fmt: 0x%x, %dx%d\n",
|
||||
__func__, fmt->pad, mf->code, mf->width, mf->height);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void __isp_subdev_try_format(struct fimc_isp *isp,
|
||||
struct v4l2_subdev_format *fmt)
|
||||
{
|
||||
struct v4l2_mbus_framefmt *mf = &fmt->format;
|
||||
|
||||
if (fmt->pad == FIMC_ISP_SD_PAD_SINK) {
|
||||
v4l_bound_align_image(&mf->width, FIMC_ISP_SINK_WIDTH_MIN,
|
||||
FIMC_ISP_SINK_WIDTH_MAX, 0,
|
||||
&mf->height, FIMC_ISP_SINK_HEIGHT_MIN,
|
||||
FIMC_ISP_SINK_HEIGHT_MAX, 0, 0);
|
||||
isp->subdev_fmt = *mf;
|
||||
} else {
|
||||
/* Allow changing format only on sink pad */
|
||||
mf->width = isp->subdev_fmt.width - FIMC_ISP_CAC_MARGIN_WIDTH;
|
||||
mf->height = isp->subdev_fmt.height - FIMC_ISP_CAC_MARGIN_HEIGHT;
|
||||
mf->code = isp->subdev_fmt.code;
|
||||
}
|
||||
}
|
||||
|
||||
static int fimc_isp_subdev_set_fmt(struct v4l2_subdev *sd,
|
||||
struct v4l2_subdev_fh *fh,
|
||||
struct v4l2_subdev_format *fmt)
|
||||
{
|
||||
struct fimc_isp *isp = v4l2_get_subdevdata(sd);
|
||||
struct fimc_is *is = fimc_isp_to_is(isp);
|
||||
struct v4l2_mbus_framefmt *mf = &fmt->format;
|
||||
int ret = 0;
|
||||
|
||||
v4l2_dbg(1, debug, sd, "%s: pad%d: code: 0x%x, %dx%d\n",
|
||||
__func__, fmt->pad, mf->code, mf->width, mf->height);
|
||||
|
||||
mf->colorspace = V4L2_COLORSPACE_JPEG;
|
||||
|
||||
mutex_lock(&isp->subdev_lock);
|
||||
__isp_subdev_try_format(isp, fmt);
|
||||
|
||||
if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
|
||||
mf = v4l2_subdev_get_try_format(fh, fmt->pad);
|
||||
*mf = fmt->format;
|
||||
mutex_unlock(&isp->subdev_lock);
|
||||
return 0;
|
||||
}
|
||||
|
||||
if (sd->entity.stream_count == 0)
|
||||
__is_set_frame_size(is, mf);
|
||||
else
|
||||
ret = -EBUSY;
|
||||
mutex_unlock(&isp->subdev_lock);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int fimc_isp_subdev_s_stream(struct v4l2_subdev *sd, int on)
|
||||
{
|
||||
struct fimc_isp *isp = v4l2_get_subdevdata(sd);
|
||||
struct fimc_is *is = fimc_isp_to_is(isp);
|
||||
int ret;
|
||||
|
||||
v4l2_dbg(1, debug, sd, "%s: on: %d\n", __func__, on);
|
||||
|
||||
if (!test_bit(IS_ST_INIT_DONE, &is->state))
|
||||
return -EBUSY;
|
||||
|
||||
fimc_is_mem_barrier();
|
||||
|
||||
if (on) {
|
||||
if (atomic_read(&is->cfg_param[is->scenario_id].p_region_num))
|
||||
ret = fimc_is_itf_s_param(is, true);
|
||||
|
||||
v4l2_dbg(1, debug, sd, "changing mode to %d\n",
|
||||
is->scenario_id);
|
||||
ret = fimc_is_itf_mode_change(is);
|
||||
if (ret)
|
||||
return -EINVAL;
|
||||
|
||||
clear_bit(IS_ST_STREAM_ON, &is->state);
|
||||
fimc_is_hw_stream_on(is);
|
||||
ret = fimc_is_wait_event(is, IS_ST_STREAM_ON, 1,
|
||||
FIMC_IS_CONFIG_TIMEOUT);
|
||||
if (ret < 0) {
|
||||
v4l2_err(sd, "stream on timeout\n");
|
||||
return ret;
|
||||
}
|
||||
} else {
|
||||
clear_bit(IS_ST_STREAM_OFF, &is->state);
|
||||
fimc_is_hw_stream_off(is);
|
||||
ret = fimc_is_wait_event(is, IS_ST_STREAM_OFF, 1,
|
||||
FIMC_IS_CONFIG_TIMEOUT);
|
||||
if (ret < 0) {
|
||||
v4l2_err(sd, "stream off timeout\n");
|
||||
return ret;
|
||||
}
|
||||
is->setfile.sub_index = 0;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int fimc_isp_subdev_s_power(struct v4l2_subdev *sd, int on)
|
||||
{
|
||||
struct fimc_isp *isp = v4l2_get_subdevdata(sd);
|
||||
struct fimc_is *is = fimc_isp_to_is(isp);
|
||||
int ret = 0;
|
||||
|
||||
pr_debug("on: %d\n", on);
|
||||
|
||||
if (on) {
|
||||
ret = pm_runtime_get_sync(&is->pdev->dev);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
set_bit(IS_ST_PWR_ON, &is->state);
|
||||
|
||||
ret = fimc_is_start_firmware(is);
|
||||
if (ret < 0) {
|
||||
v4l2_err(sd, "firmware booting failed\n");
|
||||
pm_runtime_put(&is->pdev->dev);
|
||||
return ret;
|
||||
}
|
||||
set_bit(IS_ST_PWR_SUBIP_ON, &is->state);
|
||||
|
||||
ret = fimc_is_hw_initialize(is);
|
||||
} else {
|
||||
/* Close sensor */
|
||||
if (!test_bit(IS_ST_PWR_ON, &is->state)) {
|
||||
fimc_is_hw_close_sensor(is, 0);
|
||||
|
||||
ret = fimc_is_wait_event(is, IS_ST_OPEN_SENSOR, 0,
|
||||
FIMC_IS_CONFIG_TIMEOUT);
|
||||
if (ret < 0) {
|
||||
v4l2_err(sd, "sensor close timeout\n");
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
|
||||
/* SUB IP power off */
|
||||
if (test_bit(IS_ST_PWR_SUBIP_ON, &is->state)) {
|
||||
fimc_is_hw_subip_power_off(is);
|
||||
ret = fimc_is_wait_event(is, IS_ST_PWR_SUBIP_ON, 0,
|
||||
FIMC_IS_CONFIG_TIMEOUT);
|
||||
if (ret < 0) {
|
||||
v4l2_err(sd, "sub-IP power off timeout\n");
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
|
||||
fimc_is_cpu_set_power(is, 0);
|
||||
pm_runtime_put_sync(&is->pdev->dev);
|
||||
|
||||
clear_bit(IS_ST_PWR_ON, &is->state);
|
||||
clear_bit(IS_ST_INIT_DONE, &is->state);
|
||||
is->state = 0;
|
||||
is->cfg_param[is->scenario_id].p_region_index1 = 0;
|
||||
is->cfg_param[is->scenario_id].p_region_index2 = 0;
|
||||
set_bit(IS_ST_IDLE, &is->state);
|
||||
wmb();
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int fimc_isp_subdev_open(struct v4l2_subdev *sd,
|
||||
struct v4l2_subdev_fh *fh)
|
||||
{
|
||||
struct v4l2_mbus_framefmt fmt;
|
||||
struct v4l2_mbus_framefmt *format;
|
||||
|
||||
format = v4l2_subdev_get_try_format(fh, FIMC_ISP_SD_PAD_SINK);
|
||||
|
||||
fmt.colorspace = V4L2_COLORSPACE_SRGB;
|
||||
fmt.code = fimc_isp_formats[0].mbus_code;
|
||||
fmt.width = DEFAULT_PREVIEW_STILL_WIDTH + FIMC_ISP_CAC_MARGIN_WIDTH;
|
||||
fmt.height = DEFAULT_PREVIEW_STILL_HEIGHT + FIMC_ISP_CAC_MARGIN_HEIGHT;
|
||||
fmt.field = V4L2_FIELD_NONE;
|
||||
*format = fmt;
|
||||
|
||||
format = v4l2_subdev_get_try_format(fh, FIMC_ISP_SD_PAD_SRC_FIFO);
|
||||
fmt.width = DEFAULT_PREVIEW_STILL_WIDTH;
|
||||
fmt.height = DEFAULT_PREVIEW_STILL_HEIGHT;
|
||||
*format = fmt;
|
||||
|
||||
format = v4l2_subdev_get_try_format(fh, FIMC_ISP_SD_PAD_SRC_DMA);
|
||||
*format = fmt;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct v4l2_subdev_internal_ops fimc_is_subdev_internal_ops = {
|
||||
.open = fimc_isp_subdev_open,
|
||||
};
|
||||
|
||||
static const struct v4l2_subdev_pad_ops fimc_is_subdev_pad_ops = {
|
||||
.enum_mbus_code = fimc_is_subdev_enum_mbus_code,
|
||||
.get_fmt = fimc_isp_subdev_get_fmt,
|
||||
.set_fmt = fimc_isp_subdev_set_fmt,
|
||||
};
|
||||
|
||||
static const struct v4l2_subdev_video_ops fimc_is_subdev_video_ops = {
|
||||
.s_stream = fimc_isp_subdev_s_stream,
|
||||
};
|
||||
|
||||
static const struct v4l2_subdev_core_ops fimc_is_core_ops = {
|
||||
.s_power = fimc_isp_subdev_s_power,
|
||||
};
|
||||
|
||||
static struct v4l2_subdev_ops fimc_is_subdev_ops = {
|
||||
.core = &fimc_is_core_ops,
|
||||
.video = &fimc_is_subdev_video_ops,
|
||||
.pad = &fimc_is_subdev_pad_ops,
|
||||
};
|
||||
|
||||
static int __ctrl_set_white_balance(struct fimc_is *is, int value)
|
||||
{
|
||||
switch (value) {
|
||||
case V4L2_WHITE_BALANCE_AUTO:
|
||||
__is_set_isp_awb(is, ISP_AWB_COMMAND_AUTO, 0);
|
||||
break;
|
||||
case V4L2_WHITE_BALANCE_DAYLIGHT:
|
||||
__is_set_isp_awb(is, ISP_AWB_COMMAND_ILLUMINATION,
|
||||
ISP_AWB_ILLUMINATION_DAYLIGHT);
|
||||
break;
|
||||
case V4L2_WHITE_BALANCE_CLOUDY:
|
||||
__is_set_isp_awb(is, ISP_AWB_COMMAND_ILLUMINATION,
|
||||
ISP_AWB_ILLUMINATION_CLOUDY);
|
||||
break;
|
||||
case V4L2_WHITE_BALANCE_INCANDESCENT:
|
||||
__is_set_isp_awb(is, ISP_AWB_COMMAND_ILLUMINATION,
|
||||
ISP_AWB_ILLUMINATION_TUNGSTEN);
|
||||
break;
|
||||
case V4L2_WHITE_BALANCE_FLUORESCENT:
|
||||
__is_set_isp_awb(is, ISP_AWB_COMMAND_ILLUMINATION,
|
||||
ISP_AWB_ILLUMINATION_FLUORESCENT);
|
||||
break;
|
||||
default:
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int __ctrl_set_aewb_lock(struct fimc_is *is,
|
||||
struct v4l2_ctrl *ctrl)
|
||||
{
|
||||
bool awb_lock = ctrl->val & V4L2_LOCK_WHITE_BALANCE;
|
||||
bool ae_lock = ctrl->val & V4L2_LOCK_EXPOSURE;
|
||||
struct isp_param *isp = &is->is_p_region->parameter.isp;
|
||||
int cmd, ret;
|
||||
|
||||
cmd = ae_lock ? ISP_AA_COMMAND_STOP : ISP_AA_COMMAND_START;
|
||||
isp->aa.cmd = cmd;
|
||||
isp->aa.target = ISP_AA_TARGET_AE;
|
||||
fimc_is_set_param_bit(is, PARAM_ISP_AA);
|
||||
fimc_is_inc_param_num(is);
|
||||
is->af.ae_lock_state = ae_lock;
|
||||
wmb();
|
||||
|
||||
ret = fimc_is_itf_s_param(is, false);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
cmd = awb_lock ? ISP_AA_COMMAND_STOP : ISP_AA_COMMAND_START;
|
||||
isp->aa.cmd = cmd;
|
||||
isp->aa.target = ISP_AA_TARGET_AE;
|
||||
fimc_is_set_param_bit(is, PARAM_ISP_AA);
|
||||
fimc_is_inc_param_num(is);
|
||||
is->af.awb_lock_state = awb_lock;
|
||||
wmb();
|
||||
|
||||
return fimc_is_itf_s_param(is, false);
|
||||
}
|
||||
|
||||
/* Supported manual ISO values */
|
||||
static const s64 iso_qmenu[] = {
|
||||
50, 100, 200, 400, 800,
|
||||
};
|
||||
|
||||
static int __ctrl_set_iso(struct fimc_is *is, int value)
|
||||
{
|
||||
unsigned int idx, iso;
|
||||
|
||||
if (value == V4L2_ISO_SENSITIVITY_AUTO) {
|
||||
__is_set_isp_iso(is, ISP_ISO_COMMAND_AUTO, 0);
|
||||
return 0;
|
||||
}
|
||||
idx = is->isp.ctrls.iso->val;
|
||||
if (idx >= ARRAY_SIZE(iso_qmenu))
|
||||
return -EINVAL;
|
||||
|
||||
iso = iso_qmenu[idx];
|
||||
__is_set_isp_iso(is, ISP_ISO_COMMAND_MANUAL, iso);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int __ctrl_set_metering(struct fimc_is *is, unsigned int value)
|
||||
{
|
||||
unsigned int val;
|
||||
|
||||
switch (value) {
|
||||
case V4L2_EXPOSURE_METERING_AVERAGE:
|
||||
val = ISP_METERING_COMMAND_AVERAGE;
|
||||
break;
|
||||
case V4L2_EXPOSURE_METERING_CENTER_WEIGHTED:
|
||||
val = ISP_METERING_COMMAND_CENTER;
|
||||
break;
|
||||
case V4L2_EXPOSURE_METERING_SPOT:
|
||||
val = ISP_METERING_COMMAND_SPOT;
|
||||
break;
|
||||
case V4L2_EXPOSURE_METERING_MATRIX:
|
||||
val = ISP_METERING_COMMAND_MATRIX;
|
||||
break;
|
||||
default:
|
||||
return -EINVAL;
|
||||
};
|
||||
|
||||
__is_set_isp_metering(is, IS_METERING_CONFIG_CMD, val);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int __ctrl_set_afc(struct fimc_is *is, int value)
|
||||
{
|
||||
switch (value) {
|
||||
case V4L2_CID_POWER_LINE_FREQUENCY_DISABLED:
|
||||
__is_set_isp_afc(is, ISP_AFC_COMMAND_DISABLE, 0);
|
||||
break;
|
||||
case V4L2_CID_POWER_LINE_FREQUENCY_50HZ:
|
||||
__is_set_isp_afc(is, ISP_AFC_COMMAND_MANUAL, 50);
|
||||
break;
|
||||
case V4L2_CID_POWER_LINE_FREQUENCY_60HZ:
|
||||
__is_set_isp_afc(is, ISP_AFC_COMMAND_MANUAL, 60);
|
||||
break;
|
||||
case V4L2_CID_POWER_LINE_FREQUENCY_AUTO:
|
||||
__is_set_isp_afc(is, ISP_AFC_COMMAND_AUTO, 0);
|
||||
break;
|
||||
default:
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int __ctrl_set_image_effect(struct fimc_is *is, int value)
|
||||
{
|
||||
static const u8 effects[][2] = {
|
||||
{ V4L2_COLORFX_NONE, ISP_IMAGE_EFFECT_DISABLE },
|
||||
{ V4L2_COLORFX_BW, ISP_IMAGE_EFFECT_MONOCHROME },
|
||||
{ V4L2_COLORFX_SEPIA, ISP_IMAGE_EFFECT_SEPIA },
|
||||
{ V4L2_COLORFX_NEGATIVE, ISP_IMAGE_EFFECT_NEGATIVE_MONO },
|
||||
{ 16 /* TODO */, ISP_IMAGE_EFFECT_NEGATIVE_COLOR },
|
||||
};
|
||||
int i;
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(effects); i++) {
|
||||
if (effects[i][0] != value)
|
||||
continue;
|
||||
|
||||
__is_set_isp_effect(is, effects[i][1]);
|
||||
return 0;
|
||||
}
|
||||
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
static int fimc_is_s_ctrl(struct v4l2_ctrl *ctrl)
|
||||
{
|
||||
struct fimc_isp *isp = ctrl_to_fimc_isp(ctrl);
|
||||
struct fimc_is *is = fimc_isp_to_is(isp);
|
||||
bool set_param = true;
|
||||
int ret = 0;
|
||||
|
||||
switch (ctrl->id) {
|
||||
case V4L2_CID_CONTRAST:
|
||||
__is_set_isp_adjust(is, ISP_ADJUST_COMMAND_MANUAL_CONTRAST,
|
||||
ctrl->val);
|
||||
break;
|
||||
|
||||
case V4L2_CID_SATURATION:
|
||||
__is_set_isp_adjust(is, ISP_ADJUST_COMMAND_MANUAL_SATURATION,
|
||||
ctrl->val);
|
||||
break;
|
||||
|
||||
case V4L2_CID_SHARPNESS:
|
||||
__is_set_isp_adjust(is, ISP_ADJUST_COMMAND_MANUAL_SHARPNESS,
|
||||
ctrl->val);
|
||||
break;
|
||||
|
||||
case V4L2_CID_EXPOSURE_ABSOLUTE:
|
||||
__is_set_isp_adjust(is, ISP_ADJUST_COMMAND_MANUAL_EXPOSURE,
|
||||
ctrl->val);
|
||||
break;
|
||||
|
||||
case V4L2_CID_BRIGHTNESS:
|
||||
__is_set_isp_adjust(is, ISP_ADJUST_COMMAND_MANUAL_BRIGHTNESS,
|
||||
ctrl->val);
|
||||
break;
|
||||
|
||||
case V4L2_CID_HUE:
|
||||
__is_set_isp_adjust(is, ISP_ADJUST_COMMAND_MANUAL_HUE,
|
||||
ctrl->val);
|
||||
break;
|
||||
|
||||
case V4L2_CID_EXPOSURE_METERING:
|
||||
ret = __ctrl_set_metering(is, ctrl->val);
|
||||
break;
|
||||
|
||||
case V4L2_CID_AUTO_N_PRESET_WHITE_BALANCE:
|
||||
ret = __ctrl_set_white_balance(is, ctrl->val);
|
||||
break;
|
||||
|
||||
case V4L2_CID_3A_LOCK:
|
||||
ret = __ctrl_set_aewb_lock(is, ctrl);
|
||||
set_param = false;
|
||||
break;
|
||||
|
||||
case V4L2_CID_ISO_SENSITIVITY_AUTO:
|
||||
ret = __ctrl_set_iso(is, ctrl->val);
|
||||
break;
|
||||
|
||||
case V4L2_CID_POWER_LINE_FREQUENCY:
|
||||
ret = __ctrl_set_afc(is, ctrl->val);
|
||||
break;
|
||||
|
||||
case V4L2_CID_COLORFX:
|
||||
__ctrl_set_image_effect(is, ctrl->val);
|
||||
break;
|
||||
|
||||
default:
|
||||
ret = -EINVAL;
|
||||
break;
|
||||
}
|
||||
|
||||
if (ret < 0) {
|
||||
v4l2_err(&isp->subdev, "Failed to set control: %s (%d)\n",
|
||||
ctrl->name, ctrl->val);
|
||||
return ret;
|
||||
}
|
||||
|
||||
if (set_param && test_bit(IS_ST_STREAM_ON, &is->state))
|
||||
return fimc_is_itf_s_param(is, true);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct v4l2_ctrl_ops fimc_isp_ctrl_ops = {
|
||||
.s_ctrl = fimc_is_s_ctrl,
|
||||
};
|
||||
|
||||
int fimc_isp_subdev_create(struct fimc_isp *isp)
|
||||
{
|
||||
const struct v4l2_ctrl_ops *ops = &fimc_isp_ctrl_ops;
|
||||
struct v4l2_ctrl_handler *handler = &isp->ctrls.handler;
|
||||
struct v4l2_subdev *sd = &isp->subdev;
|
||||
struct fimc_isp_ctrls *ctrls = &isp->ctrls;
|
||||
int ret;
|
||||
|
||||
mutex_init(&isp->subdev_lock);
|
||||
|
||||
v4l2_subdev_init(sd, &fimc_is_subdev_ops);
|
||||
sd->grp_id = GRP_ID_FIMC_IS;
|
||||
sd->flags = V4L2_SUBDEV_FL_HAS_DEVNODE;
|
||||
snprintf(sd->name, sizeof(sd->name), "FIMC-IS-ISP");
|
||||
|
||||
isp->subdev_pads[FIMC_ISP_SD_PAD_SINK].flags = MEDIA_PAD_FL_SINK;
|
||||
isp->subdev_pads[FIMC_ISP_SD_PAD_SRC_FIFO].flags = MEDIA_PAD_FL_SOURCE;
|
||||
isp->subdev_pads[FIMC_ISP_SD_PAD_SRC_DMA].flags = MEDIA_PAD_FL_SOURCE;
|
||||
ret = media_entity_init(&sd->entity, FIMC_ISP_SD_PADS_NUM,
|
||||
isp->subdev_pads, 0);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
v4l2_ctrl_handler_init(handler, 20);
|
||||
|
||||
ctrls->saturation = v4l2_ctrl_new_std(handler, ops, V4L2_CID_SATURATION,
|
||||
-2, 2, 1, 0);
|
||||
ctrls->brightness = v4l2_ctrl_new_std(handler, ops, V4L2_CID_BRIGHTNESS,
|
||||
-4, 4, 1, 0);
|
||||
ctrls->contrast = v4l2_ctrl_new_std(handler, ops, V4L2_CID_CONTRAST,
|
||||
-2, 2, 1, 0);
|
||||
ctrls->sharpness = v4l2_ctrl_new_std(handler, ops, V4L2_CID_SHARPNESS,
|
||||
-2, 2, 1, 0);
|
||||
ctrls->hue = v4l2_ctrl_new_std(handler, ops, V4L2_CID_HUE,
|
||||
-2, 2, 1, 0);
|
||||
|
||||
ctrls->auto_wb = v4l2_ctrl_new_std_menu(handler, ops,
|
||||
V4L2_CID_AUTO_N_PRESET_WHITE_BALANCE,
|
||||
8, ~0x14e, V4L2_WHITE_BALANCE_AUTO);
|
||||
|
||||
ctrls->exposure = v4l2_ctrl_new_std(handler, ops,
|
||||
V4L2_CID_EXPOSURE_ABSOLUTE,
|
||||
-4, 4, 1, 0);
|
||||
|
||||
ctrls->exp_metering = v4l2_ctrl_new_std_menu(handler, ops,
|
||||
V4L2_CID_EXPOSURE_METERING, 3,
|
||||
~0xf, V4L2_EXPOSURE_METERING_AVERAGE);
|
||||
|
||||
v4l2_ctrl_new_std_menu(handler, ops, V4L2_CID_POWER_LINE_FREQUENCY,
|
||||
V4L2_CID_POWER_LINE_FREQUENCY_AUTO, 0,
|
||||
V4L2_CID_POWER_LINE_FREQUENCY_AUTO);
|
||||
/* ISO sensitivity */
|
||||
ctrls->auto_iso = v4l2_ctrl_new_std_menu(handler, ops,
|
||||
V4L2_CID_ISO_SENSITIVITY_AUTO, 1, 0,
|
||||
V4L2_ISO_SENSITIVITY_AUTO);
|
||||
|
||||
ctrls->iso = v4l2_ctrl_new_int_menu(handler, ops,
|
||||
V4L2_CID_ISO_SENSITIVITY, ARRAY_SIZE(iso_qmenu) - 1,
|
||||
ARRAY_SIZE(iso_qmenu)/2 - 1, iso_qmenu);
|
||||
|
||||
ctrls->aewb_lock = v4l2_ctrl_new_std(handler, ops,
|
||||
V4L2_CID_3A_LOCK, 0, 0x3, 0, 0);
|
||||
|
||||
/* TODO: Add support for NEGATIVE_COLOR option */
|
||||
ctrls->colorfx = v4l2_ctrl_new_std_menu(handler, ops, V4L2_CID_COLORFX,
|
||||
V4L2_COLORFX_SET_CBCR + 1, ~0x1000f, V4L2_COLORFX_NONE);
|
||||
|
||||
if (handler->error) {
|
||||
media_entity_cleanup(&sd->entity);
|
||||
return handler->error;
|
||||
}
|
||||
|
||||
v4l2_ctrl_auto_cluster(2, &ctrls->auto_iso,
|
||||
V4L2_ISO_SENSITIVITY_MANUAL, false);
|
||||
|
||||
sd->ctrl_handler = handler;
|
||||
sd->internal_ops = &fimc_is_subdev_internal_ops;
|
||||
sd->entity.ops = &fimc_is_subdev_media_ops;
|
||||
v4l2_set_subdevdata(sd, isp);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void fimc_isp_subdev_destroy(struct fimc_isp *isp)
|
||||
{
|
||||
struct v4l2_subdev *sd = &isp->subdev;
|
||||
|
||||
v4l2_device_unregister_subdev(sd);
|
||||
media_entity_cleanup(&sd->entity);
|
||||
v4l2_ctrl_handler_free(&isp->ctrls.handler);
|
||||
v4l2_set_subdevdata(sd, NULL);
|
||||
}
|
||||
|
|
@ -0,0 +1,181 @@
|
|||
/*
|
||||
* Samsung EXYNOS4x12 FIMC-IS (Imaging Subsystem) driver
|
||||
*
|
||||
* Copyright (C) 2013 Samsung Electronics Co., Ltd.
|
||||
*
|
||||
* Authors: Sylwester Nawrocki <s.nawrocki@samsung.com>
|
||||
* Younghwan Joo <yhwan.joo@samsung.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
#ifndef FIMC_ISP_H_
|
||||
#define FIMC_ISP_H_
|
||||
|
||||
#include <linux/io.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/sched.h>
|
||||
#include <linux/spinlock.h>
|
||||
#include <linux/types.h>
|
||||
#include <linux/videodev2.h>
|
||||
|
||||
#include <media/media-entity.h>
|
||||
#include <media/videobuf2-core.h>
|
||||
#include <media/v4l2-device.h>
|
||||
#include <media/v4l2-mediabus.h>
|
||||
#include <media/s5p_fimc.h>
|
||||
|
||||
/* FIXME: revisit these constraints */
|
||||
#define FIMC_ISP_SINK_WIDTH_MIN (16 + 8)
|
||||
#define FIMC_ISP_SINK_HEIGHT_MIN (12 + 8)
|
||||
#define FIMC_ISP_SOURCE_WIDTH_MIN 8
|
||||
#define FIMC_ISP_SOURC_HEIGHT_MIN 8
|
||||
#define FIMC_ISP_CAC_MARGIN_WIDTH 16
|
||||
#define FIMC_ISP_CAC_MARGIN_HEIGHT 12
|
||||
|
||||
#define FIMC_ISP_SINK_WIDTH_MAX (4000 - 16)
|
||||
#define FIMC_ISP_SINK_HEIGHT_MAX (4000 + 12)
|
||||
#define FIMC_ISP_SOURCE_WIDTH_MAX 4000
|
||||
#define FIMC_ISP_SOURC_HEIGHT_MAX 4000
|
||||
|
||||
#define FIMC_ISP_NUM_FORMATS 3
|
||||
#define FIMC_ISP_REQ_BUFS_MIN 2
|
||||
|
||||
#define FIMC_ISP_SD_PAD_SINK 0
|
||||
#define FIMC_ISP_SD_PAD_SRC_FIFO 1
|
||||
#define FIMC_ISP_SD_PAD_SRC_DMA 2
|
||||
#define FIMC_ISP_SD_PADS_NUM 3
|
||||
#define FIMC_ISP_MAX_PLANES 1
|
||||
|
||||
/**
|
||||
* struct fimc_isp_frame - source/target frame properties
|
||||
* @width: full image width
|
||||
* @height: full image height
|
||||
* @rect: crop/composition rectangle
|
||||
*/
|
||||
struct fimc_isp_frame {
|
||||
u16 width;
|
||||
u16 height;
|
||||
struct v4l2_rect rect;
|
||||
};
|
||||
|
||||
struct fimc_isp_ctrls {
|
||||
struct v4l2_ctrl_handler handler;
|
||||
|
||||
/* Auto white balance */
|
||||
struct v4l2_ctrl *auto_wb;
|
||||
/* Auto ISO control cluster */
|
||||
struct {
|
||||
struct v4l2_ctrl *auto_iso;
|
||||
struct v4l2_ctrl *iso;
|
||||
};
|
||||
/* Adjust - contrast */
|
||||
struct v4l2_ctrl *contrast;
|
||||
/* Adjust - saturation */
|
||||
struct v4l2_ctrl *saturation;
|
||||
/* Adjust - sharpness */
|
||||
struct v4l2_ctrl *sharpness;
|
||||
/* Adjust - brightness */
|
||||
struct v4l2_ctrl *brightness;
|
||||
/* Adjust - hue */
|
||||
struct v4l2_ctrl *hue;
|
||||
|
||||
/* Auto/manual exposure */
|
||||
struct v4l2_ctrl *auto_exp;
|
||||
/* Manual exposure value */
|
||||
struct v4l2_ctrl *exposure;
|
||||
/* AE/AWB lock/unlock */
|
||||
struct v4l2_ctrl *aewb_lock;
|
||||
/* Exposure metering mode */
|
||||
struct v4l2_ctrl *exp_metering;
|
||||
/* AFC */
|
||||
struct v4l2_ctrl *afc;
|
||||
/* ISP image effect */
|
||||
struct v4l2_ctrl *colorfx;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct fimc_is_video - fimc-is video device structure
|
||||
* @vdev: video_device structure
|
||||
* @type: video device type (CAPTURE/OUTPUT)
|
||||
* @pad: video device media (sink) pad
|
||||
* @pending_buf_q: pending buffers queue head
|
||||
* @active_buf_q: a queue head of buffers scheduled in hardware
|
||||
* @vb_queue: vb2 buffer queue
|
||||
* @active_buf_count: number of video buffers scheduled in hardware
|
||||
* @frame_count: counter of frames dequeued to user space
|
||||
* @reqbufs_count: number of buffers requested with REQBUFS ioctl
|
||||
* @format: current pixel format
|
||||
*/
|
||||
struct fimc_is_video {
|
||||
struct video_device vdev;
|
||||
enum v4l2_buf_type type;
|
||||
struct media_pad pad;
|
||||
struct list_head pending_buf_q;
|
||||
struct list_head active_buf_q;
|
||||
struct vb2_queue vb_queue;
|
||||
unsigned int frame_count;
|
||||
unsigned int reqbufs_count;
|
||||
int streaming;
|
||||
unsigned long payload[FIMC_ISP_MAX_PLANES];
|
||||
const struct fimc_fmt *format;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct fimc_isp - FIMC-IS ISP data structure
|
||||
* @pdev: pointer to FIMC-IS platform device
|
||||
* @alloc_ctx: videobuf2 memory allocator context
|
||||
* @subdev: ISP v4l2_subdev
|
||||
* @subdev_pads: the ISP subdev media pads
|
||||
* @ctrl_handler: v4l2 controls handler
|
||||
* @test_pattern: test pattern controls
|
||||
* @pipeline: video capture pipeline data structure
|
||||
* @video_lock: mutex serializing video device and the subdev operations
|
||||
* @fmt: pointer to color format description structure
|
||||
* @payload: image size in bytes (w x h x bpp)
|
||||
* @inp_frame: camera input frame structure
|
||||
* @out_frame: DMA output frame structure
|
||||
* @source_subdev_grp_id: group id of remote source subdev
|
||||
* @cac_margin_x: horizontal CAC margin in pixels
|
||||
* @cac_margin_y: vertical CAC margin in pixels
|
||||
* @state: driver state flags
|
||||
* @video_capture: the ISP block video capture device
|
||||
*/
|
||||
struct fimc_isp {
|
||||
struct platform_device *pdev;
|
||||
struct vb2_alloc_ctx *alloc_ctx;
|
||||
struct v4l2_subdev subdev;
|
||||
struct media_pad subdev_pads[FIMC_ISP_SD_PADS_NUM];
|
||||
struct v4l2_mbus_framefmt subdev_fmt;
|
||||
struct v4l2_ctrl *test_pattern;
|
||||
struct fimc_isp_ctrls ctrls;
|
||||
|
||||
struct mutex video_lock;
|
||||
struct mutex subdev_lock;
|
||||
|
||||
struct fimc_isp_frame inp_frame;
|
||||
struct fimc_isp_frame out_frame;
|
||||
unsigned int source_subdev_grp_id;
|
||||
|
||||
unsigned int cac_margin_x;
|
||||
unsigned int cac_margin_y;
|
||||
|
||||
unsigned long state;
|
||||
|
||||
struct fimc_is_video video_capture;
|
||||
};
|
||||
|
||||
#define ctrl_to_fimc_isp(_ctrl) \
|
||||
container_of(ctrl->handler, struct fimc_isp, ctrls.handler)
|
||||
|
||||
struct fimc_is;
|
||||
|
||||
int fimc_isp_subdev_create(struct fimc_isp *isp);
|
||||
void fimc_isp_subdev_destroy(struct fimc_isp *isp);
|
||||
void fimc_isp_irq_handler(struct fimc_is *is);
|
||||
int fimc_is_create_controls(struct fimc_isp *isp);
|
||||
int fimc_is_delete_controls(struct fimc_isp *isp);
|
||||
const struct fimc_fmt *fimc_isp_find_format(const u32 *pixelformat,
|
||||
const u32 *mbus_code, int index);
|
||||
#endif /* FIMC_ISP_H_ */
|
||||
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