dma: coh901318: skip hard-coded addresses
Remove hard-coded target addresses altogether. Skip the prefix "runtime_*" from the variables, since all of these are now runtime and their names are unique enough already. Acked-by: Vinod Koul <vinod.koul@intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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9aab4d6f08
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@ -56,7 +56,6 @@ struct coh901318_params {
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* @desc_nbr_max: number of preallocated descriptors
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* @priority_high: prio of channel, 0 low otherwise high.
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* @param: configuration parameters
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* @dev_addr: physical address of periphal connected to channel
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*/
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struct coh_dma_channel {
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const char name[32];
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@ -64,7 +63,6 @@ struct coh_dma_channel {
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const int desc_nbr_max;
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const int priority_high;
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const struct coh901318_params param;
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const dma_addr_t dev_addr;
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};
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/**
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@ -1141,8 +1141,8 @@ struct coh901318_chan {
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unsigned long nbr_active_done;
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unsigned long busy;
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u32 runtime_addr;
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u32 runtime_ctrl;
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u32 addr;
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u32 ctrl;
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struct coh901318_base *base;
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};
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@ -1253,15 +1253,6 @@ static inline struct coh901318_chan *to_coh901318_chan(struct dma_chan *chan)
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return container_of(chan, struct coh901318_chan, chan);
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}
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static inline dma_addr_t
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cohc_dev_addr(struct coh901318_chan *cohc)
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{
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/* Runtime supplied address will take precedence */
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if (cohc->runtime_addr)
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return cohc->runtime_addr;
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return cohc->base->platform->chan_conf[cohc->id].dev_addr;
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}
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static inline const struct coh901318_params *
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cohc_chan_param(struct coh901318_chan *cohc)
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{
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@ -2118,9 +2109,9 @@ coh901318_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
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* sure the bits you set per peripheral channel are
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* cleared in the default config from the platform.
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*/
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ctrl_chained |= cohc->runtime_ctrl;
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ctrl_last |= cohc->runtime_ctrl;
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ctrl |= cohc->runtime_ctrl;
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ctrl_chained |= cohc->ctrl;
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ctrl_last |= cohc->ctrl;
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ctrl |= cohc->ctrl;
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if (direction == DMA_MEM_TO_DEV) {
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u32 tx_flags = COH901318_CX_CTRL_PRDD_SOURCE |
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@ -2169,7 +2160,7 @@ coh901318_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
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/* initiate allocated lli list */
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ret = coh901318_lli_fill_sg(&cohc->base->pool, lli, sgl, sg_len,
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cohc_dev_addr(cohc),
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cohc->addr,
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ctrl_chained,
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ctrl,
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ctrl_last,
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@ -2310,7 +2301,7 @@ static void coh901318_dma_set_runtimeconfig(struct dma_chan *chan,
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dma_addr_t addr;
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enum dma_slave_buswidth addr_width;
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u32 maxburst;
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u32 runtime_ctrl = 0;
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u32 ctrl = 0;
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int i = 0;
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/* We only support mem to per or per to mem transfers */
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@ -2331,7 +2322,7 @@ static void coh901318_dma_set_runtimeconfig(struct dma_chan *chan,
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addr_width);
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switch (addr_width) {
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case DMA_SLAVE_BUSWIDTH_1_BYTE:
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runtime_ctrl |=
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ctrl |=
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COH901318_CX_CTRL_SRC_BUS_SIZE_8_BITS |
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COH901318_CX_CTRL_DST_BUS_SIZE_8_BITS;
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@ -2343,7 +2334,7 @@ static void coh901318_dma_set_runtimeconfig(struct dma_chan *chan,
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break;
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case DMA_SLAVE_BUSWIDTH_2_BYTES:
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runtime_ctrl |=
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ctrl |=
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COH901318_CX_CTRL_SRC_BUS_SIZE_16_BITS |
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COH901318_CX_CTRL_DST_BUS_SIZE_16_BITS;
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@ -2356,7 +2347,7 @@ static void coh901318_dma_set_runtimeconfig(struct dma_chan *chan,
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break;
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case DMA_SLAVE_BUSWIDTH_4_BYTES:
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/* Direction doesn't matter here, it's 32/32 bits */
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runtime_ctrl |=
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ctrl |=
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COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
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COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS;
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@ -2373,13 +2364,13 @@ static void coh901318_dma_set_runtimeconfig(struct dma_chan *chan,
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return;
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}
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runtime_ctrl |= burst_sizes[i].reg;
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ctrl |= burst_sizes[i].reg;
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dev_dbg(COHC_2_DEV(cohc),
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"selected burst size %d bytes for address width %d bytes, maxburst %d\n",
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burst_sizes[i].burst_8bit, addr_width, maxburst);
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cohc->runtime_addr = addr;
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cohc->runtime_ctrl = runtime_ctrl;
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cohc->addr = addr;
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cohc->ctrl = ctrl;
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}
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static int
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