powerpc: minor cleanups for mpc86xx
* Remove duplicated cputable entry for 8641 (matches w/7448) * Removed __init from function prototypes in mpc86xx.h * Moved pci fixups into board specific code * Moved mpc86xx_exclude_device to generic mpc86xx pci code * Fixed sparse warnings in mpc86xx_smp.c * Removed board specific header include from asm-powerpc/mpc86xx.h Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This commit is contained in:
Kumar Gala
Родитель
fcc18e83e1
Коммит
9ad494f624
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@ -722,18 +722,6 @@ struct cpu_spec cpu_specs[] = {
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.oprofile_type = PPC_OPROFILE_G4,
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.platform = "ppc7450",
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},
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{ /* 8641 */
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.pvr_mask = 0xffffffff,
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.pvr_value = 0x80040010,
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.cpu_name = "8641",
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.cpu_features = CPU_FTRS_7447A,
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.cpu_user_features = COMMON_USER | PPC_FEATURE_HAS_ALTIVEC_COMP,
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.icache_bsize = 32,
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.dcache_bsize = 32,
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.num_pmcs = 6,
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.cpu_setup = __setup_cpu_745x
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},
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{ /* 82xx (8240, 8245, 8260 are all 603e cores) */
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.pvr_mask = 0x7fff0000,
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.pvr_value = 0x00810000,
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@ -15,11 +15,13 @@
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* mpc86xx_* files. Mostly for use by mpc86xx_setup().
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*/
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extern int __init add_bridge(struct device_node *dev);
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extern int add_bridge(struct device_node *dev);
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extern void __init setup_indirect_pcie(struct pci_controller *hose,
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extern int mpc86xx_exclude_device(u_char bus, u_char devfn);
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extern void setup_indirect_pcie(struct pci_controller *hose,
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u32 cfg_addr, u32 cfg_data);
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extern void __init setup_indirect_pcie_nomap(struct pci_controller *hose,
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extern void setup_indirect_pcie_nomap(struct pci_controller *hose,
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void __iomem *cfg_addr,
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void __iomem *cfg_data);
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@ -36,6 +36,7 @@
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#include <sysdev/fsl_soc.h>
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#include "mpc86xx.h"
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#include "mpc8641_hpcn.h"
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#ifndef CONFIG_PCI
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unsigned long isa_io_base = 0;
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@ -186,17 +187,130 @@ mpc86xx_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
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return PCI_IRQ_TABLE_LOOKUP + I8259_OFFSET;
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}
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int
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mpc86xx_exclude_device(u_char bus, u_char devfn)
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static void __devinit quirk_ali1575(struct pci_dev *dev)
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{
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#if !defined(CONFIG_PCI)
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if (bus == 0 && PCI_SLOT(devfn) == 0)
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return PCIBIOS_DEVICE_NOT_FOUND;
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#endif
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unsigned short temp;
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return PCIBIOS_SUCCESSFUL;
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/*
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* ALI1575 interrupts route table setup:
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*
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* IRQ pin IRQ#
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* PIRQA ---- 3
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* PIRQB ---- 4
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* PIRQC ---- 5
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* PIRQD ---- 6
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* PIRQE ---- 9
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* PIRQF ---- 10
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* PIRQG ---- 11
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* PIRQH ---- 12
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*
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* interrupts for PCI slot0 -- PIRQA / PIRQB / PIRQC / PIRQD
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* PCI slot1 -- PIRQB / PIRQC / PIRQD / PIRQA
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*/
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pci_write_config_dword(dev, 0x48, 0xb9317542);
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/* USB 1.1 OHCI controller 1, interrupt: PIRQE */
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pci_write_config_byte(dev, 0x86, 0x0c);
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/* USB 1.1 OHCI controller 2, interrupt: PIRQF */
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pci_write_config_byte(dev, 0x87, 0x0d);
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/* USB 1.1 OHCI controller 3, interrupt: PIRQH */
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pci_write_config_byte(dev, 0x88, 0x0f);
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/* USB 2.0 controller, interrupt: PIRQ7 */
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pci_write_config_byte(dev, 0x74, 0x06);
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/* Audio controller, interrupt: PIRQE */
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pci_write_config_byte(dev, 0x8a, 0x0c);
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/* Modem controller, interrupt: PIRQF */
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pci_write_config_byte(dev, 0x8b, 0x0d);
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/* HD audio controller, interrupt: PIRQG */
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pci_write_config_byte(dev, 0x8c, 0x0e);
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/* Serial ATA interrupt: PIRQD */
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pci_write_config_byte(dev, 0x8d, 0x0b);
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/* SMB interrupt: PIRQH */
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pci_write_config_byte(dev, 0x8e, 0x0f);
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/* PMU ACPI SCI interrupt: PIRQH */
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pci_write_config_byte(dev, 0x8f, 0x0f);
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/* Primary PATA IDE IRQ: 14
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* Secondary PATA IDE IRQ: 15
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*/
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pci_write_config_byte(dev, 0x44, 0x3d);
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pci_write_config_byte(dev, 0x75, 0x0f);
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/* Set IRQ14 and IRQ15 to legacy IRQs */
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pci_read_config_word(dev, 0x46, &temp);
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temp |= 0xc000;
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pci_write_config_word(dev, 0x46, temp);
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/* Set i8259 interrupt trigger
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* IRQ 3: Level
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* IRQ 4: Level
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* IRQ 5: Level
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* IRQ 6: Level
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* IRQ 7: Level
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* IRQ 9: Level
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* IRQ 10: Level
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* IRQ 11: Level
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* IRQ 12: Level
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* IRQ 14: Edge
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* IRQ 15: Edge
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*/
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outb(0xfa, 0x4d0);
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outb(0x1e, 0x4d1);
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}
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static void __devinit quirk_uli5288(struct pci_dev *dev)
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{
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unsigned char c;
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pci_read_config_byte(dev,0x83,&c);
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c |= 0x80;
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pci_write_config_byte(dev, 0x83, c);
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pci_write_config_byte(dev, 0x09, 0x01);
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pci_write_config_byte(dev, 0x0a, 0x06);
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pci_read_config_byte(dev,0x83,&c);
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c &= 0x7f;
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pci_write_config_byte(dev, 0x83, c);
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pci_read_config_byte(dev,0x84,&c);
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c |= 0x01;
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pci_write_config_byte(dev, 0x84, c);
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}
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static void __devinit quirk_uli5229(struct pci_dev *dev)
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{
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unsigned short temp;
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pci_write_config_word(dev, 0x04, 0x0405);
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pci_read_config_word(dev, 0x4a, &temp);
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temp |= 0x1000;
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pci_write_config_word(dev, 0x4a, temp);
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}
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static void __devinit early_uli5249(struct pci_dev *dev)
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{
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unsigned char temp;
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pci_write_config_word(dev, 0x04, 0x0007);
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pci_read_config_byte(dev, 0x7c, &temp);
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pci_write_config_byte(dev, 0x7c, 0x80);
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pci_write_config_byte(dev, 0x09, 0x01);
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pci_write_config_byte(dev, 0x7c, temp);
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dev->class |= 0x1;
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}
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, 0x1575, quirk_ali1575);
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, 0x5288, quirk_uli5288);
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, 0x5229, quirk_uli5229);
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DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AL, 0x5249, early_uli5249);
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#endif /* CONFIG_PCI */
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@ -34,8 +34,8 @@ extern unsigned long __secondary_hold_acknowledge;
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static void __init
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smp_86xx_release_core(int nr)
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{
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void *mcm_vaddr;
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unsigned long vaddr, pcr;
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__be32 __iomem *mcm_vaddr;
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unsigned long pcr;
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if (nr < 0 || nr >= NR_CPUS)
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return;
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@ -45,10 +45,9 @@ smp_86xx_release_core(int nr)
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*/
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mcm_vaddr = ioremap(get_immrbase() + MPC86xx_MCM_OFFSET,
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MPC86xx_MCM_SIZE);
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vaddr = (unsigned long)mcm_vaddr + MCM_PORT_CONFIG_OFFSET;
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pcr = in_be32((volatile unsigned *)vaddr);
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pcr = in_be32(mcm_vaddr + (MCM_PORT_CONFIG_OFFSET >> 2));
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pcr |= 1 << (nr + 24);
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out_be32((volatile unsigned *)vaddr, pcr);
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out_be32(mcm_vaddr + (MCM_PORT_CONFIG_OFFSET >> 2), pcr);
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}
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@ -122,15 +122,12 @@ static void __init setup_pcie_atmu(struct pci_controller *hose, struct resource
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static void __init
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mpc86xx_setup_pcie(struct pci_controller *hose, u32 pcie_offset, u32 pcie_size)
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{
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volatile struct ccsr_pex *pcie;
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u16 cmd;
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unsigned int temps;
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DBG("PCIE host controller register offset 0x%08x, size 0x%08x.\n",
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pcie_offset, pcie_size);
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pcie = ioremap(pcie_offset, pcie_size);
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early_read_config_word(hose, 0, 0, PCI_COMMAND, &cmd);
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cmd |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY
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| PCI_COMMAND_IO;
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@ -144,6 +141,14 @@ mpc86xx_setup_pcie(struct pci_controller *hose, u32 pcie_offset, u32 pcie_size)
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early_write_config_dword(hose, 0, 0, PCI_PRIMARY_BUS, temps);
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}
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int mpc86xx_exclude_device(u_char bus, u_char devfn)
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{
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if (bus == 0 && PCI_SLOT(devfn) == 0)
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return PCIBIOS_DEVICE_NOT_FOUND;
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return PCIBIOS_SUCCESSFUL;
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}
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int __init add_bridge(struct device_node *dev)
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{
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int len;
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@ -198,128 +203,3 @@ int __init add_bridge(struct device_node *dev)
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return 0;
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}
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static void __devinit quirk_ali1575(struct pci_dev *dev)
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{
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unsigned short temp;
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/*
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* ALI1575 interrupts route table setup:
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*
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* IRQ pin IRQ#
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* PIRQA ---- 3
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* PIRQB ---- 4
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* PIRQC ---- 5
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* PIRQD ---- 6
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* PIRQE ---- 9
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* PIRQF ---- 10
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* PIRQG ---- 11
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* PIRQH ---- 12
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*
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* interrupts for PCI slot0 -- PIRQA / PIRQB / PIRQC / PIRQD
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* PCI slot1 -- PIRQB / PIRQC / PIRQD / PIRQA
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*/
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pci_write_config_dword(dev, 0x48, 0xb9317542);
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/* USB 1.1 OHCI controller 1, interrupt: PIRQE */
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pci_write_config_byte(dev, 0x86, 0x0c);
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/* USB 1.1 OHCI controller 2, interrupt: PIRQF */
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pci_write_config_byte(dev, 0x87, 0x0d);
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/* USB 1.1 OHCI controller 3, interrupt: PIRQH */
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pci_write_config_byte(dev, 0x88, 0x0f);
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/* USB 2.0 controller, interrupt: PIRQ7 */
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pci_write_config_byte(dev, 0x74, 0x06);
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/* Audio controller, interrupt: PIRQE */
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pci_write_config_byte(dev, 0x8a, 0x0c);
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/* Modem controller, interrupt: PIRQF */
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pci_write_config_byte(dev, 0x8b, 0x0d);
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/* HD audio controller, interrupt: PIRQG */
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pci_write_config_byte(dev, 0x8c, 0x0e);
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/* Serial ATA interrupt: PIRQD */
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pci_write_config_byte(dev, 0x8d, 0x0b);
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/* SMB interrupt: PIRQH */
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pci_write_config_byte(dev, 0x8e, 0x0f);
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/* PMU ACPI SCI interrupt: PIRQH */
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pci_write_config_byte(dev, 0x8f, 0x0f);
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/* Primary PATA IDE IRQ: 14
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* Secondary PATA IDE IRQ: 15
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*/
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pci_write_config_byte(dev, 0x44, 0x3d);
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pci_write_config_byte(dev, 0x75, 0x0f);
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/* Set IRQ14 and IRQ15 to legacy IRQs */
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pci_read_config_word(dev, 0x46, &temp);
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temp |= 0xc000;
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pci_write_config_word(dev, 0x46, temp);
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/* Set i8259 interrupt trigger
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* IRQ 3: Level
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* IRQ 4: Level
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* IRQ 5: Level
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* IRQ 6: Level
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* IRQ 7: Level
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* IRQ 9: Level
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* IRQ 10: Level
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* IRQ 11: Level
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* IRQ 12: Level
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* IRQ 14: Edge
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* IRQ 15: Edge
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*/
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outb(0xfa, 0x4d0);
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outb(0x1e, 0x4d1);
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}
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static void __devinit quirk_uli5288(struct pci_dev *dev)
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{
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unsigned char c;
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pci_read_config_byte(dev,0x83,&c);
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c |= 0x80;
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pci_write_config_byte(dev, 0x83, c);
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pci_write_config_byte(dev, 0x09, 0x01);
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pci_write_config_byte(dev, 0x0a, 0x06);
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pci_read_config_byte(dev,0x83,&c);
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c &= 0x7f;
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pci_write_config_byte(dev, 0x83, c);
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pci_read_config_byte(dev,0x84,&c);
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c |= 0x01;
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pci_write_config_byte(dev, 0x84, c);
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}
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static void __devinit quirk_uli5229(struct pci_dev *dev)
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{
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unsigned short temp;
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pci_write_config_word(dev, 0x04, 0x0405);
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pci_read_config_word(dev, 0x4a, &temp);
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temp |= 0x1000;
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pci_write_config_word(dev, 0x4a, temp);
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}
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static void __devinit early_uli5249(struct pci_dev *dev)
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{
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unsigned char temp;
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pci_write_config_word(dev, 0x04, 0x0007);
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pci_read_config_byte(dev, 0x7c, &temp);
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pci_write_config_byte(dev, 0x7c, 0x80);
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pci_write_config_byte(dev, 0x09, 0x01);
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pci_write_config_byte(dev, 0x7c, temp);
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dev->class |= 0x1;
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}
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, 0x1575, quirk_ali1575);
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, 0x5288, quirk_uli5288);
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, 0x5229, quirk_uli5229);
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DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AL, 0x5249, early_uli5249);
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@ -20,10 +20,6 @@
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#ifdef CONFIG_PPC_86xx
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#ifdef CONFIG_MPC8641_HPCN
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#include <platforms/86xx/mpc8641_hpcn.h>
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#endif
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#define _IO_BASE isa_io_base
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#define _ISA_MEM_BASE isa_mem_base
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#ifdef CONFIG_PCI
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