drm/i915: cache the last object lookup during pin_and_relocate()
The most frequent relocation within a batchbuffer is a contiguous sequence of vertex buffer relocations, for which we can virtually eliminate the drm_gem_object_lookup() overhead by caching the last handle to object translation. In doing so we refactor the pin and relocate retry loop out of do_execbuffer into its own helper function and so improve the error paths. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
This commit is contained in:
Chris Wilson
Родитель
1d7cfea152
Коммит
9af90d19f8
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@ -2152,6 +2152,7 @@ i915_gem_object_unbind(struct drm_gem_object *obj)
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drm_mm_put_block(obj_priv->gtt_space);
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obj_priv->gtt_space = NULL;
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obj_priv->gtt_offset = 0;
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if (i915_gem_object_is_purgeable(obj_priv))
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i915_gem_object_truncate(obj);
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@ -2645,12 +2646,9 @@ i915_gem_object_bind_to_gtt(struct drm_gem_object *obj, unsigned alignment)
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search_free:
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free_space = drm_mm_search_free(&dev_priv->mm.gtt_space,
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obj->size, alignment, 0);
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if (free_space != NULL) {
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if (free_space != NULL)
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obj_priv->gtt_space = drm_mm_get_block(free_space, obj->size,
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alignment);
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if (obj_priv->gtt_space != NULL)
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obj_priv->gtt_offset = obj_priv->gtt_space->start;
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}
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if (obj_priv->gtt_space == NULL) {
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/* If the gtt is empty and we're still having trouble
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* fitting our object in, we're out of memory.
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@ -2693,7 +2691,7 @@ i915_gem_object_bind_to_gtt(struct drm_gem_object *obj, unsigned alignment)
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obj_priv->agp_mem = drm_agp_bind_pages(dev,
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obj_priv->pages,
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obj->size >> PAGE_SHIFT,
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obj_priv->gtt_offset,
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obj_priv->gtt_space->start,
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obj_priv->agp_type);
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if (obj_priv->agp_mem == NULL) {
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i915_gem_object_put_pages(obj);
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@ -2718,6 +2716,7 @@ i915_gem_object_bind_to_gtt(struct drm_gem_object *obj, unsigned alignment)
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BUG_ON(obj->read_domains & I915_GEM_GPU_DOMAINS);
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BUG_ON(obj->write_domain & I915_GEM_GPU_DOMAINS);
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obj_priv->gtt_offset = obj_priv->gtt_space->start;
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trace_i915_gem_object_bind(obj, obj_priv->gtt_offset);
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return 0;
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@ -3240,74 +3239,42 @@ i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj,
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* Pin an object to the GTT and evaluate the relocations landing in it.
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*/
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static int
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i915_gem_object_pin_and_relocate(struct drm_gem_object *obj,
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struct drm_file *file_priv,
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struct drm_i915_gem_exec_object2 *entry)
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i915_gem_execbuffer_relocate(struct drm_i915_gem_object *obj,
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struct drm_file *file_priv,
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struct drm_i915_gem_exec_object2 *entry)
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{
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struct drm_device *dev = obj->dev;
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struct drm_device *dev = obj->base.dev;
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drm_i915_private_t *dev_priv = dev->dev_private;
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struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
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struct drm_i915_gem_relocation_entry __user *user_relocs;
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int i, ret;
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bool need_fence;
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struct drm_gem_object *target_obj = NULL;
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uint32_t target_handle = 0;
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int i, ret = 0;
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need_fence = entry->flags & EXEC_OBJECT_NEEDS_FENCE &&
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obj_priv->tiling_mode != I915_TILING_NONE;
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/* Check fence reg constraints and rebind if necessary */
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if (need_fence &&
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!i915_gem_object_fence_offset_ok(obj,
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obj_priv->tiling_mode)) {
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ret = i915_gem_object_unbind(obj);
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if (ret)
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return ret;
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}
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/* Choose the GTT offset for our buffer and put it there. */
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ret = i915_gem_object_pin(obj, (uint32_t) entry->alignment);
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if (ret)
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return ret;
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/*
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* Pre-965 chips need a fence register set up in order to
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* properly handle blits to/from tiled surfaces.
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*/
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if (need_fence) {
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ret = i915_gem_object_get_fence_reg(obj, true);
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if (ret != 0) {
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i915_gem_object_unpin(obj);
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return ret;
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}
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dev_priv->fence_regs[obj_priv->fence_reg].gpu = true;
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}
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entry->offset = obj_priv->gtt_offset;
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/* Apply the relocations, using the GTT aperture to avoid cache
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* flushing requirements.
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*/
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user_relocs = (void __user *)(uintptr_t)entry->relocs_ptr;
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for (i = 0; i < entry->relocation_count; i++) {
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struct drm_i915_gem_relocation_entry reloc;
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struct drm_gem_object *target_obj;
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struct drm_i915_gem_object *target_obj_priv;
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uint32_t target_offset;
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ret = __copy_from_user_inatomic(&reloc,
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user_relocs+i,
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sizeof(reloc));
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if (ret) {
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i915_gem_object_unpin(obj);
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return -EFAULT;
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if (__copy_from_user_inatomic(&reloc,
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user_relocs+i,
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sizeof(reloc))) {
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ret = -EFAULT;
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break;
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}
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target_obj = drm_gem_object_lookup(obj->dev, file_priv,
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reloc.target_handle);
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if (target_obj == NULL) {
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i915_gem_object_unpin(obj);
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return -ENOENT;
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if (reloc.target_handle != target_handle) {
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drm_gem_object_unreference(target_obj);
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target_obj = drm_gem_object_lookup(dev, file_priv,
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reloc.target_handle);
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if (target_obj == NULL) {
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ret = -ENOENT;
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break;
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}
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target_handle = reloc.target_handle;
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}
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target_obj_priv = to_intel_bo(target_obj);
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target_offset = to_intel_bo(target_obj)->gtt_offset;
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#if WATCH_RELOC
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DRM_INFO("%s: obj %p offset %08x target %d "
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@ -3319,7 +3286,7 @@ i915_gem_object_pin_and_relocate(struct drm_gem_object *obj,
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(int) reloc.target_handle,
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(int) reloc.read_domains,
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(int) reloc.write_domain,
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(int) target_obj_priv->gtt_offset,
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(int) target_offset,
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(int) reloc.presumed_offset,
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reloc.delta);
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#endif
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@ -3327,12 +3294,11 @@ i915_gem_object_pin_and_relocate(struct drm_gem_object *obj,
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/* The target buffer should have appeared before us in the
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* exec_object list, so it should have a GTT space bound by now.
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*/
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if (target_obj_priv->gtt_space == NULL) {
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if (target_offset == 0) {
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DRM_ERROR("No GTT space found for object %d\n",
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reloc.target_handle);
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drm_gem_object_unreference(target_obj);
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i915_gem_object_unpin(obj);
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return -EINVAL;
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ret = -EINVAL;
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break;
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}
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/* Validate that the target is in a valid r/w GPU domain */
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@ -3344,9 +3310,8 @@ i915_gem_object_pin_and_relocate(struct drm_gem_object *obj,
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(int) reloc.offset,
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reloc.read_domains,
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reloc.write_domain);
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drm_gem_object_unreference(target_obj);
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i915_gem_object_unpin(obj);
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return -EINVAL;
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ret = -EINVAL;
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break;
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}
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if (reloc.write_domain & I915_GEM_DOMAIN_CPU ||
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reloc.read_domains & I915_GEM_DOMAIN_CPU) {
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@ -3357,9 +3322,8 @@ i915_gem_object_pin_and_relocate(struct drm_gem_object *obj,
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(int) reloc.offset,
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reloc.read_domains,
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reloc.write_domain);
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drm_gem_object_unreference(target_obj);
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i915_gem_object_unpin(obj);
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return -EINVAL;
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ret = -EINVAL;
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break;
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}
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if (reloc.write_domain && target_obj->pending_write_domain &&
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reloc.write_domain != target_obj->pending_write_domain) {
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@ -3370,40 +3334,35 @@ i915_gem_object_pin_and_relocate(struct drm_gem_object *obj,
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(int) reloc.offset,
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reloc.write_domain,
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target_obj->pending_write_domain);
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drm_gem_object_unreference(target_obj);
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i915_gem_object_unpin(obj);
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return -EINVAL;
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ret = -EINVAL;
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break;
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}
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target_obj->pending_read_domains |= reloc.read_domains;
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target_obj->pending_write_domain |= reloc.write_domain;
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target_obj->pending_write_domain = reloc.write_domain;
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/* If the relocation already has the right value in it, no
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* more work needs to be done.
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*/
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if (target_obj_priv->gtt_offset == reloc.presumed_offset) {
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drm_gem_object_unreference(target_obj);
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if (target_offset == reloc.presumed_offset)
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continue;
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}
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/* Check that the relocation address is valid... */
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if (reloc.offset > obj->size - 4) {
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if (reloc.offset > obj->base.size - 4) {
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DRM_ERROR("Relocation beyond object bounds: "
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"obj %p target %d offset %d size %d.\n",
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obj, reloc.target_handle,
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(int) reloc.offset, (int) obj->size);
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drm_gem_object_unreference(target_obj);
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i915_gem_object_unpin(obj);
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return -EINVAL;
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(int) reloc.offset, (int) obj->base.size);
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ret = -EINVAL;
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break;
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}
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if (reloc.offset & 3) {
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DRM_ERROR("Relocation not 4-byte aligned: "
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"obj %p target %d offset %d.\n",
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obj, reloc.target_handle,
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(int) reloc.offset);
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drm_gem_object_unreference(target_obj);
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i915_gem_object_unpin(obj);
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return -EINVAL;
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ret = -EINVAL;
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break;
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}
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/* and points to somewhere within the target object. */
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@ -3412,33 +3371,28 @@ i915_gem_object_pin_and_relocate(struct drm_gem_object *obj,
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"obj %p target %d delta %d size %d.\n",
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obj, reloc.target_handle,
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(int) reloc.delta, (int) target_obj->size);
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drm_gem_object_unreference(target_obj);
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i915_gem_object_unpin(obj);
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return -EINVAL;
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ret = -EINVAL;
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break;
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}
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reloc.delta += target_obj_priv->gtt_offset;
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if (obj->write_domain == I915_GEM_DOMAIN_CPU) {
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reloc.delta += target_offset;
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if (obj->base.write_domain == I915_GEM_DOMAIN_CPU) {
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uint32_t page_offset = reloc.offset & ~PAGE_MASK;
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char *vaddr;
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vaddr = kmap_atomic(obj_priv->pages[reloc.offset >> PAGE_SHIFT], KM_USER0);
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vaddr = kmap_atomic(obj->pages[reloc.offset >> PAGE_SHIFT], KM_USER0);
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*(uint32_t *)(vaddr + page_offset) = reloc.delta;
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kunmap_atomic(vaddr, KM_USER0);
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} else {
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uint32_t __iomem *reloc_entry;
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void __iomem *reloc_page;
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int ret;
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ret = i915_gem_object_set_to_gtt_domain(obj, 1);
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if (ret) {
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drm_gem_object_unreference(target_obj);
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i915_gem_object_unpin(obj);
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return ret;
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}
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ret = i915_gem_object_set_to_gtt_domain(&obj->base, 1);
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if (ret)
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break;
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/* Map the page containing the relocation we're going to perform. */
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reloc.offset += obj_priv->gtt_offset;
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reloc.offset += obj->gtt_offset;
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reloc_page = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping,
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reloc.offset & PAGE_MASK,
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KM_USER0);
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@ -3447,8 +3401,74 @@ i915_gem_object_pin_and_relocate(struct drm_gem_object *obj,
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iowrite32(reloc.delta, reloc_entry);
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io_mapping_unmap_atomic(reloc_page, KM_USER0);
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}
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}
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drm_gem_object_unreference(target_obj);
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drm_gem_object_unreference(target_obj);
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return ret;
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}
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static int
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i915_gem_execbuffer_pin(struct drm_device *dev,
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struct drm_file *file,
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struct drm_gem_object **object_list,
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struct drm_i915_gem_exec_object2 *exec_list,
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int count)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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int ret, i, retry;
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/* attempt to pin all of the buffers into the GTT */
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for (retry = 0; retry < 2; retry++) {
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ret = 0;
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for (i = 0; i < count; i++) {
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struct drm_i915_gem_exec_object2 *entry = &exec_list[i];
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struct drm_i915_gem_object *obj= to_intel_bo(object_list[i]);
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bool need_fence =
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entry->flags & EXEC_OBJECT_NEEDS_FENCE &&
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obj->tiling_mode != I915_TILING_NONE;
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/* Check fence reg constraints and rebind if necessary */
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if (need_fence &&
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!i915_gem_object_fence_offset_ok(&obj->base,
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obj->tiling_mode)) {
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ret = i915_gem_object_unbind(&obj->base);
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if (ret)
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break;
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}
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ret = i915_gem_object_pin(&obj->base, entry->alignment);
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if (ret)
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break;
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/*
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* Pre-965 chips need a fence register set up in order
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* to properly handle blits to/from tiled surfaces.
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*/
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if (need_fence) {
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ret = i915_gem_object_get_fence_reg(&obj->base, true);
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if (ret) {
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i915_gem_object_unpin(&obj->base);
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break;
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}
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dev_priv->fence_regs[obj->fence_reg].gpu = true;
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}
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entry->offset = obj->gtt_offset;
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}
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while (i--)
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i915_gem_object_unpin(object_list[i]);
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if (ret == 0)
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break;
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if (ret != -ENOSPC || retry)
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return ret;
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ret = i915_gem_evict_everything(dev);
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if (ret)
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return ret;
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}
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return 0;
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@ -3551,7 +3571,7 @@ validate_exec_list(struct drm_i915_gem_exec_object2 *exec,
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static int
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i915_gem_do_execbuffer(struct drm_device *dev, void *data,
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struct drm_file *file_priv,
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struct drm_file *file,
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struct drm_i915_gem_execbuffer2 *args,
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struct drm_i915_gem_exec_object2 *exec_list)
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{
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@ -3561,9 +3581,8 @@ i915_gem_do_execbuffer(struct drm_device *dev, void *data,
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struct drm_i915_gem_object *obj_priv;
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struct drm_clip_rect *cliprects = NULL;
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struct drm_i915_gem_request *request = NULL;
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int ret, i, pinned = 0;
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int ret, i, flips;
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uint64_t exec_offset;
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int pin_tries, flips;
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struct intel_ring_buffer *ring = NULL;
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@ -3639,7 +3658,7 @@ i915_gem_do_execbuffer(struct drm_device *dev, void *data,
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/* Look up object handles */
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for (i = 0; i < args->buffer_count; i++) {
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object_list[i] = drm_gem_object_lookup(dev, file_priv,
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object_list[i] = drm_gem_object_lookup(dev, file,
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exec_list[i].handle);
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if (object_list[i] == NULL) {
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DRM_ERROR("Invalid object handle %d at index %d\n",
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@ -3662,63 +3681,20 @@ i915_gem_do_execbuffer(struct drm_device *dev, void *data,
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obj_priv->in_execbuffer = true;
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}
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/* Pin and relocate */
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for (pin_tries = 0; ; pin_tries++) {
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ret = 0;
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/* Move the objects en-masse into the GTT, evicting if necessary. */
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ret = i915_gem_execbuffer_pin(dev, file,
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object_list, exec_list,
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args->buffer_count);
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if (ret)
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goto err;
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for (i = 0; i < args->buffer_count; i++) {
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object_list[i]->pending_read_domains = 0;
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object_list[i]->pending_write_domain = 0;
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ret = i915_gem_object_pin_and_relocate(object_list[i],
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file_priv,
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&exec_list[i]);
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if (ret)
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break;
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pinned = i + 1;
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}
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/* success */
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if (ret == 0)
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break;
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/* error other than GTT full, or we've already tried again */
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if (ret != -ENOSPC || pin_tries >= 1) {
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if (ret != -ERESTARTSYS) {
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unsigned long long total_size = 0;
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int num_fences = 0;
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for (i = 0; i < args->buffer_count; i++) {
|
||||
obj_priv = to_intel_bo(object_list[i]);
|
||||
|
||||
total_size += object_list[i]->size;
|
||||
num_fences +=
|
||||
exec_list[i].flags & EXEC_OBJECT_NEEDS_FENCE &&
|
||||
obj_priv->tiling_mode != I915_TILING_NONE;
|
||||
}
|
||||
DRM_ERROR("Failed to pin buffer %d of %d, total %llu bytes, %d fences: %d\n",
|
||||
pinned+1, args->buffer_count,
|
||||
total_size, num_fences,
|
||||
ret);
|
||||
DRM_ERROR("%u objects [%u pinned, %u GTT], "
|
||||
"%zu object bytes [%zu pinned], "
|
||||
"%zu /%zu gtt bytes\n",
|
||||
dev_priv->mm.object_count,
|
||||
dev_priv->mm.pin_count,
|
||||
dev_priv->mm.gtt_count,
|
||||
dev_priv->mm.object_memory,
|
||||
dev_priv->mm.pin_memory,
|
||||
dev_priv->mm.gtt_memory,
|
||||
dev_priv->mm.gtt_total);
|
||||
}
|
||||
goto err;
|
||||
}
|
||||
|
||||
/* unpin all of our buffers */
|
||||
for (i = 0; i < pinned; i++)
|
||||
i915_gem_object_unpin(object_list[i]);
|
||||
pinned = 0;
|
||||
|
||||
/* evict everyone we can from the aperture */
|
||||
ret = i915_gem_evict_everything(dev);
|
||||
if (ret && ret != -ENOSPC)
|
||||
/* The objects are in their final locations, apply the relocations. */
|
||||
for (i = 0; i < args->buffer_count; i++) {
|
||||
struct drm_i915_gem_object *obj = to_intel_bo(object_list[i]);
|
||||
obj->base.pending_read_domains = 0;
|
||||
obj->base.pending_write_domain = 0;
|
||||
ret = i915_gem_execbuffer_relocate(obj, file, &exec_list[i]);
|
||||
if (ret)
|
||||
goto err;
|
||||
}
|
||||
|
||||
|
|
@ -3731,9 +3707,9 @@ i915_gem_do_execbuffer(struct drm_device *dev, void *data,
|
|||
}
|
||||
batch_obj->pending_read_domains |= I915_GEM_DOMAIN_COMMAND;
|
||||
|
||||
/* Sanity check the batch buffer, prior to moving objects */
|
||||
exec_offset = exec_list[args->buffer_count - 1].offset;
|
||||
ret = i915_gem_check_execbuffer (args, exec_offset);
|
||||
/* Sanity check the batch buffer */
|
||||
exec_offset = to_intel_bo(batch_obj)->gtt_offset;
|
||||
ret = i915_gem_check_execbuffer(args, exec_offset);
|
||||
if (ret != 0) {
|
||||
DRM_ERROR("execbuf with invalid offset/length\n");
|
||||
goto err;
|
||||
|
|
@ -3761,7 +3737,7 @@ i915_gem_do_execbuffer(struct drm_device *dev, void *data,
|
|||
dev->invalidate_domains,
|
||||
dev->flush_domains);
|
||||
#endif
|
||||
i915_gem_flush(dev, file_priv,
|
||||
i915_gem_flush(dev, file,
|
||||
dev->invalidate_domains,
|
||||
dev->flush_domains,
|
||||
dev_priv->mm.flush_rings);
|
||||
|
|
@ -3846,13 +3822,10 @@ i915_gem_do_execbuffer(struct drm_device *dev, void *data,
|
|||
i915_gem_object_move_to_active(obj, ring);
|
||||
}
|
||||
|
||||
i915_add_request(dev, file_priv, request, ring);
|
||||
i915_add_request(dev, file, request, ring);
|
||||
request = NULL;
|
||||
|
||||
err:
|
||||
for (i = 0; i < pinned; i++)
|
||||
i915_gem_object_unpin(object_list[i]);
|
||||
|
||||
for (i = 0; i < args->buffer_count; i++) {
|
||||
if (object_list[i]) {
|
||||
obj_priv = to_intel_bo(object_list[i]);
|
||||
|
|
|
|||
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Ссылка в новой задаче