Merge branch 'nvme-4.16' of git://git.infradead.org/nvme into for-4.16/block
Pull NVMe fixes for 4.16 from Christoph. * 'nvme-4.16' of git://git.infradead.org/nvme: nvme-pci: clean up SMBSZ bit definitions nvme-pci: clean up CMB initialization nvme-fc: correct hang in nvme_ns_remove() nvme-fc: fix rogue admin cmds stalling teardown nvmet: release a ns reference in nvmet_req_uninit if needed nvme-fabrics: fix memory leak when parsing host ID option nvme: fix comment typos in nvme_create_io_queues nvme: host delete_work and reset_work on separate workqueues nvme-pci: allocate device queues storage space at probe nvme-pci: serialize pci resets
This commit is contained in:
Jens Axboe
Коммит
9b9c63f71b
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@ -65,9 +65,26 @@ static bool streams;
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module_param(streams, bool, 0644);
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MODULE_PARM_DESC(streams, "turn on support for Streams write directives");
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/*
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* nvme_wq - hosts nvme related works that are not reset or delete
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* nvme_reset_wq - hosts nvme reset works
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* nvme_delete_wq - hosts nvme delete works
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*
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* nvme_wq will host works such are scan, aen handling, fw activation,
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* keep-alive error recovery, periodic reconnects etc. nvme_reset_wq
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* runs reset works which also flush works hosted on nvme_wq for
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* serialization purposes. nvme_delete_wq host controller deletion
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* works which flush reset works for serialization.
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*/
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struct workqueue_struct *nvme_wq;
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EXPORT_SYMBOL_GPL(nvme_wq);
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struct workqueue_struct *nvme_reset_wq;
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EXPORT_SYMBOL_GPL(nvme_reset_wq);
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struct workqueue_struct *nvme_delete_wq;
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EXPORT_SYMBOL_GPL(nvme_delete_wq);
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static DEFINE_IDA(nvme_subsystems_ida);
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static LIST_HEAD(nvme_subsystems);
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static DEFINE_MUTEX(nvme_subsystems_lock);
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@ -89,13 +106,13 @@ int nvme_reset_ctrl(struct nvme_ctrl *ctrl)
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{
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if (!nvme_change_ctrl_state(ctrl, NVME_CTRL_RESETTING))
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return -EBUSY;
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if (!queue_work(nvme_wq, &ctrl->reset_work))
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if (!queue_work(nvme_reset_wq, &ctrl->reset_work))
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return -EBUSY;
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return 0;
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}
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EXPORT_SYMBOL_GPL(nvme_reset_ctrl);
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static int nvme_reset_ctrl_sync(struct nvme_ctrl *ctrl)
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int nvme_reset_ctrl_sync(struct nvme_ctrl *ctrl)
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{
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int ret;
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@ -104,6 +121,7 @@ static int nvme_reset_ctrl_sync(struct nvme_ctrl *ctrl)
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flush_work(&ctrl->reset_work);
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return ret;
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}
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EXPORT_SYMBOL_GPL(nvme_reset_ctrl_sync);
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static void nvme_delete_ctrl_work(struct work_struct *work)
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{
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@ -122,7 +140,7 @@ int nvme_delete_ctrl(struct nvme_ctrl *ctrl)
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{
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if (!nvme_change_ctrl_state(ctrl, NVME_CTRL_DELETING))
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return -EBUSY;
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if (!queue_work(nvme_wq, &ctrl->delete_work))
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if (!queue_work(nvme_delete_wq, &ctrl->delete_work))
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return -EBUSY;
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return 0;
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}
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@ -3525,16 +3543,26 @@ EXPORT_SYMBOL_GPL(nvme_reinit_tagset);
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int __init nvme_core_init(void)
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{
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int result;
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int result = -ENOMEM;
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nvme_wq = alloc_workqueue("nvme-wq",
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WQ_UNBOUND | WQ_MEM_RECLAIM | WQ_SYSFS, 0);
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if (!nvme_wq)
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return -ENOMEM;
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goto out;
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nvme_reset_wq = alloc_workqueue("nvme-reset-wq",
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WQ_UNBOUND | WQ_MEM_RECLAIM | WQ_SYSFS, 0);
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if (!nvme_reset_wq)
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goto destroy_wq;
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nvme_delete_wq = alloc_workqueue("nvme-delete-wq",
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WQ_UNBOUND | WQ_MEM_RECLAIM | WQ_SYSFS, 0);
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if (!nvme_delete_wq)
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goto destroy_reset_wq;
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result = alloc_chrdev_region(&nvme_chr_devt, 0, NVME_MINORS, "nvme");
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if (result < 0)
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goto destroy_wq;
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goto destroy_delete_wq;
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nvme_class = class_create(THIS_MODULE, "nvme");
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if (IS_ERR(nvme_class)) {
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@ -3553,8 +3581,13 @@ destroy_class:
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class_destroy(nvme_class);
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unregister_chrdev:
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unregister_chrdev_region(nvme_chr_devt, NVME_MINORS);
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destroy_delete_wq:
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destroy_workqueue(nvme_delete_wq);
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destroy_reset_wq:
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destroy_workqueue(nvme_reset_wq);
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destroy_wq:
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destroy_workqueue(nvme_wq);
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out:
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return result;
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}
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@ -3564,6 +3597,8 @@ void nvme_core_exit(void)
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class_destroy(nvme_subsys_class);
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class_destroy(nvme_class);
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unregister_chrdev_region(nvme_chr_devt, NVME_MINORS);
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destroy_workqueue(nvme_delete_wq);
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destroy_workqueue(nvme_reset_wq);
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destroy_workqueue(nvme_wq);
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}
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@ -738,7 +738,9 @@ static int nvmf_parse_options(struct nvmf_ctrl_options *opts,
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ret = -ENOMEM;
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goto out;
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}
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if (uuid_parse(p, &hostid)) {
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ret = uuid_parse(p, &hostid);
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kfree(p);
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if (ret) {
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pr_err("Invalid hostid %s\n", p);
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ret = -EINVAL;
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goto out;
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@ -2921,6 +2921,9 @@ nvme_fc_delete_association(struct nvme_fc_ctrl *ctrl)
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__nvme_fc_delete_hw_queue(ctrl, &ctrl->queues[0], 0);
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nvme_fc_free_queue(&ctrl->queues[0]);
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/* re-enable the admin_q so anything new can fast fail */
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blk_mq_unquiesce_queue(ctrl->ctrl.admin_q);
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nvme_fc_ctlr_inactive_on_rport(ctrl);
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}
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@ -2935,6 +2938,9 @@ nvme_fc_delete_ctrl(struct nvme_ctrl *nctrl)
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* waiting for io to terminate
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*/
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nvme_fc_delete_association(ctrl);
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/* resume the io queues so that things will fast fail */
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nvme_start_queues(nctrl);
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}
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static void
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@ -32,6 +32,8 @@ extern unsigned int admin_timeout;
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#define NVME_KATO_GRACE 10
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extern struct workqueue_struct *nvme_wq;
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extern struct workqueue_struct *nvme_reset_wq;
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extern struct workqueue_struct *nvme_delete_wq;
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enum {
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NVME_NS_LBA = 0,
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@ -394,6 +396,7 @@ int nvme_set_queue_count(struct nvme_ctrl *ctrl, int *count);
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void nvme_start_keep_alive(struct nvme_ctrl *ctrl);
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void nvme_stop_keep_alive(struct nvme_ctrl *ctrl);
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int nvme_reset_ctrl(struct nvme_ctrl *ctrl);
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int nvme_reset_ctrl_sync(struct nvme_ctrl *ctrl);
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int nvme_delete_ctrl(struct nvme_ctrl *ctrl);
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int nvme_delete_ctrl_sync(struct nvme_ctrl *ctrl);
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@ -75,7 +75,7 @@ static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown);
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* Represents an NVM Express device. Each nvme_dev is a PCI function.
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*/
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struct nvme_dev {
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struct nvme_queue **queues;
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struct nvme_queue *queues;
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struct blk_mq_tag_set tagset;
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struct blk_mq_tag_set admin_tagset;
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u32 __iomem *dbs;
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@ -365,7 +365,7 @@ static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
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unsigned int hctx_idx)
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{
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struct nvme_dev *dev = data;
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struct nvme_queue *nvmeq = dev->queues[0];
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struct nvme_queue *nvmeq = &dev->queues[0];
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WARN_ON(hctx_idx != 0);
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WARN_ON(dev->admin_tagset.tags[0] != hctx->tags);
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@ -387,7 +387,7 @@ static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
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unsigned int hctx_idx)
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{
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struct nvme_dev *dev = data;
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struct nvme_queue *nvmeq = dev->queues[hctx_idx + 1];
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struct nvme_queue *nvmeq = &dev->queues[hctx_idx + 1];
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if (!nvmeq->tags)
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nvmeq->tags = &dev->tagset.tags[hctx_idx];
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@ -403,7 +403,7 @@ static int nvme_init_request(struct blk_mq_tag_set *set, struct request *req,
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struct nvme_dev *dev = set->driver_data;
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struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
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int queue_idx = (set == &dev->tagset) ? hctx_idx + 1 : 0;
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struct nvme_queue *nvmeq = dev->queues[queue_idx];
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struct nvme_queue *nvmeq = &dev->queues[queue_idx];
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BUG_ON(!nvmeq);
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iod->nvmeq = nvmeq;
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@ -1046,7 +1046,7 @@ static int nvme_poll(struct blk_mq_hw_ctx *hctx, unsigned int tag)
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static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl)
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{
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struct nvme_dev *dev = to_nvme_dev(ctrl);
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struct nvme_queue *nvmeq = dev->queues[0];
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struct nvme_queue *nvmeq = &dev->queues[0];
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struct nvme_command c;
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memset(&c, 0, sizeof(c));
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@ -1282,7 +1282,6 @@ static void nvme_free_queue(struct nvme_queue *nvmeq)
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if (nvmeq->sq_cmds)
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dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth),
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nvmeq->sq_cmds, nvmeq->sq_dma_addr);
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kfree(nvmeq);
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}
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static void nvme_free_queues(struct nvme_dev *dev, int lowest)
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@ -1290,10 +1289,8 @@ static void nvme_free_queues(struct nvme_dev *dev, int lowest)
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int i;
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for (i = dev->ctrl.queue_count - 1; i >= lowest; i--) {
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struct nvme_queue *nvmeq = dev->queues[i];
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dev->ctrl.queue_count--;
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dev->queues[i] = NULL;
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nvme_free_queue(nvmeq);
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nvme_free_queue(&dev->queues[i]);
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}
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}
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@ -1325,10 +1322,8 @@ static int nvme_suspend_queue(struct nvme_queue *nvmeq)
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static void nvme_disable_admin_queue(struct nvme_dev *dev, bool shutdown)
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{
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struct nvme_queue *nvmeq = dev->queues[0];
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struct nvme_queue *nvmeq = &dev->queues[0];
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if (!nvmeq)
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return;
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if (nvme_suspend_queue(nvmeq))
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return;
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@ -1369,7 +1364,7 @@ static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues,
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static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq,
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int qid, int depth)
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{
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if (qid && dev->cmb && use_cmb_sqes && NVME_CMB_SQS(dev->cmbsz)) {
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if (qid && dev->cmb && use_cmb_sqes && (dev->cmbsz & NVME_CMBSZ_SQS)) {
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unsigned offset = (qid - 1) * roundup(SQ_SIZE(depth),
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dev->ctrl.page_size);
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nvmeq->sq_dma_addr = dev->cmb_bus_addr + offset;
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@ -1384,13 +1379,10 @@ static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq,
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return 0;
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}
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static struct nvme_queue *nvme_alloc_queue(struct nvme_dev *dev, int qid,
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int depth, int node)
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static int nvme_alloc_queue(struct nvme_dev *dev, int qid,
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int depth, int node)
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{
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struct nvme_queue *nvmeq = kzalloc_node(sizeof(*nvmeq), GFP_KERNEL,
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node);
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if (!nvmeq)
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return NULL;
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struct nvme_queue *nvmeq = &dev->queues[qid];
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|
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nvmeq->cqes = dma_zalloc_coherent(dev->dev, CQ_SIZE(depth),
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&nvmeq->cq_dma_addr, GFP_KERNEL);
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|
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@ -1409,17 +1401,15 @@ static struct nvme_queue *nvme_alloc_queue(struct nvme_dev *dev, int qid,
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nvmeq->q_depth = depth;
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nvmeq->qid = qid;
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nvmeq->cq_vector = -1;
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dev->queues[qid] = nvmeq;
|
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dev->ctrl.queue_count++;
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|
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return nvmeq;
|
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return 0;
|
||||
|
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free_cqdma:
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dma_free_coherent(dev->dev, CQ_SIZE(depth), (void *)nvmeq->cqes,
|
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nvmeq->cq_dma_addr);
|
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free_nvmeq:
|
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kfree(nvmeq);
|
||||
return NULL;
|
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return -ENOMEM;
|
||||
}
|
||||
|
||||
static int queue_request_irq(struct nvme_queue *nvmeq)
|
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|
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@ -1592,14 +1582,12 @@ static int nvme_pci_configure_admin_queue(struct nvme_dev *dev)
|
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if (result < 0)
|
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return result;
|
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|
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nvmeq = dev->queues[0];
|
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if (!nvmeq) {
|
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nvmeq = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH,
|
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dev_to_node(dev->dev));
|
||||
if (!nvmeq)
|
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return -ENOMEM;
|
||||
}
|
||||
result = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH,
|
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dev_to_node(dev->dev));
|
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if (result)
|
||||
return result;
|
||||
|
||||
nvmeq = &dev->queues[0];
|
||||
aqa = nvmeq->q_depth - 1;
|
||||
aqa |= aqa << 16;
|
||||
|
||||
|
|
@ -1629,7 +1617,7 @@ static int nvme_create_io_queues(struct nvme_dev *dev)
|
|||
|
||||
for (i = dev->ctrl.queue_count; i <= dev->max_qid; i++) {
|
||||
/* vector == qid - 1, match nvme_create_queue */
|
||||
if (!nvme_alloc_queue(dev, i, dev->q_depth,
|
||||
if (nvme_alloc_queue(dev, i, dev->q_depth,
|
||||
pci_irq_get_node(to_pci_dev(dev->dev), i - 1))) {
|
||||
ret = -ENOMEM;
|
||||
break;
|
||||
|
|
@ -1638,15 +1626,15 @@ static int nvme_create_io_queues(struct nvme_dev *dev)
|
|||
|
||||
max = min(dev->max_qid, dev->ctrl.queue_count - 1);
|
||||
for (i = dev->online_queues; i <= max; i++) {
|
||||
ret = nvme_create_queue(dev->queues[i], i);
|
||||
ret = nvme_create_queue(&dev->queues[i], i);
|
||||
if (ret)
|
||||
break;
|
||||
}
|
||||
|
||||
/*
|
||||
* Ignore failing Create SQ/CQ commands, we can continue with less
|
||||
* than the desired aount of queues, and even a controller without
|
||||
* I/O queues an still be used to issue admin commands. This might
|
||||
* than the desired amount of queues, and even a controller without
|
||||
* I/O queues can still be used to issue admin commands. This might
|
||||
* be useful to upgrade a buggy firmware for example.
|
||||
*/
|
||||
return ret >= 0 ? 0 : ret;
|
||||
|
|
@ -1663,30 +1651,40 @@ static ssize_t nvme_cmb_show(struct device *dev,
|
|||
}
|
||||
static DEVICE_ATTR(cmb, S_IRUGO, nvme_cmb_show, NULL);
|
||||
|
||||
static void __iomem *nvme_map_cmb(struct nvme_dev *dev)
|
||||
static u64 nvme_cmb_size_unit(struct nvme_dev *dev)
|
||||
{
|
||||
u64 szu, size, offset;
|
||||
u8 szu = (dev->cmbsz >> NVME_CMBSZ_SZU_SHIFT) & NVME_CMBSZ_SZU_MASK;
|
||||
|
||||
return 1ULL << (12 + 4 * szu);
|
||||
}
|
||||
|
||||
static u32 nvme_cmb_size(struct nvme_dev *dev)
|
||||
{
|
||||
return (dev->cmbsz >> NVME_CMBSZ_SZ_SHIFT) & NVME_CMBSZ_SZ_MASK;
|
||||
}
|
||||
|
||||
static void nvme_map_cmb(struct nvme_dev *dev)
|
||||
{
|
||||
u64 size, offset;
|
||||
resource_size_t bar_size;
|
||||
struct pci_dev *pdev = to_pci_dev(dev->dev);
|
||||
void __iomem *cmb;
|
||||
int bar;
|
||||
|
||||
dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ);
|
||||
if (!(NVME_CMB_SZ(dev->cmbsz)))
|
||||
return NULL;
|
||||
if (!dev->cmbsz)
|
||||
return;
|
||||
dev->cmbloc = readl(dev->bar + NVME_REG_CMBLOC);
|
||||
|
||||
if (!use_cmb_sqes)
|
||||
return NULL;
|
||||
return;
|
||||
|
||||
szu = (u64)1 << (12 + 4 * NVME_CMB_SZU(dev->cmbsz));
|
||||
size = szu * NVME_CMB_SZ(dev->cmbsz);
|
||||
offset = szu * NVME_CMB_OFST(dev->cmbloc);
|
||||
size = nvme_cmb_size_unit(dev) * nvme_cmb_size(dev);
|
||||
offset = nvme_cmb_size_unit(dev) * NVME_CMB_OFST(dev->cmbloc);
|
||||
bar = NVME_CMB_BIR(dev->cmbloc);
|
||||
bar_size = pci_resource_len(pdev, bar);
|
||||
|
||||
if (offset > bar_size)
|
||||
return NULL;
|
||||
return;
|
||||
|
||||
/*
|
||||
* Controllers may support a CMB size larger than their BAR,
|
||||
|
|
@ -1696,13 +1694,16 @@ static void __iomem *nvme_map_cmb(struct nvme_dev *dev)
|
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if (size > bar_size - offset)
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size = bar_size - offset;
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||||
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||||
cmb = ioremap_wc(pci_resource_start(pdev, bar) + offset, size);
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if (!cmb)
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return NULL;
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||||
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||||
dev->cmb = ioremap_wc(pci_resource_start(pdev, bar) + offset, size);
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||||
if (!dev->cmb)
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return;
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dev->cmb_bus_addr = pci_bus_address(pdev, bar) + offset;
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dev->cmb_size = size;
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return cmb;
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||||
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if (sysfs_add_file_to_group(&dev->ctrl.device->kobj,
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&dev_attr_cmb.attr, NULL))
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dev_warn(dev->ctrl.device,
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"failed to add sysfs attribute for CMB\n");
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}
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static inline void nvme_release_cmb(struct nvme_dev *dev)
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@ -1894,7 +1895,7 @@ static int nvme_setup_host_mem(struct nvme_dev *dev)
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static int nvme_setup_io_queues(struct nvme_dev *dev)
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{
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struct nvme_queue *adminq = dev->queues[0];
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struct nvme_queue *adminq = &dev->queues[0];
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struct pci_dev *pdev = to_pci_dev(dev->dev);
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int result, nr_io_queues;
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unsigned long size;
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@ -1907,7 +1908,7 @@ static int nvme_setup_io_queues(struct nvme_dev *dev)
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if (nr_io_queues == 0)
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return 0;
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if (dev->cmb && NVME_CMB_SQS(dev->cmbsz)) {
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if (dev->cmb && (dev->cmbsz & NVME_CMBSZ_SQS)) {
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result = nvme_cmb_qdepth(dev, nr_io_queues,
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sizeof(struct nvme_command));
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if (result > 0)
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|
|
@ -2020,7 +2021,7 @@ static void nvme_disable_io_queues(struct nvme_dev *dev, int queues)
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retry:
|
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timeout = ADMIN_TIMEOUT;
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for (; i > 0; i--, sent++)
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if (nvme_delete_queue(dev->queues[i], opcode))
|
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if (nvme_delete_queue(&dev->queues[i], opcode))
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break;
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||||
|
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while (sent--) {
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|
|
@ -2127,22 +2128,7 @@ static int nvme_pci_enable(struct nvme_dev *dev)
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"set queue depth=%u\n", dev->q_depth);
|
||||
}
|
||||
|
||||
/*
|
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* CMBs can currently only exist on >=1.2 PCIe devices. We only
|
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* populate sysfs if a CMB is implemented. Since nvme_dev_attrs_group
|
||||
* has no name we can pass NULL as final argument to
|
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* sysfs_add_file_to_group.
|
||||
*/
|
||||
|
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if (readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 2, 0)) {
|
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dev->cmb = nvme_map_cmb(dev);
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if (dev->cmb) {
|
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if (sysfs_add_file_to_group(&dev->ctrl.device->kobj,
|
||||
&dev_attr_cmb.attr, NULL))
|
||||
dev_warn(dev->ctrl.device,
|
||||
"failed to add sysfs attribute for CMB\n");
|
||||
}
|
||||
}
|
||||
nvme_map_cmb(dev);
|
||||
|
||||
pci_enable_pcie_error_reporting(pdev);
|
||||
pci_save_state(pdev);
|
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|
|
@ -2212,7 +2198,7 @@ static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown)
|
|||
|
||||
queues = dev->online_queues - 1;
|
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for (i = dev->ctrl.queue_count - 1; i > 0; i--)
|
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nvme_suspend_queue(dev->queues[i]);
|
||||
nvme_suspend_queue(&dev->queues[i]);
|
||||
|
||||
if (dead) {
|
||||
/* A device might become IO incapable very soon during
|
||||
|
|
@ -2220,7 +2206,7 @@ static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown)
|
|||
* queue_count can be 0 here.
|
||||
*/
|
||||
if (dev->ctrl.queue_count)
|
||||
nvme_suspend_queue(dev->queues[0]);
|
||||
nvme_suspend_queue(&dev->queues[0]);
|
||||
} else {
|
||||
nvme_disable_io_queues(dev, queues);
|
||||
nvme_disable_admin_queue(dev, shutdown);
|
||||
|
|
@ -2482,8 +2468,9 @@ static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id)
|
|||
dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node);
|
||||
if (!dev)
|
||||
return -ENOMEM;
|
||||
dev->queues = kzalloc_node((num_possible_cpus() + 1) * sizeof(void *),
|
||||
GFP_KERNEL, node);
|
||||
|
||||
dev->queues = kcalloc_node(num_possible_cpus() + 1,
|
||||
sizeof(struct nvme_queue), GFP_KERNEL, node);
|
||||
if (!dev->queues)
|
||||
goto free;
|
||||
|
||||
|
|
@ -2537,7 +2524,7 @@ static void nvme_reset_prepare(struct pci_dev *pdev)
|
|||
static void nvme_reset_done(struct pci_dev *pdev)
|
||||
{
|
||||
struct nvme_dev *dev = pci_get_drvdata(pdev);
|
||||
nvme_reset_ctrl(&dev->ctrl);
|
||||
nvme_reset_ctrl_sync(&dev->ctrl);
|
||||
}
|
||||
|
||||
static void nvme_shutdown(struct pci_dev *pdev)
|
||||
|
|
|
|||
|
|
@ -2029,7 +2029,7 @@ static void nvme_rdma_remove_one(struct ib_device *ib_device, void *client_data)
|
|||
}
|
||||
mutex_unlock(&nvme_rdma_ctrl_mutex);
|
||||
|
||||
flush_workqueue(nvme_wq);
|
||||
flush_workqueue(nvme_delete_wq);
|
||||
}
|
||||
|
||||
static struct ib_client nvme_rdma_ib_client = {
|
||||
|
|
|
|||
|
|
@ -512,6 +512,7 @@ bool nvmet_req_init(struct nvmet_req *req, struct nvmet_cq *cq,
|
|||
req->sg_cnt = 0;
|
||||
req->transfer_len = 0;
|
||||
req->rsp->status = 0;
|
||||
req->ns = NULL;
|
||||
|
||||
/* no support for fused commands yet */
|
||||
if (unlikely(flags & (NVME_CMD_FUSE_FIRST | NVME_CMD_FUSE_SECOND))) {
|
||||
|
|
@ -557,6 +558,8 @@ EXPORT_SYMBOL_GPL(nvmet_req_init);
|
|||
void nvmet_req_uninit(struct nvmet_req *req)
|
||||
{
|
||||
percpu_ref_put(&req->sq->ref);
|
||||
if (req->ns)
|
||||
nvmet_put_namespace(req->ns);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(nvmet_req_uninit);
|
||||
|
||||
|
|
|
|||
|
|
@ -717,7 +717,7 @@ static void __exit nvme_loop_cleanup_module(void)
|
|||
nvme_delete_ctrl(&ctrl->ctrl);
|
||||
mutex_unlock(&nvme_loop_ctrl_mutex);
|
||||
|
||||
flush_workqueue(nvme_wq);
|
||||
flush_workqueue(nvme_delete_wq);
|
||||
}
|
||||
|
||||
module_init(nvme_loop_init_module);
|
||||
|
|
|
|||
|
|
@ -124,14 +124,20 @@ enum {
|
|||
|
||||
#define NVME_CMB_BIR(cmbloc) ((cmbloc) & 0x7)
|
||||
#define NVME_CMB_OFST(cmbloc) (((cmbloc) >> 12) & 0xfffff)
|
||||
#define NVME_CMB_SZ(cmbsz) (((cmbsz) >> 12) & 0xfffff)
|
||||
#define NVME_CMB_SZU(cmbsz) (((cmbsz) >> 8) & 0xf)
|
||||
|
||||
#define NVME_CMB_WDS(cmbsz) ((cmbsz) & 0x10)
|
||||
#define NVME_CMB_RDS(cmbsz) ((cmbsz) & 0x8)
|
||||
#define NVME_CMB_LISTS(cmbsz) ((cmbsz) & 0x4)
|
||||
#define NVME_CMB_CQS(cmbsz) ((cmbsz) & 0x2)
|
||||
#define NVME_CMB_SQS(cmbsz) ((cmbsz) & 0x1)
|
||||
enum {
|
||||
NVME_CMBSZ_SQS = 1 << 0,
|
||||
NVME_CMBSZ_CQS = 1 << 1,
|
||||
NVME_CMBSZ_LISTS = 1 << 2,
|
||||
NVME_CMBSZ_RDS = 1 << 3,
|
||||
NVME_CMBSZ_WDS = 1 << 4,
|
||||
|
||||
NVME_CMBSZ_SZ_SHIFT = 12,
|
||||
NVME_CMBSZ_SZ_MASK = 0xfffff,
|
||||
|
||||
NVME_CMBSZ_SZU_SHIFT = 8,
|
||||
NVME_CMBSZ_SZU_MASK = 0xf,
|
||||
};
|
||||
|
||||
/*
|
||||
* Submission and Completion Queue Entry Sizes for the NVM command set.
|
||||
|
|
|
|||
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