clk: pxa: add pxa3xx clock driver
Move pxa25x clock drivers from arch/arm/mach-pxa to driver/clk. In the move : - convert to new clock framework legacy clocks - provide clocks as before for platform data based boards - provide clocks through devicetree with clk-pxa-dt Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr> Signed-off-by: Michael Turquette <mturquette@linaro.org>
This commit is contained in:
Robert Jarzmik
Michael Turquette
Родитель
3dccfecdb8
Коммит
9bbb8a338f
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@ -1,3 +1,4 @@
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obj-y += clk-pxa.o
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obj-$(CONFIG_PXA25x) += clk-pxa25x.o
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obj-$(CONFIG_PXA27x) += clk-pxa27x.o
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obj-$(CONFIG_PXA3xx) += clk-pxa3xx.o
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@ -0,0 +1,364 @@
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/*
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* Marvell PXA3xxx family clocks
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*
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* Copyright (C) 2014 Robert Jarzmik
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*
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* Heavily inspired from former arch/arm/mach-pxa/pxa3xx.c
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* For non-devicetree platforms. Once pxa is fully converted to devicetree, this
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* should go away.
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*/
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#include <linux/io.h>
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include <linux/clkdev.h>
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#include <linux/of.h>
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#include <mach/smemc.h>
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#include <mach/pxa3xx-regs.h>
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#include <dt-bindings/clock/pxa-clock.h>
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#include "clk-pxa.h"
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#define KHz 1000
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#define MHz (1000 * 1000)
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enum {
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PXA_CORE_60Mhz = 0,
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PXA_CORE_RUN,
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PXA_CORE_TURBO,
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};
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enum {
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PXA_BUS_60Mhz = 0,
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PXA_BUS_HSS,
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};
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/* crystal frequency to HSIO bus frequency multiplier (HSS) */
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static unsigned char hss_mult[4] = { 8, 12, 16, 24 };
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/* crystal frequency to static memory controller multiplier (SMCFS) */
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static unsigned int smcfs_mult[8] = { 6, 0, 8, 0, 0, 16, };
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static unsigned int df_clkdiv[4] = { 1, 2, 4, 1 };
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static const char * const get_freq_khz[] = {
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"core", "ring_osc_60mhz", "run", "cpll", "system_bus"
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};
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/*
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* Get the clock frequency as reflected by ACSR and the turbo flag.
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* We assume these values have been applied via a fcs.
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* If info is not 0 we also display the current settings.
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*/
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unsigned int pxa3xx_get_clk_frequency_khz(int info)
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{
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struct clk *clk;
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unsigned long clks[5];
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int i;
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for (i = 0; i < 5; i++) {
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clk = clk_get(NULL, get_freq_khz[i]);
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if (IS_ERR(clk)) {
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clks[i] = 0;
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} else {
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clks[i] = clk_get_rate(clk);
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clk_put(clk);
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}
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}
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if (info) {
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pr_info("RO Mode clock: %ld.%02ldMHz\n",
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clks[1] / 1000000, (clks[0] % 1000000) / 10000);
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pr_info("Run Mode clock: %ld.%02ldMHz\n",
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clks[2] / 1000000, (clks[1] % 1000000) / 10000);
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pr_info("Turbo Mode clock: %ld.%02ldMHz\n",
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clks[3] / 1000000, (clks[2] % 1000000) / 10000);
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pr_info("System bus clock: %ld.%02ldMHz\n",
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clks[4] / 1000000, (clks[4] % 1000000) / 10000);
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}
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return (unsigned int)clks[0];
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}
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static unsigned long clk_pxa3xx_ac97_get_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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unsigned long ac97_div, rate;
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ac97_div = AC97_DIV;
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/* This may loose precision for some rates but won't for the
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* standard 24.576MHz.
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*/
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rate = parent_rate / 2;
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rate /= ((ac97_div >> 12) & 0x7fff);
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rate *= (ac97_div & 0xfff);
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return rate;
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}
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PARENTS(clk_pxa3xx_ac97) = { "spll_624mhz" };
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RATE_RO_OPS(clk_pxa3xx_ac97, "ac97");
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static unsigned long clk_pxa3xx_smemc_get_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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unsigned long acsr = ACSR;
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unsigned long memclkcfg = __raw_readl(MEMCLKCFG);
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return (parent_rate / 48) * smcfs_mult[(acsr >> 23) & 0x7] /
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df_clkdiv[(memclkcfg >> 16) & 0x3];
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}
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PARENTS(clk_pxa3xx_smemc) = { "spll_624mhz" };
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RATE_RO_OPS(clk_pxa3xx_smemc, "smemc");
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static bool pxa3xx_is_ring_osc_forced(void)
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{
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unsigned long acsr = ACSR;
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return acsr & ACCR_D0CS;
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}
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PARENTS(pxa3xx_pbus) = { "ring_osc_60mhz", "spll_624mhz" };
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PARENTS(pxa3xx_32Khz_bus) = { "osc_32_768khz", "osc_32_768khz" };
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PARENTS(pxa3xx_13MHz_bus) = { "osc_13mhz", "osc_13mhz" };
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PARENTS(pxa3xx_ac97_bus) = { "ring_osc_60mhz", "ac97" };
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PARENTS(pxa3xx_sbus) = { "ring_osc_60mhz", "system_bus" };
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PARENTS(pxa3xx_smemcbus) = { "ring_osc_60mhz", "smemc" };
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#define CKEN_AB(bit) ((CKEN_ ## bit > 31) ? &CKENA : &CKENB)
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#define PXA3XX_CKEN(dev_id, con_id, parents, mult_lp, div_lp, mult_hp, \
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div_hp, bit, is_lp, flags) \
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PXA_CKEN(dev_id, con_id, bit, parents, mult_lp, div_lp, \
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mult_hp, div_hp, is_lp, CKEN_AB(bit), \
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(CKEN_ ## bit % 32), flags)
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#define PXA3XX_PBUS_CKEN(dev_id, con_id, bit, mult_lp, div_lp, \
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mult_hp, div_hp, delay) \
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PXA3XX_CKEN(dev_id, con_id, pxa3xx_pbus_parents, mult_lp, \
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div_lp, mult_hp, div_hp, bit, pxa3xx_is_ring_osc_forced, 0)
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#define PXA3XX_CKEN_1RATE(dev_id, con_id, bit, parents) \
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PXA_CKEN_1RATE(dev_id, con_id, bit, parents, \
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CKEN_AB(bit), (CKEN_ ## bit % 32), 0)
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static struct desc_clk_cken pxa3xx_clocks[] __initdata = {
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PXA3XX_PBUS_CKEN("pxa2xx-uart.0", NULL, FFUART, 1, 4, 1, 42, 1),
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PXA3XX_PBUS_CKEN("pxa2xx-uart.1", NULL, BTUART, 1, 4, 1, 42, 1),
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PXA3XX_PBUS_CKEN("pxa2xx-uart.2", NULL, STUART, 1, 4, 1, 42, 1),
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PXA3XX_PBUS_CKEN("pxa2xx-i2c.0", NULL, I2C, 2, 5, 1, 19, 0),
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PXA3XX_PBUS_CKEN("pxa27x-udc", NULL, UDC, 1, 4, 1, 13, 5),
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PXA3XX_PBUS_CKEN("pxa27x-ohci", NULL, USBH, 1, 4, 1, 13, 0),
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PXA3XX_PBUS_CKEN("pxa3xx-u2d", NULL, USB2, 1, 4, 1, 13, 0),
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PXA3XX_PBUS_CKEN("pxa27x-pwm.0", NULL, PWM0, 1, 6, 1, 48, 0),
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PXA3XX_PBUS_CKEN("pxa27x-pwm.1", NULL, PWM1, 1, 6, 1, 48, 0),
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PXA3XX_PBUS_CKEN("pxa2xx-mci.0", NULL, MMC1, 1, 4, 1, 24, 0),
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PXA3XX_PBUS_CKEN("pxa2xx-mci.1", NULL, MMC2, 1, 4, 1, 24, 0),
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PXA3XX_PBUS_CKEN("pxa2xx-mci.2", NULL, MMC3, 1, 4, 1, 24, 0),
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PXA3XX_CKEN_1RATE("pxa27x-keypad", NULL, KEYPAD,
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pxa3xx_32Khz_bus_parents),
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PXA3XX_CKEN_1RATE("pxa3xx-ssp.0", NULL, SSP1, pxa3xx_13MHz_bus_parents),
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PXA3XX_CKEN_1RATE("pxa3xx-ssp.1", NULL, SSP2, pxa3xx_13MHz_bus_parents),
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PXA3XX_CKEN_1RATE("pxa3xx-ssp.2", NULL, SSP3, pxa3xx_13MHz_bus_parents),
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PXA3XX_CKEN_1RATE("pxa3xx-ssp.3", NULL, SSP4, pxa3xx_13MHz_bus_parents),
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PXA3XX_CKEN(NULL, "AC97CLK", pxa3xx_ac97_bus_parents, 1, 4, 1, 1, AC97,
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pxa3xx_is_ring_osc_forced, 0),
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PXA3XX_CKEN(NULL, "CAMCLK", pxa3xx_sbus_parents, 1, 2, 1, 1, CAMERA,
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pxa3xx_is_ring_osc_forced, 0),
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PXA3XX_CKEN("pxa2xx-fb", NULL, pxa3xx_sbus_parents, 1, 1, 1, 1, LCD,
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pxa3xx_is_ring_osc_forced, 0),
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PXA3XX_CKEN("pxa2xx-pcmcia", NULL, pxa3xx_smemcbus_parents, 1, 4,
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1, 1, SMC, pxa3xx_is_ring_osc_forced, CLK_IGNORE_UNUSED),
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};
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static struct desc_clk_cken pxa300_310_clocks[] __initdata = {
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PXA3XX_PBUS_CKEN("pxa3xx-gcu", NULL, PXA300_GCU, 1, 1, 1, 1, 0),
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PXA3XX_PBUS_CKEN("pxa3xx-nand", NULL, NAND, 1, 2, 1, 4, 0),
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PXA3XX_CKEN_1RATE("pxa3xx-gpio", NULL, GPIO, pxa3xx_13MHz_bus_parents),
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};
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static struct desc_clk_cken pxa320_clocks[] __initdata = {
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PXA3XX_PBUS_CKEN("pxa3xx-nand", NULL, NAND, 1, 2, 1, 6, 0),
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PXA3XX_PBUS_CKEN("pxa3xx-gcu", NULL, PXA320_GCU, 1, 1, 1, 1, 0),
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PXA3XX_CKEN_1RATE("pxa3xx-gpio", NULL, GPIO, pxa3xx_13MHz_bus_parents),
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};
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static struct desc_clk_cken pxa93x_clocks[] __initdata = {
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PXA3XX_PBUS_CKEN("pxa3xx-gcu", NULL, PXA300_GCU, 1, 1, 1, 1, 0),
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PXA3XX_PBUS_CKEN("pxa3xx-nand", NULL, NAND, 1, 2, 1, 4, 0),
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PXA3XX_CKEN_1RATE("pxa93x-gpio", NULL, GPIO, pxa3xx_13MHz_bus_parents),
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};
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static unsigned long clk_pxa3xx_system_bus_get_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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unsigned long acsr = ACSR;
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unsigned int hss = (acsr >> 14) & 0x3;
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if (pxa3xx_is_ring_osc_forced())
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return parent_rate;
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return parent_rate / 48 * hss_mult[hss];
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}
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static u8 clk_pxa3xx_system_bus_get_parent(struct clk_hw *hw)
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{
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if (pxa3xx_is_ring_osc_forced())
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return PXA_BUS_60Mhz;
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else
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return PXA_BUS_HSS;
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}
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PARENTS(clk_pxa3xx_system_bus) = { "ring_osc_60mhz", "spll_624mhz" };
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MUX_RO_RATE_RO_OPS(clk_pxa3xx_system_bus, "system_bus");
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static unsigned long clk_pxa3xx_core_get_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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return parent_rate;
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}
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static u8 clk_pxa3xx_core_get_parent(struct clk_hw *hw)
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{
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unsigned long xclkcfg;
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unsigned int t;
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if (pxa3xx_is_ring_osc_forced())
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return PXA_CORE_60Mhz;
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/* Read XCLKCFG register turbo bit */
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__asm__ __volatile__("mrc\tp14, 0, %0, c6, c0, 0" : "=r"(xclkcfg));
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t = xclkcfg & 0x1;
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if (t)
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return PXA_CORE_TURBO;
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return PXA_CORE_RUN;
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}
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PARENTS(clk_pxa3xx_core) = { "ring_osc_60mhz", "run", "cpll" };
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MUX_RO_RATE_RO_OPS(clk_pxa3xx_core, "core");
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static unsigned long clk_pxa3xx_run_get_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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unsigned long acsr = ACSR;
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unsigned int xn = (acsr & ACCR_XN_MASK) >> 8;
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unsigned int t, xclkcfg;
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/* Read XCLKCFG register turbo bit */
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__asm__ __volatile__("mrc\tp14, 0, %0, c6, c0, 0" : "=r"(xclkcfg));
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t = xclkcfg & 0x1;
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return t ? (parent_rate / xn) * 2 : parent_rate;
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}
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PARENTS(clk_pxa3xx_run) = { "cpll" };
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RATE_RO_OPS(clk_pxa3xx_run, "run");
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static unsigned long clk_pxa3xx_cpll_get_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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unsigned long acsr = ACSR;
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unsigned int xn = (acsr & ACCR_XN_MASK) >> 8;
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unsigned int xl = acsr & ACCR_XL_MASK;
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unsigned int t, xclkcfg;
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/* Read XCLKCFG register turbo bit */
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__asm__ __volatile__("mrc\tp14, 0, %0, c6, c0, 0" : "=r"(xclkcfg));
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t = xclkcfg & 0x1;
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pr_info("RJK: parent_rate=%lu, xl=%u, xn=%u\n", parent_rate, xl, xn);
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return t ? parent_rate * xl * xn : parent_rate * xl;
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}
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PARENTS(clk_pxa3xx_cpll) = { "osc_13mhz" };
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RATE_RO_OPS(clk_pxa3xx_cpll, "cpll");
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static void __init pxa3xx_register_core(void)
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{
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clk_register_clk_pxa3xx_cpll();
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clk_register_clk_pxa3xx_run();
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clkdev_pxa_register(CLK_CORE, "core", NULL,
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clk_register_clk_pxa3xx_core());
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}
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static void __init pxa3xx_register_plls(void)
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{
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clk_register_fixed_rate(NULL, "osc_13mhz", NULL,
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CLK_GET_RATE_NOCACHE | CLK_IS_ROOT,
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13 * MHz);
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clk_register_fixed_rate(NULL, "osc_32_768khz", NULL,
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CLK_GET_RATE_NOCACHE | CLK_IS_ROOT,
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32768);
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clk_register_fixed_rate(NULL, "ring_osc_120mhz", NULL,
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CLK_GET_RATE_NOCACHE | CLK_IS_ROOT,
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120 * MHz);
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clk_register_fixed_rate(NULL, "clk_dummy", NULL, CLK_IS_ROOT, 0);
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clk_register_fixed_factor(NULL, "spll_624mhz", "osc_13mhz", 0, 48, 1);
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clk_register_fixed_factor(NULL, "ring_osc_60mhz", "ring_osc_120mhz",
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0, 1, 2);
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}
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#define DUMMY_CLK(_con_id, _dev_id, _parent) \
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{ .con_id = _con_id, .dev_id = _dev_id, .parent = _parent }
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struct dummy_clk {
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const char *con_id;
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const char *dev_id;
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const char *parent;
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};
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static struct dummy_clk dummy_clks[] __initdata = {
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DUMMY_CLK(NULL, "pxa93x-gpio", "osc_13mhz"),
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DUMMY_CLK(NULL, "sa1100-rtc", "osc_32_768khz"),
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DUMMY_CLK("UARTCLK", "pxa2xx-ir", "STUART"),
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DUMMY_CLK(NULL, "pxa3xx-pwri2c.1", "osc_13mhz"),
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};
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static void __init pxa3xx_dummy_clocks_init(void)
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{
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struct clk *clk;
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struct dummy_clk *d;
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const char *name;
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int i;
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for (i = 0; i < ARRAY_SIZE(dummy_clks); i++) {
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d = &dummy_clks[i];
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name = d->dev_id ? d->dev_id : d->con_id;
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clk = clk_register_fixed_factor(NULL, name, d->parent, 0, 1, 1);
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clk_register_clkdev(clk, d->con_id, d->dev_id);
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}
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}
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static void __init pxa3xx_base_clocks_init(void)
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{
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pxa3xx_register_plls();
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pxa3xx_register_core();
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clk_register_clk_pxa3xx_system_bus();
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clk_register_clk_pxa3xx_ac97();
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clk_register_clk_pxa3xx_smemc();
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clk_register_gate(NULL, "CLK_POUT", "osc_13mhz", 0,
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(void __iomem *)&OSCC, 11, 0, NULL);
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}
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int __init pxa3xx_clocks_init(void)
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{
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int ret;
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pxa3xx_base_clocks_init();
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pxa3xx_dummy_clocks_init();
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ret = clk_pxa_cken_init(pxa3xx_clocks, ARRAY_SIZE(pxa3xx_clocks));
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if (ret)
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return ret;
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if (cpu_is_pxa320())
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return clk_pxa_cken_init(pxa320_clocks,
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ARRAY_SIZE(pxa320_clocks));
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if (cpu_is_pxa300() || cpu_is_pxa310())
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return clk_pxa_cken_init(pxa300_310_clocks,
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ARRAY_SIZE(pxa300_310_clocks));
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return clk_pxa_cken_init(pxa93x_clocks, ARRAY_SIZE(pxa93x_clocks));
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}
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static void __init pxa3xx_dt_clocks_init(struct device_node *np)
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{
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pxa3xx_clocks_init();
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clk_pxa_dt_common_init(np);
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}
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CLK_OF_DECLARE(pxa_clks, "marvell,pxa300-clocks", pxa3xx_dt_clocks_init);
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