ARM: dts: stm32: add Timers driver for stm32f746 MCU
Add Timers and it sub-nodes into DT for stm32f746 family. Signed-off-by: Benjamin Gaignard <benjamin.gaignard@st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
This commit is contained in:
Benjamin Gaignard
Alexandre Torgue
Родитель
e40992cb22
Коммит
9bd7b77af8
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@ -82,6 +82,27 @@
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status = "disabled";
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};
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timers2: timers@40000000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "st,stm32-timers";
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reg = <0x40000000 0x400>;
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clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM2)>;
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clock-names = "int";
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status = "disabled";
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pwm {
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compatible = "st,stm32-pwm";
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status = "disabled";
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};
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timer@1 {
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compatible = "st,stm32-timer-trigger";
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reg = <1>;
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status = "disabled";
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};
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};
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timer3: timer@40000400 {
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compatible = "st,stm32-timer";
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reg = <0x40000400 0x400>;
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@ -90,6 +111,27 @@
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status = "disabled";
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};
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timers3: timers@40000400 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "st,stm32-timers";
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reg = <0x40000400 0x400>;
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clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM3)>;
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clock-names = "int";
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status = "disabled";
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pwm {
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compatible = "st,stm32-pwm";
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status = "disabled";
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};
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timer@2 {
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compatible = "st,stm32-timer-trigger";
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reg = <2>;
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status = "disabled";
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};
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};
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timer4: timer@40000800 {
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compatible = "st,stm32-timer";
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reg = <0x40000800 0x400>;
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@ -98,6 +140,27 @@
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status = "disabled";
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};
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timers4: timers@40000800 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "st,stm32-timers";
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reg = <0x40000800 0x400>;
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clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM4)>;
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clock-names = "int";
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status = "disabled";
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pwm {
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compatible = "st,stm32-pwm";
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status = "disabled";
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};
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timer@3 {
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compatible = "st,stm32-timer-trigger";
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reg = <3>;
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status = "disabled";
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};
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};
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timer5: timer@40000c00 {
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compatible = "st,stm32-timer";
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reg = <0x40000c00 0x400>;
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@ -105,6 +168,27 @@
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clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM5)>;
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};
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timers5: timers@40000c00 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "st,stm32-timers";
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reg = <0x40000C00 0x400>;
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clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM5)>;
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clock-names = "int";
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status = "disabled";
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pwm {
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compatible = "st,stm32-pwm";
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status = "disabled";
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};
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timer@4 {
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compatible = "st,stm32-timer-trigger";
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reg = <4>;
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status = "disabled";
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};
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};
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timer6: timer@40001000 {
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compatible = "st,stm32-timer";
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reg = <0x40001000 0x400>;
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@ -113,6 +197,22 @@
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status = "disabled";
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};
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timers6: timers@40001000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "st,stm32-timers";
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reg = <0x40001000 0x400>;
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clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM6)>;
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clock-names = "int";
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status = "disabled";
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timer@5 {
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compatible = "st,stm32-timer-trigger";
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reg = <5>;
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status = "disabled";
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};
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};
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timer7: timer@40001400 {
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compatible = "st,stm32-timer";
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reg = <0x40001400 0x400>;
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@ -121,6 +221,73 @@
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status = "disabled";
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};
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timers7: timers@40001400 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "st,stm32-timers";
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reg = <0x40001400 0x400>;
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clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM7)>;
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clock-names = "int";
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status = "disabled";
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timer@6 {
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compatible = "st,stm32-timer-trigger";
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reg = <6>;
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status = "disabled";
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};
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};
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timers12: timers@40001800 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "st,stm32-timers";
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reg = <0x40001800 0x400>;
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clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM12)>;
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clock-names = "int";
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status = "disabled";
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pwm {
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compatible = "st,stm32-pwm";
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status = "disabled";
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};
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timer@11 {
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compatible = "st,stm32-timer-trigger";
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reg = <11>;
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status = "disabled";
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};
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};
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timers13: timers@40001c00 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "st,stm32-timers";
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reg = <0x40001C00 0x400>;
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clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM13)>;
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clock-names = "int";
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status = "disabled";
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pwm {
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compatible = "st,stm32-pwm";
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status = "disabled";
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};
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};
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timers14: timers@40002000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "st,stm32-timers";
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reg = <0x40002000 0x400>;
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clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM14)>;
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clock-names = "int";
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status = "disabled";
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pwm {
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compatible = "st,stm32-pwm";
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status = "disabled";
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};
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};
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rtc: rtc@40002800 {
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compatible = "st,stm32-rtc";
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reg = <0x40002800 0x400>;
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@ -204,6 +371,48 @@
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status = "disabled";
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};
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timers1: timers@40010000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "st,stm32-timers";
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reg = <0x40010000 0x400>;
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clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM1)>;
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clock-names = "int";
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status = "disabled";
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pwm {
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compatible = "st,stm32-pwm";
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status = "disabled";
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};
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timer@0 {
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compatible = "st,stm32-timer-trigger";
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reg = <0>;
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status = "disabled";
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};
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};
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timers8: timers@40010400 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "st,stm32-timers";
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reg = <0x40010400 0x400>;
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clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM8)>;
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clock-names = "int";
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status = "disabled";
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pwm {
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compatible = "st,stm32-pwm";
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status = "disabled";
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};
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timer@7 {
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compatible = "st,stm32-timer-trigger";
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reg = <7>;
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status = "disabled";
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};
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};
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usart1: serial@40011000 {
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compatible = "st,stm32f7-usart", "st,stm32f7-uart";
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reg = <0x40011000 0x400>;
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@ -233,6 +442,57 @@
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interrupts = <1>, <2>, <3>, <6>, <7>, <8>, <9>, <10>, <23>, <40>, <41>, <42>, <62>, <76>;
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};
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timers9: timers@40014000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "st,stm32-timers";
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reg = <0x40014000 0x400>;
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clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM9)>;
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clock-names = "int";
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status = "disabled";
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pwm {
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compatible = "st,stm32-pwm";
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status = "disabled";
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};
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timer@8 {
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compatible = "st,stm32-timer-trigger";
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reg = <8>;
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status = "disabled";
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};
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};
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timers10: timers@40014400 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "st,stm32-timers";
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reg = <0x40014400 0x400>;
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clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM10)>;
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clock-names = "int";
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status = "disabled";
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pwm {
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compatible = "st,stm32-pwm";
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status = "disabled";
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};
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};
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timers11: timers@40014800 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "st,stm32-timers";
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reg = <0x40014800 0x400>;
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clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM11)>;
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clock-names = "int";
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status = "disabled";
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pwm {
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compatible = "st,stm32-pwm";
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status = "disabled";
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};
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};
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pwrcfg: power-config@40007000 {
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compatible = "syscon";
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reg = <0x40007000 0x400>;
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