ARM/cns3xxx/timer: Migrate to new 'set-state' interface
Migrate cns3xxx driver to the new 'set-state' interface provided by clockevents core, the earlier 'set-mode' interface is marked obsolete now. This also enables us to implement callbacks for new states of clockevent devices, for example: ONESHOT_STOPPED. NOTE: We don't read TIMER1_2_CONTROL_OFFSET register on shutdown anymore. Acked-by: Krzysztof Hałasa <khalasa@piap.pl> Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
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5e2535710e
Коммит
9bdc2e0c9a
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@ -113,30 +113,33 @@ void cns3xxx_power_off(void)
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*/
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*/
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static void __iomem *cns3xxx_tmr1;
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static void __iomem *cns3xxx_tmr1;
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static void cns3xxx_timer_set_mode(enum clock_event_mode mode,
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static int cns3xxx_shutdown(struct clock_event_device *clk)
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struct clock_event_device *clk)
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{
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writel(0, cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET);
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return 0;
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}
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static int cns3xxx_set_oneshot(struct clock_event_device *clk)
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{
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unsigned long ctrl = readl(cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET);
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/* period set, and timer enabled in 'next_event' hook */
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ctrl |= (1 << 2) | (1 << 9);
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writel(ctrl, cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET);
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return 0;
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}
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static int cns3xxx_set_periodic(struct clock_event_device *clk)
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{
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{
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unsigned long ctrl = readl(cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET);
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unsigned long ctrl = readl(cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET);
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int pclk = cns3xxx_cpu_clock() / 8;
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int pclk = cns3xxx_cpu_clock() / 8;
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int reload;
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int reload;
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switch (mode) {
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reload = pclk * 20 / (3 * HZ) * 0x25000;
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case CLOCK_EVT_MODE_PERIODIC:
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writel(reload, cns3xxx_tmr1 + TIMER1_AUTO_RELOAD_OFFSET);
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reload = pclk * 20 / (3 * HZ) * 0x25000;
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ctrl |= (1 << 0) | (1 << 2) | (1 << 9);
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writel(reload, cns3xxx_tmr1 + TIMER1_AUTO_RELOAD_OFFSET);
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ctrl |= (1 << 0) | (1 << 2) | (1 << 9);
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break;
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case CLOCK_EVT_MODE_ONESHOT:
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/* period set, and timer enabled in 'next_event' hook */
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ctrl |= (1 << 2) | (1 << 9);
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break;
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case CLOCK_EVT_MODE_UNUSED:
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case CLOCK_EVT_MODE_SHUTDOWN:
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default:
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ctrl = 0;
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}
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writel(ctrl, cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET);
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writel(ctrl, cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET);
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return 0;
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}
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}
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static int cns3xxx_timer_set_next_event(unsigned long evt,
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static int cns3xxx_timer_set_next_event(unsigned long evt,
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@ -151,12 +154,16 @@ static int cns3xxx_timer_set_next_event(unsigned long evt,
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}
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}
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static struct clock_event_device cns3xxx_tmr1_clockevent = {
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static struct clock_event_device cns3xxx_tmr1_clockevent = {
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.name = "cns3xxx timer1",
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.name = "cns3xxx timer1",
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.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
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.features = CLOCK_EVT_FEAT_PERIODIC |
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.set_mode = cns3xxx_timer_set_mode,
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CLOCK_EVT_FEAT_ONESHOT,
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.set_next_event = cns3xxx_timer_set_next_event,
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.set_state_shutdown = cns3xxx_shutdown,
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.rating = 350,
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.set_state_periodic = cns3xxx_set_periodic,
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.cpumask = cpu_all_mask,
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.set_state_oneshot = cns3xxx_set_oneshot,
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.tick_resume = cns3xxx_shutdown,
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.set_next_event = cns3xxx_timer_set_next_event,
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.rating = 350,
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.cpumask = cpu_all_mask,
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};
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};
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static void __init cns3xxx_clockevents_init(unsigned int timer_irq)
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static void __init cns3xxx_clockevents_init(unsigned int timer_irq)
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