Merge branch 'drm-intel-fixes' of git://people.freedesktop.org/~danvet/drm-intel into drm-fixes
Daniel Vetter writes" Nothing big at all for -fixes, just small stuff: - Two patches to fix bugs on i830M - ums regression fixer due to kicking firmeware fbs (Chris) - tune down a too loud warning (Jani) - be more careful with sdvo infoframes, which fixes a long-standing sdvo-hdmi regression" * 'drm-intel-fixes' of git://people.freedesktop.org/~danvet/drm-intel: drm/i915: Only kick out vesafb if we takeover the fbcon with KMS drm/i915: be less verbose about inability to provide vendor backlight drm/i915: clear the entire sdvo infoframe buffer drm/i915: VGA needs to be on pipe A on i830M drm/i915: fix overlay on i830M
This commit is contained in:
Коммит
9c275407a3
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@ -1505,7 +1505,8 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
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goto put_gmch;
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goto put_gmch;
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}
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}
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i915_kick_out_firmware_fb(dev_priv);
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if (drm_core_check_feature(dev, DRIVER_MODESET))
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i915_kick_out_firmware_fb(dev_priv);
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pci_set_master(dev->pdev);
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pci_set_master(dev->pdev);
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@ -729,7 +729,7 @@ void intel_crt_init(struct drm_device *dev)
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crt->base.type = INTEL_OUTPUT_ANALOG;
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crt->base.type = INTEL_OUTPUT_ANALOG;
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crt->base.cloneable = true;
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crt->base.cloneable = true;
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if (IS_HASWELL(dev))
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if (IS_HASWELL(dev) || IS_I830(dev))
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crt->base.crtc_mask = (1 << 0);
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crt->base.crtc_mask = (1 << 0);
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else
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else
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crt->base.crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
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crt->base.crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
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@ -341,9 +341,17 @@ static int intel_overlay_off(struct intel_overlay *overlay)
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intel_ring_emit(ring, flip_addr);
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intel_ring_emit(ring, flip_addr);
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intel_ring_emit(ring, MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
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intel_ring_emit(ring, MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
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/* turn overlay off */
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/* turn overlay off */
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intel_ring_emit(ring, MI_OVERLAY_FLIP | MI_OVERLAY_OFF);
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if (IS_I830(dev)) {
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intel_ring_emit(ring, flip_addr);
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/* Workaround: Don't disable the overlay fully, since otherwise
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intel_ring_emit(ring, MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
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* it dies on the next OVERLAY_ON cmd. */
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intel_ring_emit(ring, MI_NOOP);
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intel_ring_emit(ring, MI_NOOP);
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intel_ring_emit(ring, MI_NOOP);
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} else {
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intel_ring_emit(ring, MI_OVERLAY_FLIP | MI_OVERLAY_OFF);
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intel_ring_emit(ring, flip_addr);
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intel_ring_emit(ring, MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
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}
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intel_ring_advance(ring);
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intel_ring_advance(ring);
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return intel_overlay_do_wait_request(overlay, intel_overlay_off_tail);
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return intel_overlay_do_wait_request(overlay, intel_overlay_off_tail);
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@ -435,7 +435,7 @@ int intel_panel_setup_backlight(struct drm_device *dev)
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props.type = BACKLIGHT_RAW;
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props.type = BACKLIGHT_RAW;
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props.max_brightness = _intel_panel_get_max_backlight(dev);
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props.max_brightness = _intel_panel_get_max_backlight(dev);
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if (props.max_brightness == 0) {
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if (props.max_brightness == 0) {
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DRM_ERROR("Failed to get maximum backlight value\n");
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DRM_DEBUG_DRIVER("Failed to get maximum backlight value\n");
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return -ENODEV;
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return -ENODEV;
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}
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}
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dev_priv->backlight =
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dev_priv->backlight =
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@ -894,6 +894,45 @@ static void intel_sdvo_dump_hdmi_buf(struct intel_sdvo *intel_sdvo)
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}
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}
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#endif
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#endif
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static bool intel_sdvo_write_infoframe(struct intel_sdvo *intel_sdvo,
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unsigned if_index, uint8_t tx_rate,
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uint8_t *data, unsigned length)
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{
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uint8_t set_buf_index[2] = { if_index, 0 };
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uint8_t hbuf_size, tmp[8];
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int i;
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if (!intel_sdvo_set_value(intel_sdvo,
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SDVO_CMD_SET_HBUF_INDEX,
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set_buf_index, 2))
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return false;
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if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_HBUF_INFO,
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&hbuf_size, 1))
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return false;
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/* Buffer size is 0 based, hooray! */
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hbuf_size++;
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DRM_DEBUG_KMS("writing sdvo hbuf: %i, hbuf_size %i, hbuf_size: %i\n",
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if_index, length, hbuf_size);
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for (i = 0; i < hbuf_size; i += 8) {
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memset(tmp, 0, 8);
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if (i < length)
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memcpy(tmp, data + i, min_t(unsigned, 8, length - i));
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if (!intel_sdvo_set_value(intel_sdvo,
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SDVO_CMD_SET_HBUF_DATA,
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tmp, 8))
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return false;
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}
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return intel_sdvo_set_value(intel_sdvo,
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SDVO_CMD_SET_HBUF_TXRATE,
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&tx_rate, 1);
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}
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static bool intel_sdvo_set_avi_infoframe(struct intel_sdvo *intel_sdvo)
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static bool intel_sdvo_set_avi_infoframe(struct intel_sdvo *intel_sdvo)
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{
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{
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struct dip_infoframe avi_if = {
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struct dip_infoframe avi_if = {
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@ -901,11 +940,7 @@ static bool intel_sdvo_set_avi_infoframe(struct intel_sdvo *intel_sdvo)
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.ver = DIP_VERSION_AVI,
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.ver = DIP_VERSION_AVI,
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.len = DIP_LEN_AVI,
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.len = DIP_LEN_AVI,
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};
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};
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uint8_t tx_rate = SDVO_HBUF_TX_VSYNC;
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uint8_t set_buf_index[2] = { 1, 0 };
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uint8_t sdvo_data[4 + sizeof(avi_if.body.avi)];
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uint8_t sdvo_data[4 + sizeof(avi_if.body.avi)];
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uint64_t *data = (uint64_t *)sdvo_data;
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unsigned i;
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intel_dip_infoframe_csum(&avi_if);
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intel_dip_infoframe_csum(&avi_if);
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@ -915,22 +950,9 @@ static bool intel_sdvo_set_avi_infoframe(struct intel_sdvo *intel_sdvo)
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sdvo_data[3] = avi_if.checksum;
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sdvo_data[3] = avi_if.checksum;
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memcpy(&sdvo_data[4], &avi_if.body, sizeof(avi_if.body.avi));
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memcpy(&sdvo_data[4], &avi_if.body, sizeof(avi_if.body.avi));
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if (!intel_sdvo_set_value(intel_sdvo,
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return intel_sdvo_write_infoframe(intel_sdvo, SDVO_HBUF_INDEX_AVI_IF,
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SDVO_CMD_SET_HBUF_INDEX,
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SDVO_HBUF_TX_VSYNC,
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set_buf_index, 2))
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sdvo_data, sizeof(sdvo_data));
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return false;
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for (i = 0; i < sizeof(sdvo_data); i += 8) {
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if (!intel_sdvo_set_value(intel_sdvo,
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SDVO_CMD_SET_HBUF_DATA,
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data, 8))
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return false;
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data++;
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}
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return intel_sdvo_set_value(intel_sdvo,
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SDVO_CMD_SET_HBUF_TXRATE,
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&tx_rate, 1);
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}
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}
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static bool intel_sdvo_set_tv_format(struct intel_sdvo *intel_sdvo)
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static bool intel_sdvo_set_tv_format(struct intel_sdvo *intel_sdvo)
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@ -708,6 +708,8 @@ struct intel_sdvo_enhancements_arg {
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#define SDVO_CMD_SET_AUDIO_STAT 0x91
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#define SDVO_CMD_SET_AUDIO_STAT 0x91
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#define SDVO_CMD_GET_AUDIO_STAT 0x92
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#define SDVO_CMD_GET_AUDIO_STAT 0x92
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#define SDVO_CMD_SET_HBUF_INDEX 0x93
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#define SDVO_CMD_SET_HBUF_INDEX 0x93
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#define SDVO_HBUF_INDEX_ELD 0
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#define SDVO_HBUF_INDEX_AVI_IF 1
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#define SDVO_CMD_GET_HBUF_INDEX 0x94
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#define SDVO_CMD_GET_HBUF_INDEX 0x94
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#define SDVO_CMD_GET_HBUF_INFO 0x95
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#define SDVO_CMD_GET_HBUF_INFO 0x95
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#define SDVO_CMD_SET_HBUF_AV_SPLIT 0x96
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#define SDVO_CMD_SET_HBUF_AV_SPLIT 0x96
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