ASoC: SAMSUNG: Move PCM specific definitions into pcm.c
This patch moves PCM specific definitions, they doesn't need to be shared, into 'pcm.c' from 'pcm.h'. Signed-off-by: Seungwhan Youn <sw.youn@samsung.com> Acked-by: Jassi Brar <jassi.brar@samsung.com> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
This commit is contained in:
Seungwhan Youn
Mark Brown
Родитель
f7f741810f
Коммит
9c6df19e55
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@ -32,6 +32,113 @@
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#include "dma.h"
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#include "pcm.h"
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/*Register Offsets */
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#define S3C_PCM_CTL 0x00
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#define S3C_PCM_CLKCTL 0x04
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#define S3C_PCM_TXFIFO 0x08
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#define S3C_PCM_RXFIFO 0x0C
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#define S3C_PCM_IRQCTL 0x10
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#define S3C_PCM_IRQSTAT 0x14
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#define S3C_PCM_FIFOSTAT 0x18
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#define S3C_PCM_CLRINT 0x20
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/* PCM_CTL Bit-Fields */
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#define S3C_PCM_CTL_TXDIPSTICK_MASK 0x3f
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#define S3C_PCM_CTL_TXDIPSTICK_SHIFT 13
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#define S3C_PCM_CTL_RXDIPSTICK_MASK 0x3f
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#define S3C_PCM_CTL_RXDIPSTICK_SHIFT 7
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#define S3C_PCM_CTL_TXDMA_EN (0x1 << 6)
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#define S3C_PCM_CTL_RXDMA_EN (0x1 << 5)
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#define S3C_PCM_CTL_TXMSB_AFTER_FSYNC (0x1 << 4)
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#define S3C_PCM_CTL_RXMSB_AFTER_FSYNC (0x1 << 3)
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#define S3C_PCM_CTL_TXFIFO_EN (0x1 << 2)
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#define S3C_PCM_CTL_RXFIFO_EN (0x1 << 1)
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#define S3C_PCM_CTL_ENABLE (0x1 << 0)
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/* PCM_CLKCTL Bit-Fields */
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#define S3C_PCM_CLKCTL_SERCLK_EN (0x1 << 19)
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#define S3C_PCM_CLKCTL_SERCLKSEL_PCLK (0x1 << 18)
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#define S3C_PCM_CLKCTL_SCLKDIV_MASK 0x1ff
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#define S3C_PCM_CLKCTL_SYNCDIV_MASK 0x1ff
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#define S3C_PCM_CLKCTL_SCLKDIV_SHIFT 9
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#define S3C_PCM_CLKCTL_SYNCDIV_SHIFT 0
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/* PCM_TXFIFO Bit-Fields */
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#define S3C_PCM_TXFIFO_DVALID (0x1 << 16)
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#define S3C_PCM_TXFIFO_DATA_MSK (0xffff << 0)
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/* PCM_RXFIFO Bit-Fields */
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#define S3C_PCM_RXFIFO_DVALID (0x1 << 16)
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#define S3C_PCM_RXFIFO_DATA_MSK (0xffff << 0)
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/* PCM_IRQCTL Bit-Fields */
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#define S3C_PCM_IRQCTL_IRQEN (0x1 << 14)
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#define S3C_PCM_IRQCTL_WRDEN (0x1 << 12)
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#define S3C_PCM_IRQCTL_TXEMPTYEN (0x1 << 11)
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#define S3C_PCM_IRQCTL_TXALMSTEMPTYEN (0x1 << 10)
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#define S3C_PCM_IRQCTL_TXFULLEN (0x1 << 9)
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#define S3C_PCM_IRQCTL_TXALMSTFULLEN (0x1 << 8)
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#define S3C_PCM_IRQCTL_TXSTARVEN (0x1 << 7)
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#define S3C_PCM_IRQCTL_TXERROVRFLEN (0x1 << 6)
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#define S3C_PCM_IRQCTL_RXEMPTEN (0x1 << 5)
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#define S3C_PCM_IRQCTL_RXALMSTEMPTEN (0x1 << 4)
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#define S3C_PCM_IRQCTL_RXFULLEN (0x1 << 3)
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#define S3C_PCM_IRQCTL_RXALMSTFULLEN (0x1 << 2)
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#define S3C_PCM_IRQCTL_RXSTARVEN (0x1 << 1)
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#define S3C_PCM_IRQCTL_RXERROVRFLEN (0x1 << 0)
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/* PCM_IRQSTAT Bit-Fields */
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#define S3C_PCM_IRQSTAT_IRQPND (0x1 << 13)
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#define S3C_PCM_IRQSTAT_WRD_XFER (0x1 << 12)
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#define S3C_PCM_IRQSTAT_TXEMPTY (0x1 << 11)
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#define S3C_PCM_IRQSTAT_TXALMSTEMPTY (0x1 << 10)
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#define S3C_PCM_IRQSTAT_TXFULL (0x1 << 9)
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#define S3C_PCM_IRQSTAT_TXALMSTFULL (0x1 << 8)
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#define S3C_PCM_IRQSTAT_TXSTARV (0x1 << 7)
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#define S3C_PCM_IRQSTAT_TXERROVRFL (0x1 << 6)
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#define S3C_PCM_IRQSTAT_RXEMPT (0x1 << 5)
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#define S3C_PCM_IRQSTAT_RXALMSTEMPT (0x1 << 4)
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#define S3C_PCM_IRQSTAT_RXFULL (0x1 << 3)
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#define S3C_PCM_IRQSTAT_RXALMSTFULL (0x1 << 2)
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#define S3C_PCM_IRQSTAT_RXSTARV (0x1 << 1)
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#define S3C_PCM_IRQSTAT_RXERROVRFL (0x1 << 0)
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/* PCM_FIFOSTAT Bit-Fields */
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#define S3C_PCM_FIFOSTAT_TXCNT_MSK (0x3f << 14)
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#define S3C_PCM_FIFOSTAT_TXFIFOEMPTY (0x1 << 13)
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#define S3C_PCM_FIFOSTAT_TXFIFOALMSTEMPTY (0x1 << 12)
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#define S3C_PCM_FIFOSTAT_TXFIFOFULL (0x1 << 11)
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#define S3C_PCM_FIFOSTAT_TXFIFOALMSTFULL (0x1 << 10)
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#define S3C_PCM_FIFOSTAT_RXCNT_MSK (0x3f << 4)
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#define S3C_PCM_FIFOSTAT_RXFIFOEMPTY (0x1 << 3)
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#define S3C_PCM_FIFOSTAT_RXFIFOALMSTEMPTY (0x1 << 2)
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#define S3C_PCM_FIFOSTAT_RXFIFOFULL (0x1 << 1)
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#define S3C_PCM_FIFOSTAT_RXFIFOALMSTFULL (0x1 << 0)
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/**
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* struct s3c_pcm_info - S3C PCM Controller information
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* @dev: The parent device passed to use from the probe.
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* @regs: The pointer to the device register block.
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* @dma_playback: DMA information for playback channel.
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* @dma_capture: DMA information for capture channel.
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*/
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struct s3c_pcm_info {
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spinlock_t lock;
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struct device *dev;
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void __iomem *regs;
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unsigned int sclk_per_fs;
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/* Whether to keep PCMSCLK enabled even when idle(no active xfer) */
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unsigned int idleclk;
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struct clk *pclk;
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struct clk *cclk;
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struct s3c_dma_params *dma_playback;
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struct s3c_dma_params *dma_capture;
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};
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static struct s3c2410_dma_client s3c_pcm_dma_client_out = {
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.name = "PCM Stereo out"
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};
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@ -9,116 +9,9 @@
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#ifndef __S3C_PCM_H
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#define __S3C_PCM_H __FILE__
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/*Register Offsets */
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#define S3C_PCM_CTL (0x00)
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#define S3C_PCM_CLKCTL (0x04)
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#define S3C_PCM_TXFIFO (0x08)
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#define S3C_PCM_RXFIFO (0x0C)
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#define S3C_PCM_IRQCTL (0x10)
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#define S3C_PCM_IRQSTAT (0x14)
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#define S3C_PCM_FIFOSTAT (0x18)
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#define S3C_PCM_CLRINT (0x20)
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/* PCM_CTL Bit-Fields */
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#define S3C_PCM_CTL_TXDIPSTICK_MASK (0x3f)
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#define S3C_PCM_CTL_TXDIPSTICK_SHIFT (13)
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#define S3C_PCM_CTL_RXDIPSTICK_MASK (0x3f)
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#define S3C_PCM_CTL_RXDIPSTICK_SHIFT (7)
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#define S3C_PCM_CTL_TXDMA_EN (0x1<<6)
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#define S3C_PCM_CTL_RXDMA_EN (0x1<<5)
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#define S3C_PCM_CTL_TXMSB_AFTER_FSYNC (0x1<<4)
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#define S3C_PCM_CTL_RXMSB_AFTER_FSYNC (0x1<<3)
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#define S3C_PCM_CTL_TXFIFO_EN (0x1<<2)
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#define S3C_PCM_CTL_RXFIFO_EN (0x1<<1)
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#define S3C_PCM_CTL_ENABLE (0x1<<0)
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/* PCM_CLKCTL Bit-Fields */
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#define S3C_PCM_CLKCTL_SERCLK_EN (0x1<<19)
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#define S3C_PCM_CLKCTL_SERCLKSEL_PCLK (0x1<<18)
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#define S3C_PCM_CLKCTL_SCLKDIV_MASK (0x1ff)
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#define S3C_PCM_CLKCTL_SYNCDIV_MASK (0x1ff)
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#define S3C_PCM_CLKCTL_SCLKDIV_SHIFT (9)
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#define S3C_PCM_CLKCTL_SYNCDIV_SHIFT (0)
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/* PCM_TXFIFO Bit-Fields */
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#define S3C_PCM_TXFIFO_DVALID (0x1<<16)
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#define S3C_PCM_TXFIFO_DATA_MSK (0xffff<<0)
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/* PCM_RXFIFO Bit-Fields */
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#define S3C_PCM_RXFIFO_DVALID (0x1<<16)
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#define S3C_PCM_RXFIFO_DATA_MSK (0xffff<<0)
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/* PCM_IRQCTL Bit-Fields */
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#define S3C_PCM_IRQCTL_IRQEN (0x1<<14)
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#define S3C_PCM_IRQCTL_WRDEN (0x1<<12)
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#define S3C_PCM_IRQCTL_TXEMPTYEN (0x1<<11)
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#define S3C_PCM_IRQCTL_TXALMSTEMPTYEN (0x1<<10)
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#define S3C_PCM_IRQCTL_TXFULLEN (0x1<<9)
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#define S3C_PCM_IRQCTL_TXALMSTFULLEN (0x1<<8)
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#define S3C_PCM_IRQCTL_TXSTARVEN (0x1<<7)
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#define S3C_PCM_IRQCTL_TXERROVRFLEN (0x1<<6)
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#define S3C_PCM_IRQCTL_RXEMPTEN (0x1<<5)
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#define S3C_PCM_IRQCTL_RXALMSTEMPTEN (0x1<<4)
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#define S3C_PCM_IRQCTL_RXFULLEN (0x1<<3)
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#define S3C_PCM_IRQCTL_RXALMSTFULLEN (0x1<<2)
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#define S3C_PCM_IRQCTL_RXSTARVEN (0x1<<1)
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#define S3C_PCM_IRQCTL_RXERROVRFLEN (0x1<<0)
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/* PCM_IRQSTAT Bit-Fields */
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#define S3C_PCM_IRQSTAT_IRQPND (0x1<<13)
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#define S3C_PCM_IRQSTAT_WRD_XFER (0x1<<12)
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#define S3C_PCM_IRQSTAT_TXEMPTY (0x1<<11)
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#define S3C_PCM_IRQSTAT_TXALMSTEMPTY (0x1<<10)
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#define S3C_PCM_IRQSTAT_TXFULL (0x1<<9)
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#define S3C_PCM_IRQSTAT_TXALMSTFULL (0x1<<8)
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#define S3C_PCM_IRQSTAT_TXSTARV (0x1<<7)
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#define S3C_PCM_IRQSTAT_TXERROVRFL (0x1<<6)
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#define S3C_PCM_IRQSTAT_RXEMPT (0x1<<5)
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#define S3C_PCM_IRQSTAT_RXALMSTEMPT (0x1<<4)
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#define S3C_PCM_IRQSTAT_RXFULL (0x1<<3)
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#define S3C_PCM_IRQSTAT_RXALMSTFULL (0x1<<2)
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#define S3C_PCM_IRQSTAT_RXSTARV (0x1<<1)
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#define S3C_PCM_IRQSTAT_RXERROVRFL (0x1<<0)
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/* PCM_FIFOSTAT Bit-Fields */
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#define S3C_PCM_FIFOSTAT_TXCNT_MSK (0x3f<<14)
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#define S3C_PCM_FIFOSTAT_TXFIFOEMPTY (0x1<<13)
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#define S3C_PCM_FIFOSTAT_TXFIFOALMSTEMPTY (0x1<<12)
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#define S3C_PCM_FIFOSTAT_TXFIFOFULL (0x1<<11)
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#define S3C_PCM_FIFOSTAT_TXFIFOALMSTFULL (0x1<<10)
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#define S3C_PCM_FIFOSTAT_RXCNT_MSK (0x3f<<4)
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#define S3C_PCM_FIFOSTAT_RXFIFOEMPTY (0x1<<3)
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#define S3C_PCM_FIFOSTAT_RXFIFOALMSTEMPTY (0x1<<2)
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#define S3C_PCM_FIFOSTAT_RXFIFOFULL (0x1<<1)
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#define S3C_PCM_FIFOSTAT_RXFIFOALMSTFULL (0x1<<0)
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#define S3C_PCM_CLKSRC_PCLK 0
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#define S3C_PCM_CLKSRC_MUX 1
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#define S3C_PCM_SCLK_PER_FS 0
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/**
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* struct s3c_pcm_info - S3C PCM Controller information
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* @dev: The parent device passed to use from the probe.
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* @regs: The pointer to the device register block.
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* @dma_playback: DMA information for playback channel.
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* @dma_capture: DMA information for capture channel.
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*/
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struct s3c_pcm_info {
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spinlock_t lock;
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struct device *dev;
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void __iomem *regs;
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unsigned int sclk_per_fs;
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/* Whether to keep PCMSCLK enabled even when idle(no active xfer) */
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unsigned int idleclk;
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struct clk *pclk;
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struct clk *cclk;
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struct s3c_dma_params *dma_playback;
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struct s3c_dma_params *dma_capture;
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};
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#endif /* __S3C_PCM_H */
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