ARM: tegra: clock: Miscellaneous clock updates
Correct max rates for pclk and sclk (Originally fixed by Dima Zavin <dima@android.com>) Correct max rate for plla (Originally fixed by Stephen Warren <swarren@nvidia.com>) Remove unnecessary no-op set_rate on audio clocks Add clock lookup entries for grhost, bsea, and vde clocks Update clock clookup entries for vcp, bsea, and vde clocks Add shared clock entries for sclk and emc Add a virtual cop clock to provide a reset op (Originally fixed by Dima Zavin <dima@android.com>) Pass set_rate on super clocks through to parent Fix pllx frequency table entry for 608 MHz Remove incorrect plla frequency table entries Acked-by: Olof Johansson <olof@lixom.net> Signed-off-by: Colin Cross <ccross@android.com>
This commit is contained in:
Colin Cross
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c2f44a9df9
Коммит
9c7dc562cd
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@ -356,11 +356,24 @@ static int tegra2_super_clk_set_parent(struct clk *c, struct clk *p)
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return -EINVAL;
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}
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/*
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* Super clocks have "clock skippers" instead of dividers. Dividing using
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* a clock skipper does not allow the voltage to be scaled down, so instead
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* adjust the rate of the parent clock. This requires that the parent of a
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* super clock have no other children, otherwise the rate will change
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* underneath the other children.
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*/
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static int tegra2_super_clk_set_rate(struct clk *c, unsigned long rate)
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{
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return clk_set_rate(c->parent, rate);
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}
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static struct clk_ops tegra_super_ops = {
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.init = tegra2_super_clk_init,
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.enable = tegra2_super_clk_enable,
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.disable = tegra2_super_clk_disable,
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.set_parent = tegra2_super_clk_set_parent,
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.set_rate = tegra2_super_clk_set_rate,
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};
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/* virtual cpu clock functions */
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@ -429,6 +442,20 @@ static struct clk_ops tegra_cpu_ops = {
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.set_rate = tegra2_cpu_clk_set_rate,
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};
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/* virtual cop clock functions. Used to acquire the fake 'cop' clock to
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* reset the COP block (i.e. AVP) */
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static void tegra2_cop_clk_reset(struct clk *c, bool assert)
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{
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unsigned long reg = assert ? RST_DEVICES_SET : RST_DEVICES_CLR;
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pr_debug("%s %s\n", __func__, assert ? "assert" : "deassert");
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clk_writel(1 << 1, reg);
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}
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static struct clk_ops tegra_cop_ops = {
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.reset = tegra2_cop_clk_reset,
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};
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/* bus clock functions */
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static void tegra2_bus_clk_init(struct clk *c)
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{
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@ -1199,30 +1226,10 @@ static int tegra2_audio_sync_clk_set_parent(struct clk *c, struct clk *p)
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return -EINVAL;
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}
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static int tegra2_audio_sync_clk_set_rate(struct clk *c, unsigned long rate)
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{
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unsigned long parent_rate;
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if (!c->parent) {
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pr_err("%s: clock has no parent\n", __func__);
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return -EINVAL;
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}
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parent_rate = c->parent->rate;
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if (rate != parent_rate) {
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pr_err("%s: %s/%ld differs from parent %s/%ld\n",
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__func__,
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c->name, rate,
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c->parent->name, parent_rate);
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return -EINVAL;
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}
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c->rate = parent_rate;
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return 0;
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}
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static struct clk_ops tegra_audio_sync_clk_ops = {
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.init = tegra2_audio_sync_clk_init,
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.enable = tegra2_audio_sync_clk_enable,
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.disable = tegra2_audio_sync_clk_disable,
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.set_rate = tegra2_audio_sync_clk_set_rate,
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.set_parent = tegra2_audio_sync_clk_set_parent,
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};
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@ -1558,8 +1565,6 @@ static struct clk tegra_pll_p_out4 = {
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static struct clk_pll_freq_table tegra_pll_a_freq_table[] = {
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{ 28800000, 56448000, 49, 25, 1, 1},
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{ 28800000, 73728000, 64, 25, 1, 1},
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{ 28800000, 11289600, 49, 25, 1, 1},
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{ 28800000, 12288000, 64, 25, 1, 1},
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{ 28800000, 24000000, 5, 6, 1, 1},
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{ 0, 0, 0, 0, 0, 0 },
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};
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@ -1570,7 +1575,7 @@ static struct clk tegra_pll_a = {
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.ops = &tegra_pll_ops,
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.reg = 0xb0,
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.parent = &tegra_pll_p_out1,
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.max_rate = 56448000,
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.max_rate = 73728000,
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.u.pll = {
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.input_min = 2000000,
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.input_max = 31000000,
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@ -1590,7 +1595,7 @@ static struct clk tegra_pll_a_out0 = {
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.parent = &tegra_pll_a,
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.reg = 0xb4,
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.reg_shift = 0,
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.max_rate = 56448000,
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.max_rate = 73728000,
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};
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static struct clk_pll_freq_table tegra_pll_d_freq_table[] = {
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@ -1692,10 +1697,10 @@ static struct clk_pll_freq_table tegra_pll_x_freq_table[] = {
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{ 26000000, 760000000, 760, 26, 1, 12},
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/* 608 MHz */
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{ 12000000, 608000000, 760, 12, 1, 12},
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{ 13000000, 608000000, 760, 13, 1, 12},
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{ 12000000, 608000000, 608, 12, 1, 12},
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{ 13000000, 608000000, 608, 13, 1, 12},
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{ 19200000, 608000000, 380, 12, 1, 8},
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{ 26000000, 608000000, 760, 26, 1, 12},
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{ 26000000, 608000000, 608, 26, 1, 12},
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/* 456 MHz */
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{ 12000000, 456000000, 456, 12, 1, 12},
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@ -1808,7 +1813,7 @@ static struct clk tegra_clk_audio = {
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.name = "audio",
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.inputs = mux_audio_sync_clk,
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.reg = 0x38,
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.max_rate = 24000000,
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.max_rate = 73728000,
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.ops = &tegra_audio_sync_clk_ops
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};
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@ -1894,7 +1899,8 @@ static struct clk tegra_clk_sclk = {
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.inputs = mux_sclk,
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.reg = 0x28,
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.ops = &tegra_super_ops,
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.max_rate = 600000000,
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.max_rate = 240000000,
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.min_rate = 120000000,
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};
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static struct clk tegra_clk_virtual_cpu = {
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@ -1908,6 +1914,13 @@ static struct clk tegra_clk_virtual_cpu = {
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},
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};
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static struct clk tegra_clk_cop = {
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.name = "cop",
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.parent = &tegra_clk_sclk,
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.ops = &tegra_cop_ops,
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.max_rate = 240000000,
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};
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static struct clk tegra_clk_hclk = {
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.name = "hclk",
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.flags = DIV_BUS,
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@ -1925,7 +1938,7 @@ static struct clk tegra_clk_pclk = {
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.reg = 0x30,
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.reg_shift = 0,
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.ops = &tegra_bus_ops,
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.max_rate = 108000000,
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.max_rate = 120000000,
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};
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static struct clk tegra_clk_blink = {
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@ -2082,7 +2095,10 @@ struct clk tegra_list_clks[] = {
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PERIPH_CLK("sdmmc2", "sdhci-tegra.1", NULL, 9, 0x154, 52000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage */
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PERIPH_CLK("sdmmc3", "sdhci-tegra.2", NULL, 69, 0x1bc, 52000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage */
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PERIPH_CLK("sdmmc4", "sdhci-tegra.3", NULL, 15, 0x164, 52000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage */
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PERIPH_CLK("vde", "vde", NULL, 61, 0x1c8, 250000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage and process_id */
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PERIPH_CLK("vcp", "tegra-avp", "vcp", 29, 0, 250000000, mux_clk_m, 0),
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PERIPH_CLK("bsea", "tegra-avp", "bsea", 62, 0, 250000000, mux_clk_m, 0),
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PERIPH_CLK("bsev", "tegra-aes", "bsev", 63, 0, 250000000, mux_clk_m, 0),
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PERIPH_CLK("vde", "tegra-avp", "vde", 61, 0x1c8, 250000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage and process_id */
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PERIPH_CLK("csite", "csite", NULL, 73, 0x1d4, 144000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* max rate ??? */
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/* FIXME: what is la? */
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PERIPH_CLK("la", "la", NULL, 76, 0x1f8, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
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@ -2127,6 +2143,18 @@ struct clk tegra_list_clks[] = {
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PERIPH_CLK("pex", NULL, "pex", 70, 0, 26000000, mux_clk_m, PERIPH_MANUAL_RESET),
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PERIPH_CLK("afi", NULL, "afi", 72, 0, 26000000, mux_clk_m, PERIPH_MANUAL_RESET),
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PERIPH_CLK("pcie_xclk", NULL, "pcie_xclk", 74, 0, 26000000, mux_clk_m, PERIPH_MANUAL_RESET),
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SHARED_CLK("avp.sclk", "tegra-avp", "sclk", &tegra_clk_sclk),
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SHARED_CLK("avp.emc", "tegra-avp", "emc", &tegra_clk_emc),
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SHARED_CLK("cpu.emc", "cpu", "emc", &tegra_clk_emc),
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SHARED_CLK("disp1.emc", "tegradc.0", "emc", &tegra_clk_emc),
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SHARED_CLK("disp2.emc", "tegradc.1", "emc", &tegra_clk_emc),
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SHARED_CLK("hdmi.emc", "hdmi", "emc", &tegra_clk_emc),
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SHARED_CLK("host.emc", "tegra_grhost", "emc", &tegra_clk_emc),
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SHARED_CLK("usbd.emc", "fsl-tegra-udc", "emc", &tegra_clk_emc),
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SHARED_CLK("usb1.emc", "tegra-ehci.0", "emc", &tegra_clk_emc),
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SHARED_CLK("usb2.emc", "tegra-ehci.1", "emc", &tegra_clk_emc),
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SHARED_CLK("usb3.emc", "tegra-ehci.2", "emc", &tegra_clk_emc),
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};
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#define CLK_DUPLICATE(_name, _dev, _con) \
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@ -2157,6 +2185,13 @@ struct clk_duplicate tegra_clk_duplicates[] = {
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CLK_DUPLICATE("pwm", "tegra_pwm.1", NULL),
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CLK_DUPLICATE("pwm", "tegra_pwm.2", NULL),
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CLK_DUPLICATE("pwm", "tegra_pwm.3", NULL),
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CLK_DUPLICATE("host1x", "tegra_grhost", "host1x"),
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CLK_DUPLICATE("2d", "tegra_grhost", "gr2d"),
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CLK_DUPLICATE("3d", "tegra_grhost", "gr3d"),
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CLK_DUPLICATE("epp", "tegra_grhost", "epp"),
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CLK_DUPLICATE("mpe", "tegra_grhost", "mpe"),
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CLK_DUPLICATE("cop", "tegra-avp", "cop"),
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CLK_DUPLICATE("vde", "tegra-aes", "vde"),
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};
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#define CLK(dev, con, ck) \
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@ -2195,6 +2230,7 @@ struct clk *tegra_ptr_clks[] = {
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&tegra_dev2_clk,
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&tegra_clk_virtual_cpu,
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&tegra_clk_blink,
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&tegra_clk_cop,
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&tegra_clk_emc,
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};
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