Merge remote-tracking branch 'remotes/powerpc/topic/ppc-kvm' into kvm-ppc-next
This merges in the ppc-kvm topic branch of the powerpc repository to get some changes on which future patches will depend, in particular the definitions of various new TLB flushing functions. Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
This commit is contained in:
Paul Mackerras
Коммит
9c9e9cf40a
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@ -51,4 +51,11 @@ extern void radix__flush_tlb_all(void);
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extern void radix__flush_tlb_pte_p9_dd1(unsigned long old_pte, struct mm_struct *mm,
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unsigned long address);
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extern void radix__flush_tlb_lpid_page(unsigned int lpid,
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unsigned long addr,
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unsigned long page_size);
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extern void radix__flush_pwc_lpid(unsigned int lpid);
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extern void radix__local_flush_tlb_lpid(unsigned int lpid);
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extern void radix__local_flush_tlb_lpid_guest(unsigned int lpid);
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#endif
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@ -25,6 +25,7 @@
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#include <linux/kvm_para.h>
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#include <linux/slab.h>
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#include <linux/of.h>
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#include <linux/pagemap.h>
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#include <asm/reg.h>
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#include <asm/sections.h>
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@ -672,14 +673,13 @@ static void kvm_use_magic_page(void)
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{
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u32 *p;
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u32 *start, *end;
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u32 tmp;
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u32 features;
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/* Tell the host to map the magic page to -4096 on all CPUs */
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on_each_cpu(kvm_map_magic_page, &features, 1);
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/* Quick self-test to see if the mapping works */
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if (__get_user(tmp, (u32*)KVM_MAGIC_PAGE)) {
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if (!fault_in_pages_readable((const char *)KVM_MAGIC_PAGE, sizeof(u32))) {
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kvm_patching_worked = false;
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return;
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}
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@ -200,6 +200,7 @@ void kvmppc_radix_set_pte_at(struct kvm *kvm, unsigned long addr,
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}
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static struct kmem_cache *kvm_pte_cache;
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static struct kmem_cache *kvm_pmd_cache;
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static pte_t *kvmppc_pte_alloc(void)
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{
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@ -217,6 +218,16 @@ static inline int pmd_is_leaf(pmd_t pmd)
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return !!(pmd_val(pmd) & _PAGE_PTE);
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}
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static pmd_t *kvmppc_pmd_alloc(void)
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{
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return kmem_cache_alloc(kvm_pmd_cache, GFP_KERNEL);
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}
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static void kvmppc_pmd_free(pmd_t *pmdp)
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{
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kmem_cache_free(kvm_pmd_cache, pmdp);
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}
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static int kvmppc_create_pte(struct kvm *kvm, pte_t pte, unsigned long gpa,
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unsigned int level, unsigned long mmu_seq)
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{
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@ -239,7 +250,7 @@ static int kvmppc_create_pte(struct kvm *kvm, pte_t pte, unsigned long gpa,
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if (pud && pud_present(*pud) && !pud_huge(*pud))
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pmd = pmd_offset(pud, gpa);
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else if (level <= 1)
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new_pmd = pmd_alloc_one(kvm->mm, gpa);
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new_pmd = kvmppc_pmd_alloc();
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if (level == 0 && !(pmd && pmd_present(*pmd) && !pmd_is_leaf(*pmd)))
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new_ptep = kvmppc_pte_alloc();
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@ -382,7 +393,7 @@ static int kvmppc_create_pte(struct kvm *kvm, pte_t pte, unsigned long gpa,
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if (new_pud)
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pud_free(kvm->mm, new_pud);
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if (new_pmd)
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pmd_free(kvm->mm, new_pmd);
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kvmppc_pmd_free(new_pmd);
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if (new_ptep)
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kvmppc_pte_free(new_ptep);
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return ret;
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@ -758,7 +769,7 @@ void kvmppc_free_radix(struct kvm *kvm)
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kvmppc_pte_free(pte);
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pmd_clear(pmd);
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}
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pmd_free(kvm->mm, pmd_offset(pud, 0));
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kvmppc_pmd_free(pmd_offset(pud, 0));
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pud_clear(pud);
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}
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pud_free(kvm->mm, pud_offset(pgd, 0));
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@ -770,20 +781,35 @@ void kvmppc_free_radix(struct kvm *kvm)
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static void pte_ctor(void *addr)
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{
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memset(addr, 0, PTE_TABLE_SIZE);
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memset(addr, 0, RADIX_PTE_TABLE_SIZE);
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}
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static void pmd_ctor(void *addr)
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{
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memset(addr, 0, RADIX_PMD_TABLE_SIZE);
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}
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int kvmppc_radix_init(void)
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{
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unsigned long size = sizeof(void *) << PTE_INDEX_SIZE;
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unsigned long size = sizeof(void *) << RADIX_PTE_INDEX_SIZE;
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kvm_pte_cache = kmem_cache_create("kvm-pte", size, size, 0, pte_ctor);
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if (!kvm_pte_cache)
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return -ENOMEM;
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size = sizeof(void *) << RADIX_PMD_INDEX_SIZE;
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kvm_pmd_cache = kmem_cache_create("kvm-pmd", size, size, 0, pmd_ctor);
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if (!kvm_pmd_cache) {
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kmem_cache_destroy(kvm_pte_cache);
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return -ENOMEM;
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}
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return 0;
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}
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void kvmppc_radix_exit(void)
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{
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kmem_cache_destroy(kvm_pte_cache);
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kmem_cache_destroy(kvm_pmd_cache);
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}
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@ -118,6 +118,53 @@ static inline void __tlbie_pid(unsigned long pid, unsigned long ric)
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trace_tlbie(0, 0, rb, rs, ric, prs, r);
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}
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static inline void __tlbiel_lpid(unsigned long lpid, int set,
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unsigned long ric)
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{
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unsigned long rb,rs,prs,r;
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rb = PPC_BIT(52); /* IS = 2 */
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rb |= set << PPC_BITLSHIFT(51);
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rs = 0; /* LPID comes from LPIDR */
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prs = 0; /* partition scoped */
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r = 1; /* radix format */
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asm volatile(PPC_TLBIEL(%0, %4, %3, %2, %1)
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: : "r"(rb), "i"(r), "i"(prs), "i"(ric), "r"(rs) : "memory");
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trace_tlbie(lpid, 1, rb, rs, ric, prs, r);
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}
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static inline void __tlbie_lpid(unsigned long lpid, unsigned long ric)
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{
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unsigned long rb,rs,prs,r;
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rb = PPC_BIT(52); /* IS = 2 */
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rs = lpid;
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prs = 0; /* partition scoped */
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r = 1; /* radix format */
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asm volatile(PPC_TLBIE_5(%0, %4, %3, %2, %1)
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: : "r"(rb), "i"(r), "i"(prs), "i"(ric), "r"(rs) : "memory");
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trace_tlbie(lpid, 0, rb, rs, ric, prs, r);
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}
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static inline void __tlbiel_lpid_guest(unsigned long lpid, int set,
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unsigned long ric)
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{
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unsigned long rb,rs,prs,r;
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rb = PPC_BIT(52); /* IS = 2 */
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rb |= set << PPC_BITLSHIFT(51);
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rs = 0; /* LPID comes from LPIDR */
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prs = 1; /* process scoped */
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r = 1; /* radix format */
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asm volatile(PPC_TLBIEL(%0, %4, %3, %2, %1)
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: : "r"(rb), "i"(r), "i"(prs), "i"(ric), "r"(rs) : "memory");
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trace_tlbie(lpid, 1, rb, rs, ric, prs, r);
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}
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static inline void __tlbiel_va(unsigned long va, unsigned long pid,
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unsigned long ap, unsigned long ric)
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{
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@ -150,6 +197,22 @@ static inline void __tlbie_va(unsigned long va, unsigned long pid,
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trace_tlbie(0, 0, rb, rs, ric, prs, r);
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}
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static inline void __tlbie_lpid_va(unsigned long va, unsigned long lpid,
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unsigned long ap, unsigned long ric)
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{
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unsigned long rb,rs,prs,r;
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rb = va & ~(PPC_BITMASK(52, 63));
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rb |= ap << PPC_BITLSHIFT(58);
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rs = lpid;
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prs = 0; /* partition scoped */
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r = 1; /* radix format */
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asm volatile(PPC_TLBIE_5(%0, %4, %3, %2, %1)
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: : "r"(rb), "i"(r), "i"(prs), "i"(ric), "r"(rs) : "memory");
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trace_tlbie(lpid, 0, rb, rs, ric, prs, r);
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}
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static inline void fixup_tlbie(void)
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{
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unsigned long pid = 0;
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@ -161,6 +224,16 @@ static inline void fixup_tlbie(void)
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}
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}
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static inline void fixup_tlbie_lpid(unsigned long lpid)
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{
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unsigned long va = ((1UL << 52) - 1);
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if (cpu_has_feature(CPU_FTR_P9_TLBIE_BUG)) {
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asm volatile("ptesync": : :"memory");
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__tlbie_lpid_va(va, lpid, mmu_get_ap(MMU_PAGE_64K), RIC_FLUSH_TLB);
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}
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}
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/*
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* We use 128 set in radix mode and 256 set in hpt mode.
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*/
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@ -214,6 +287,86 @@ static inline void _tlbie_pid(unsigned long pid, unsigned long ric)
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asm volatile("eieio; tlbsync; ptesync": : :"memory");
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}
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static inline void _tlbiel_lpid(unsigned long lpid, unsigned long ric)
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{
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int set;
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VM_BUG_ON(mfspr(SPRN_LPID) != lpid);
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asm volatile("ptesync": : :"memory");
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/*
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* Flush the first set of the TLB, and if we're doing a RIC_FLUSH_ALL,
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* also flush the entire Page Walk Cache.
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*/
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__tlbiel_lpid(lpid, 0, ric);
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/* For PWC, only one flush is needed */
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if (ric == RIC_FLUSH_PWC) {
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asm volatile("ptesync": : :"memory");
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return;
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}
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/* For the remaining sets, just flush the TLB */
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for (set = 1; set < POWER9_TLB_SETS_RADIX ; set++)
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__tlbiel_lpid(lpid, set, RIC_FLUSH_TLB);
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asm volatile("ptesync": : :"memory");
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asm volatile(PPC_INVALIDATE_ERAT "; isync" : : :"memory");
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}
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static inline void _tlbie_lpid(unsigned long lpid, unsigned long ric)
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{
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asm volatile("ptesync": : :"memory");
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/*
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* Workaround the fact that the "ric" argument to __tlbie_pid
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* must be a compile-time contraint to match the "i" constraint
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* in the asm statement.
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*/
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switch (ric) {
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case RIC_FLUSH_TLB:
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__tlbie_lpid(lpid, RIC_FLUSH_TLB);
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break;
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case RIC_FLUSH_PWC:
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__tlbie_lpid(lpid, RIC_FLUSH_PWC);
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break;
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case RIC_FLUSH_ALL:
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default:
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__tlbie_lpid(lpid, RIC_FLUSH_ALL);
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}
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fixup_tlbie_lpid(lpid);
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asm volatile("eieio; tlbsync; ptesync": : :"memory");
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}
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static inline void _tlbiel_lpid_guest(unsigned long lpid, unsigned long ric)
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{
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int set;
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VM_BUG_ON(mfspr(SPRN_LPID) != lpid);
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asm volatile("ptesync": : :"memory");
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/*
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* Flush the first set of the TLB, and if we're doing a RIC_FLUSH_ALL,
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* also flush the entire Page Walk Cache.
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*/
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__tlbiel_lpid_guest(lpid, 0, ric);
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/* For PWC, only one flush is needed */
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if (ric == RIC_FLUSH_PWC) {
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asm volatile("ptesync": : :"memory");
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return;
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}
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/* For the remaining sets, just flush the TLB */
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for (set = 1; set < POWER9_TLB_SETS_RADIX ; set++)
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__tlbiel_lpid_guest(lpid, set, RIC_FLUSH_TLB);
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asm volatile("ptesync": : :"memory");
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}
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static inline void __tlbiel_va_range(unsigned long start, unsigned long end,
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unsigned long pid, unsigned long page_size,
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unsigned long psize)
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@ -268,6 +421,17 @@ static inline void _tlbie_va(unsigned long va, unsigned long pid,
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asm volatile("eieio; tlbsync; ptesync": : :"memory");
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}
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static inline void _tlbie_lpid_va(unsigned long va, unsigned long lpid,
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unsigned long psize, unsigned long ric)
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{
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unsigned long ap = mmu_get_ap(psize);
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asm volatile("ptesync": : :"memory");
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__tlbie_lpid_va(va, lpid, ap, ric);
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fixup_tlbie_lpid(lpid);
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asm volatile("eieio; tlbsync; ptesync": : :"memory");
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}
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static inline void _tlbie_va_range(unsigned long start, unsigned long end,
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unsigned long pid, unsigned long page_size,
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unsigned long psize, bool also_pwc)
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@ -534,6 +698,49 @@ static int radix_get_mmu_psize(int page_size)
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return psize;
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}
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/*
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* Flush partition scoped LPID address translation for all CPUs.
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*/
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void radix__flush_tlb_lpid_page(unsigned int lpid,
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unsigned long addr,
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unsigned long page_size)
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{
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int psize = radix_get_mmu_psize(page_size);
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_tlbie_lpid_va(addr, lpid, psize, RIC_FLUSH_TLB);
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}
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EXPORT_SYMBOL_GPL(radix__flush_tlb_lpid_page);
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/*
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* Flush partition scoped PWC from LPID for all CPUs.
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*/
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void radix__flush_pwc_lpid(unsigned int lpid)
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{
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_tlbie_lpid(lpid, RIC_FLUSH_PWC);
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}
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EXPORT_SYMBOL_GPL(radix__flush_pwc_lpid);
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/*
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* Flush partition scoped translations from LPID (=LPIDR)
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*/
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void radix__local_flush_tlb_lpid(unsigned int lpid)
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{
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_tlbiel_lpid(lpid, RIC_FLUSH_ALL);
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}
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EXPORT_SYMBOL_GPL(radix__local_flush_tlb_lpid);
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/*
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* Flush process scoped translations from LPID (=LPIDR).
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* Important difference, the guest normally manages its own translations,
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* but some cases e.g., vCPU CPU migration require KVM to flush.
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*/
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void radix__local_flush_tlb_lpid_guest(unsigned int lpid)
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{
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_tlbiel_lpid_guest(lpid, RIC_FLUSH_ALL);
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}
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EXPORT_SYMBOL_GPL(radix__local_flush_tlb_lpid_guest);
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static void radix__flush_tlb_pwc_range_psize(struct mm_struct *mm, unsigned long start,
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unsigned long end, int psize);
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