net: dsa: sja1105: parse {rx, tx}-internal-delay-ps properties for RGMII delays
This change does not fix any functional issue or address any real life
use case that wasn't possible before. It is just a small step in the
process of standardizing the way in which Ethernet MAC drivers may apply
RGMII delays (traditionally these have been applied by PHYs, with no
clear definition of what to do in the case of a fixed-link).
The sja1105 driver used to apply MAC-level RGMII delays on the RX data
lines when in fixed-link mode and using a phy-mode of "rgmii-rxid" or
"rgmii-id" and on the TX data lines when using "rgmii-txid" or "rgmii-id".
But the standard definitions don't say anything about behaving
differently when the port is in fixed-link vs when it isn't, and the new
device tree bindings are about having a way of applying the delays in a
way that is independent of the phy-mode and of the fixed-link property.
When the {rx,tx}-internal-delay-ps properties are present, use them,
otherwise fall back to the old behavior and warn.
One other thing to note is that the SJA1105 hardware applies a delay
value in degrees rather than in picoseconds (the delay in ps changes
depending on the frequency of the RGMII clock - 125 MHz at 1G, 25 MHz at
100M, 2.5MHz at 10M). I assume that is fine, we calculate the phase
shift of the internal delay lines assuming that the device tree meant
gigabit, and we let the hardware scale those according to the link speed.
Link: https://patchwork.kernel.org/project/netdevbpf/patch/20210723173108.459770-6-prasanna.vengateshan@microchip.com/
Link: https://patchwork.ozlabs.org/project/netdev/patch/20200616074955.GA9092@laureti-dev/#2461123
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Vladimir Oltean
David S. Miller
Родитель
ac41ac81e3
Коммит
9ca482a246
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@ -20,6 +20,27 @@
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#define SJA1105_AGEING_TIME_MS(ms) ((ms) / 10)
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#define SJA1105_NUM_L2_POLICERS SJA1110_MAX_L2_POLICING_COUNT
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/* Calculated assuming 1Gbps, where the clock has 125 MHz (8 ns period)
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* To avoid floating point operations, we'll multiply the degrees by 10
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* to get a "phase" and get 1 decimal point precision.
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*/
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#define SJA1105_RGMII_DELAY_PS_TO_PHASE(ps) \
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(((ps) * 360) / 800)
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#define SJA1105_RGMII_DELAY_PHASE_TO_PS(phase) \
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((800 * (phase)) / 360)
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#define SJA1105_RGMII_DELAY_PHASE_TO_HW(phase) \
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(((phase) - 738) / 9)
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#define SJA1105_RGMII_DELAY_PS_TO_HW(ps) \
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SJA1105_RGMII_DELAY_PHASE_TO_HW(SJA1105_RGMII_DELAY_PS_TO_PHASE(ps))
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/* Valid range in degrees is a value between 73.8 and 101.7
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* in 0.9 degree increments
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*/
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#define SJA1105_RGMII_DELAY_MIN_PS \
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SJA1105_RGMII_DELAY_PHASE_TO_PS(738)
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#define SJA1105_RGMII_DELAY_MAX_PS \
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SJA1105_RGMII_DELAY_PHASE_TO_PS(1017)
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typedef enum {
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SPI_READ = 0,
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SPI_WRITE = 1,
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@ -222,8 +243,8 @@ struct sja1105_flow_block {
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struct sja1105_private {
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struct sja1105_static_config static_config;
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bool rgmii_rx_delay[SJA1105_MAX_NUM_PORTS];
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bool rgmii_tx_delay[SJA1105_MAX_NUM_PORTS];
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int rgmii_rx_delay_ps[SJA1105_MAX_NUM_PORTS];
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int rgmii_tx_delay_ps[SJA1105_MAX_NUM_PORTS];
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phy_interface_t phy_mode[SJA1105_MAX_NUM_PORTS];
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bool fixed_link[SJA1105_MAX_NUM_PORTS];
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unsigned long ucast_egress_floods;
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@ -498,17 +498,6 @@ sja1110_cfg_pad_mii_id_packing(void *buf, struct sja1105_cfg_pad_mii_id *cmd,
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sja1105_packing(buf, &cmd->txc_pd, 0, 0, size, op);
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}
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/* Valid range in degrees is an integer between 73.8 and 101.7 */
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static u64 sja1105_rgmii_delay(u64 phase)
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{
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/* UM11040.pdf: The delay in degree phase is 73.8 + delay_tune * 0.9.
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* To avoid floating point operations we'll multiply by 10
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* and get 1 decimal point precision.
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*/
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phase *= 10;
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return (phase - 738) / 9;
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}
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/* The RGMII delay setup procedure is 2-step and gets called upon each
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* .phylink_mac_config. Both are strategic.
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* The reason is that the RX Tunable Delay Line of the SJA1105 MAC has issues
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@ -521,13 +510,15 @@ int sja1105pqrs_setup_rgmii_delay(const void *ctx, int port)
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const struct sja1105_private *priv = ctx;
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const struct sja1105_regs *regs = priv->info->regs;
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struct sja1105_cfg_pad_mii_id pad_mii_id = {0};
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int rx_delay = priv->rgmii_rx_delay_ps[port];
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int tx_delay = priv->rgmii_tx_delay_ps[port];
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u8 packed_buf[SJA1105_SIZE_CGU_CMD] = {0};
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int rc;
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if (priv->rgmii_rx_delay[port])
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pad_mii_id.rxc_delay = sja1105_rgmii_delay(90);
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if (priv->rgmii_tx_delay[port])
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pad_mii_id.txc_delay = sja1105_rgmii_delay(90);
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if (rx_delay)
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pad_mii_id.rxc_delay = SJA1105_RGMII_DELAY_PS_TO_HW(rx_delay);
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if (tx_delay)
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pad_mii_id.txc_delay = SJA1105_RGMII_DELAY_PS_TO_HW(tx_delay);
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/* Stage 1: Turn the RGMII delay lines off. */
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pad_mii_id.rxc_bypass = 1;
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@ -542,11 +533,11 @@ int sja1105pqrs_setup_rgmii_delay(const void *ctx, int port)
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return rc;
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/* Stage 2: Turn the RGMII delay lines on. */
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if (priv->rgmii_rx_delay[port]) {
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if (rx_delay) {
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pad_mii_id.rxc_bypass = 0;
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pad_mii_id.rxc_pd = 0;
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}
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if (priv->rgmii_tx_delay[port]) {
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if (tx_delay) {
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pad_mii_id.txc_bypass = 0;
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pad_mii_id.txc_pd = 0;
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}
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@ -561,20 +552,22 @@ int sja1110_setup_rgmii_delay(const void *ctx, int port)
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const struct sja1105_private *priv = ctx;
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const struct sja1105_regs *regs = priv->info->regs;
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struct sja1105_cfg_pad_mii_id pad_mii_id = {0};
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int rx_delay = priv->rgmii_rx_delay_ps[port];
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int tx_delay = priv->rgmii_tx_delay_ps[port];
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u8 packed_buf[SJA1105_SIZE_CGU_CMD] = {0};
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pad_mii_id.rxc_pd = 1;
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pad_mii_id.txc_pd = 1;
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if (priv->rgmii_rx_delay[port]) {
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pad_mii_id.rxc_delay = sja1105_rgmii_delay(90);
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if (rx_delay) {
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pad_mii_id.rxc_delay = SJA1105_RGMII_DELAY_PS_TO_HW(rx_delay);
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/* The "BYPASS" bit in SJA1110 is actually a "don't bypass" */
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pad_mii_id.rxc_bypass = 1;
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pad_mii_id.rxc_pd = 0;
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}
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if (priv->rgmii_tx_delay[port]) {
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pad_mii_id.txc_delay = sja1105_rgmii_delay(90);
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if (tx_delay) {
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pad_mii_id.txc_delay = SJA1105_RGMII_DELAY_PS_TO_HW(tx_delay);
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pad_mii_id.txc_bypass = 1;
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pad_mii_id.txc_pd = 0;
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}
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@ -1109,27 +1109,78 @@ static int sja1105_static_config_load(struct sja1105_private *priv)
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return sja1105_static_config_upload(priv);
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}
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static int sja1105_parse_rgmii_delays(struct sja1105_private *priv)
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/* This is the "new way" for a MAC driver to configure its RGMII delay lines,
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* based on the explicit "rx-internal-delay-ps" and "tx-internal-delay-ps"
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* properties. It has the advantage of working with fixed links and with PHYs
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* that apply RGMII delays too, and the MAC driver needs not perform any
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* special checks.
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*
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* Previously we were acting upon the "phy-mode" property when we were
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* operating in fixed-link, basically acting as a PHY, but with a reversed
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* interpretation: PHY_INTERFACE_MODE_RGMII_TXID means that the MAC should
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* behave as if it is connected to a PHY which has applied RGMII delays in the
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* TX direction. So if anything, RX delays should have been added by the MAC,
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* but we were adding TX delays.
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*
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* If the "{rx,tx}-internal-delay-ps" properties are not specified, we fall
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* back to the legacy behavior and apply delays on fixed-link ports based on
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* the reverse interpretation of the phy-mode. This is a deviation from the
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* expected default behavior which is to simply apply no delays. To achieve
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* that behavior with the new bindings, it is mandatory to specify
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* "{rx,tx}-internal-delay-ps" with a value of 0.
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*/
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static int sja1105_parse_rgmii_delays(struct sja1105_private *priv, int port,
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struct device_node *port_dn)
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{
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struct dsa_switch *ds = priv->ds;
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int port;
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phy_interface_t phy_mode = priv->phy_mode[port];
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struct device *dev = &priv->spidev->dev;
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int rx_delay = -1, tx_delay = -1;
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for (port = 0; port < ds->num_ports; port++) {
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if (!priv->fixed_link[port])
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continue;
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if (!phy_interface_mode_is_rgmii(phy_mode))
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return 0;
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if (priv->phy_mode[port] == PHY_INTERFACE_MODE_RGMII_RXID ||
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priv->phy_mode[port] == PHY_INTERFACE_MODE_RGMII_ID)
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priv->rgmii_rx_delay[port] = true;
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of_property_read_u32(port_dn, "rx-internal-delay-ps", &rx_delay);
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of_property_read_u32(port_dn, "tx-internal-delay-ps", &tx_delay);
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if (priv->phy_mode[port] == PHY_INTERFACE_MODE_RGMII_TXID ||
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priv->phy_mode[port] == PHY_INTERFACE_MODE_RGMII_ID)
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priv->rgmii_tx_delay[port] = true;
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if (rx_delay == -1 && tx_delay == -1 && priv->fixed_link[port]) {
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dev_warn(dev,
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"Port %d interpreting RGMII delay settings based on \"phy-mode\" property, "
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"please update device tree to specify \"rx-internal-delay-ps\" and "
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"\"tx-internal-delay-ps\"",
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port);
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if ((priv->rgmii_rx_delay[port] || priv->rgmii_tx_delay[port]) &&
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!priv->info->setup_rgmii_delay)
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return -EINVAL;
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if (phy_mode == PHY_INTERFACE_MODE_RGMII_RXID ||
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phy_mode == PHY_INTERFACE_MODE_RGMII_ID)
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rx_delay = 2000;
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if (phy_mode == PHY_INTERFACE_MODE_RGMII_TXID ||
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phy_mode == PHY_INTERFACE_MODE_RGMII_ID)
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tx_delay = 2000;
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}
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if (rx_delay < 0)
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rx_delay = 0;
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if (tx_delay < 0)
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tx_delay = 0;
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if ((rx_delay || tx_delay) && !priv->info->setup_rgmii_delay) {
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dev_err(dev, "Chip cannot apply RGMII delays\n");
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return -EINVAL;
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}
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if ((rx_delay && rx_delay < SJA1105_RGMII_DELAY_MIN_PS) ||
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(tx_delay && tx_delay < SJA1105_RGMII_DELAY_MIN_PS) ||
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(rx_delay > SJA1105_RGMII_DELAY_MAX_PS) ||
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(tx_delay > SJA1105_RGMII_DELAY_MAX_PS)) {
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dev_err(dev,
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"port %d RGMII delay values out of range, must be between %d and %d ps\n",
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port, SJA1105_RGMII_DELAY_MIN_PS, SJA1105_RGMII_DELAY_MAX_PS);
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return -ERANGE;
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}
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priv->rgmii_rx_delay_ps[port] = rx_delay;
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priv->rgmii_tx_delay_ps[port] = tx_delay;
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return 0;
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}
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@ -1180,6 +1231,10 @@ static int sja1105_parse_ports_node(struct sja1105_private *priv,
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}
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priv->phy_mode[index] = phy_mode;
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err = sja1105_parse_rgmii_delays(priv, index, child);
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if (err)
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return err;
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}
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return 0;
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@ -3317,15 +3372,6 @@ static int sja1105_probe(struct spi_device *spi)
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return rc;
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}
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/* Error out early if internal delays are required through DT
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* and we can't apply them.
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*/
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rc = sja1105_parse_rgmii_delays(priv);
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if (rc < 0) {
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dev_err(ds->dev, "RGMII delay not supported\n");
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return rc;
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}
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if (IS_ENABLED(CONFIG_NET_SCH_CBS)) {
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priv->cbs = devm_kcalloc(dev, priv->info->num_cbs_shapers,
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sizeof(struct sja1105_cbs_entry),
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