Merge commit 'v2.6.39-rc7' into sched/core
This commit is contained in:
Ingo Molnar
Коммит
9cb5baba5e
|
|
@ -294,6 +294,7 @@
|
|||
<!ENTITY sub-srggb10 SYSTEM "v4l/pixfmt-srggb10.xml">
|
||||
<!ENTITY sub-srggb8 SYSTEM "v4l/pixfmt-srggb8.xml">
|
||||
<!ENTITY sub-y10 SYSTEM "v4l/pixfmt-y10.xml">
|
||||
<!ENTITY sub-y12 SYSTEM "v4l/pixfmt-y12.xml">
|
||||
<!ENTITY sub-pixfmt SYSTEM "v4l/pixfmt.xml">
|
||||
<!ENTITY sub-cropcap SYSTEM "v4l/vidioc-cropcap.xml">
|
||||
<!ENTITY sub-dbg-g-register SYSTEM "v4l/vidioc-dbg-g-register.xml">
|
||||
|
|
|
|||
|
|
@ -34,7 +34,7 @@
|
|||
<varlistentry>
|
||||
<term><parameter>request</parameter></term>
|
||||
<listitem>
|
||||
<para>MEDIA_IOC_ENUM_LINKS</para>
|
||||
<para>MEDIA_IOC_SETUP_LINK</para>
|
||||
</listitem>
|
||||
</varlistentry>
|
||||
<varlistentry>
|
||||
|
|
|
|||
|
|
@ -0,0 +1,79 @@
|
|||
<refentry id="V4L2-PIX-FMT-Y12">
|
||||
<refmeta>
|
||||
<refentrytitle>V4L2_PIX_FMT_Y12 ('Y12 ')</refentrytitle>
|
||||
&manvol;
|
||||
</refmeta>
|
||||
<refnamediv>
|
||||
<refname><constant>V4L2_PIX_FMT_Y12</constant></refname>
|
||||
<refpurpose>Grey-scale image</refpurpose>
|
||||
</refnamediv>
|
||||
<refsect1>
|
||||
<title>Description</title>
|
||||
|
||||
<para>This is a grey-scale image with a depth of 12 bits per pixel. Pixels
|
||||
are stored in 16-bit words with unused high bits padded with 0. The least
|
||||
significant byte is stored at lower memory addresses (little-endian).</para>
|
||||
|
||||
<example>
|
||||
<title><constant>V4L2_PIX_FMT_Y12</constant> 4 × 4
|
||||
pixel image</title>
|
||||
|
||||
<formalpara>
|
||||
<title>Byte Order.</title>
|
||||
<para>Each cell is one byte.
|
||||
<informaltable frame="none">
|
||||
<tgroup cols="9" align="center">
|
||||
<colspec align="left" colwidth="2*" />
|
||||
<tbody valign="top">
|
||||
<row>
|
||||
<entry>start + 0:</entry>
|
||||
<entry>Y'<subscript>00low</subscript></entry>
|
||||
<entry>Y'<subscript>00high</subscript></entry>
|
||||
<entry>Y'<subscript>01low</subscript></entry>
|
||||
<entry>Y'<subscript>01high</subscript></entry>
|
||||
<entry>Y'<subscript>02low</subscript></entry>
|
||||
<entry>Y'<subscript>02high</subscript></entry>
|
||||
<entry>Y'<subscript>03low</subscript></entry>
|
||||
<entry>Y'<subscript>03high</subscript></entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry>start + 8:</entry>
|
||||
<entry>Y'<subscript>10low</subscript></entry>
|
||||
<entry>Y'<subscript>10high</subscript></entry>
|
||||
<entry>Y'<subscript>11low</subscript></entry>
|
||||
<entry>Y'<subscript>11high</subscript></entry>
|
||||
<entry>Y'<subscript>12low</subscript></entry>
|
||||
<entry>Y'<subscript>12high</subscript></entry>
|
||||
<entry>Y'<subscript>13low</subscript></entry>
|
||||
<entry>Y'<subscript>13high</subscript></entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry>start + 16:</entry>
|
||||
<entry>Y'<subscript>20low</subscript></entry>
|
||||
<entry>Y'<subscript>20high</subscript></entry>
|
||||
<entry>Y'<subscript>21low</subscript></entry>
|
||||
<entry>Y'<subscript>21high</subscript></entry>
|
||||
<entry>Y'<subscript>22low</subscript></entry>
|
||||
<entry>Y'<subscript>22high</subscript></entry>
|
||||
<entry>Y'<subscript>23low</subscript></entry>
|
||||
<entry>Y'<subscript>23high</subscript></entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry>start + 24:</entry>
|
||||
<entry>Y'<subscript>30low</subscript></entry>
|
||||
<entry>Y'<subscript>30high</subscript></entry>
|
||||
<entry>Y'<subscript>31low</subscript></entry>
|
||||
<entry>Y'<subscript>31high</subscript></entry>
|
||||
<entry>Y'<subscript>32low</subscript></entry>
|
||||
<entry>Y'<subscript>32high</subscript></entry>
|
||||
<entry>Y'<subscript>33low</subscript></entry>
|
||||
<entry>Y'<subscript>33high</subscript></entry>
|
||||
</row>
|
||||
</tbody>
|
||||
</tgroup>
|
||||
</informaltable>
|
||||
</para>
|
||||
</formalpara>
|
||||
</example>
|
||||
</refsect1>
|
||||
</refentry>
|
||||
|
|
@ -696,6 +696,7 @@ information.</para>
|
|||
&sub-packed-yuv;
|
||||
&sub-grey;
|
||||
&sub-y10;
|
||||
&sub-y12;
|
||||
&sub-y16;
|
||||
&sub-yuyv;
|
||||
&sub-uyvy;
|
||||
|
|
|
|||
|
|
@ -456,6 +456,23 @@
|
|||
<entry>b<subscript>1</subscript></entry>
|
||||
<entry>b<subscript>0</subscript></entry>
|
||||
</row>
|
||||
<row id="V4L2-MBUS-FMT-SGBRG8-1X8">
|
||||
<entry>V4L2_MBUS_FMT_SGBRG8_1X8</entry>
|
||||
<entry>0x3013</entry>
|
||||
<entry></entry>
|
||||
<entry>-</entry>
|
||||
<entry>-</entry>
|
||||
<entry>-</entry>
|
||||
<entry>-</entry>
|
||||
<entry>g<subscript>7</subscript></entry>
|
||||
<entry>g<subscript>6</subscript></entry>
|
||||
<entry>g<subscript>5</subscript></entry>
|
||||
<entry>g<subscript>4</subscript></entry>
|
||||
<entry>g<subscript>3</subscript></entry>
|
||||
<entry>g<subscript>2</subscript></entry>
|
||||
<entry>g<subscript>1</subscript></entry>
|
||||
<entry>g<subscript>0</subscript></entry>
|
||||
</row>
|
||||
<row id="V4L2-MBUS-FMT-SGRBG8-1X8">
|
||||
<entry>V4L2_MBUS_FMT_SGRBG8_1X8</entry>
|
||||
<entry>0x3002</entry>
|
||||
|
|
@ -473,6 +490,23 @@
|
|||
<entry>g<subscript>1</subscript></entry>
|
||||
<entry>g<subscript>0</subscript></entry>
|
||||
</row>
|
||||
<row id="V4L2-MBUS-FMT-SRGGB8-1X8">
|
||||
<entry>V4L2_MBUS_FMT_SRGGB8_1X8</entry>
|
||||
<entry>0x3014</entry>
|
||||
<entry></entry>
|
||||
<entry>-</entry>
|
||||
<entry>-</entry>
|
||||
<entry>-</entry>
|
||||
<entry>-</entry>
|
||||
<entry>r<subscript>7</subscript></entry>
|
||||
<entry>r<subscript>6</subscript></entry>
|
||||
<entry>r<subscript>5</subscript></entry>
|
||||
<entry>r<subscript>4</subscript></entry>
|
||||
<entry>r<subscript>3</subscript></entry>
|
||||
<entry>r<subscript>2</subscript></entry>
|
||||
<entry>r<subscript>1</subscript></entry>
|
||||
<entry>r<subscript>0</subscript></entry>
|
||||
</row>
|
||||
<row id="V4L2-MBUS-FMT-SBGGR10-DPCM8-1X8">
|
||||
<entry>V4L2_MBUS_FMT_SBGGR10_DPCM8_1X8</entry>
|
||||
<entry>0x300b</entry>
|
||||
|
|
@ -2159,6 +2193,31 @@
|
|||
<entry>u<subscript>1</subscript></entry>
|
||||
<entry>u<subscript>0</subscript></entry>
|
||||
</row>
|
||||
<row id="V4L2-MBUS-FMT-Y12-1X12">
|
||||
<entry>V4L2_MBUS_FMT_Y12_1X12</entry>
|
||||
<entry>0x2013</entry>
|
||||
<entry></entry>
|
||||
<entry>-</entry>
|
||||
<entry>-</entry>
|
||||
<entry>-</entry>
|
||||
<entry>-</entry>
|
||||
<entry>-</entry>
|
||||
<entry>-</entry>
|
||||
<entry>-</entry>
|
||||
<entry>-</entry>
|
||||
<entry>y<subscript>11</subscript></entry>
|
||||
<entry>y<subscript>10</subscript></entry>
|
||||
<entry>y<subscript>9</subscript></entry>
|
||||
<entry>y<subscript>8</subscript></entry>
|
||||
<entry>y<subscript>7</subscript></entry>
|
||||
<entry>y<subscript>6</subscript></entry>
|
||||
<entry>y<subscript>5</subscript></entry>
|
||||
<entry>y<subscript>4</subscript></entry>
|
||||
<entry>y<subscript>3</subscript></entry>
|
||||
<entry>y<subscript>2</subscript></entry>
|
||||
<entry>y<subscript>1</subscript></entry>
|
||||
<entry>y<subscript>0</subscript></entry>
|
||||
</row>
|
||||
<row id="V4L2-MBUS-FMT-UYVY8-1X16">
|
||||
<entry>V4L2_MBUS_FMT_UYVY8_1X16</entry>
|
||||
<entry>0x200f</entry>
|
||||
|
|
|
|||
|
|
@ -52,8 +52,10 @@ Brief summary of control files.
|
|||
tasks # attach a task(thread) and show list of threads
|
||||
cgroup.procs # show list of processes
|
||||
cgroup.event_control # an interface for event_fd()
|
||||
memory.usage_in_bytes # show current memory(RSS+Cache) usage.
|
||||
memory.memsw.usage_in_bytes # show current memory+Swap usage
|
||||
memory.usage_in_bytes # show current res_counter usage for memory
|
||||
(See 5.5 for details)
|
||||
memory.memsw.usage_in_bytes # show current res_counter usage for memory+Swap
|
||||
(See 5.5 for details)
|
||||
memory.limit_in_bytes # set/show limit of memory usage
|
||||
memory.memsw.limit_in_bytes # set/show limit of memory+Swap usage
|
||||
memory.failcnt # show the number of memory usage hits limits
|
||||
|
|
@ -453,6 +455,15 @@ memory under it will be reclaimed.
|
|||
You can reset failcnt by writing 0 to failcnt file.
|
||||
# echo 0 > .../memory.failcnt
|
||||
|
||||
5.5 usage_in_bytes
|
||||
|
||||
For efficiency, as other kernel components, memory cgroup uses some optimization
|
||||
to avoid unnecessary cacheline false sharing. usage_in_bytes is affected by the
|
||||
method and doesn't show 'exact' value of memory(and swap) usage, it's an fuzz
|
||||
value for efficient access. (Of course, when necessary, it's synchronized.)
|
||||
If you want to know more exact memory usage, you should use RSS+CACHE(+SWAP)
|
||||
value in memory.stat(see 5.2).
|
||||
|
||||
6. Hierarchy support
|
||||
|
||||
The memory controller supports a deep hierarchy and hierarchical accounting.
|
||||
|
|
|
|||
|
|
@ -66,10 +66,10 @@ trick is to ensure that any needed memory allocations are done before
|
|||
entering atomic context, using:
|
||||
|
||||
int flex_array_prealloc(struct flex_array *array, unsigned int start,
|
||||
unsigned int end, gfp_t flags);
|
||||
unsigned int nr_elements, gfp_t flags);
|
||||
|
||||
This function will ensure that memory for the elements indexed in the range
|
||||
defined by start and end has been allocated. Thereafter, a
|
||||
defined by start and nr_elements has been allocated. Thereafter, a
|
||||
flex_array_put() call on an element in that range is guaranteed not to
|
||||
block.
|
||||
|
||||
|
|
|
|||
|
|
@ -14,10 +14,6 @@ Supported chips:
|
|||
Prefix: 'gl523sm'
|
||||
Addresses scanned: I2C 0x18 - 0x1a, 0x29 - 0x2b, 0x4c - 0x4e
|
||||
Datasheet:
|
||||
* Intel Xeon Processor
|
||||
Prefix: - any other - may require 'force_adm1021' parameter
|
||||
Addresses scanned: none
|
||||
Datasheet: Publicly available at Intel website
|
||||
* Maxim MAX1617
|
||||
Prefix: 'max1617'
|
||||
Addresses scanned: I2C 0x18 - 0x1a, 0x29 - 0x2b, 0x4c - 0x4e
|
||||
|
|
@ -91,21 +87,27 @@ will do no harm, but will return 'old' values. It is possible to make
|
|||
ADM1021-clones do faster measurements, but there is really no good reason
|
||||
for that.
|
||||
|
||||
Xeon support
|
||||
------------
|
||||
|
||||
Some Xeon processors have real max1617, adm1021, or compatible chips
|
||||
within them, with two temperature sensors.
|
||||
Netburst-based Xeon support
|
||||
---------------------------
|
||||
|
||||
Other Xeons have chips with only one sensor.
|
||||
Some Xeon processors based on the Netburst (early Pentium 4, from 2001 to
|
||||
2003) microarchitecture had real MAX1617, ADM1021, or compatible chips
|
||||
within them, with two temperature sensors. Other Xeon processors of this
|
||||
era (with 400 MHz FSB) had chips with only one temperature sensor.
|
||||
|
||||
If you have a Xeon, and the adm1021 module loads, and both temperatures
|
||||
appear valid, then things are good.
|
||||
If you have such an old Xeon, and you get two valid temperatures when
|
||||
loading the adm1021 module, then things are good.
|
||||
|
||||
If the adm1021 module doesn't load, you should try this:
|
||||
modprobe adm1021 force_adm1021=BUS,ADDRESS
|
||||
ADDRESS can only be 0x18, 0x1a, 0x29, 0x2b, 0x4c, or 0x4e.
|
||||
If nothing happens when loading the adm1021 module, and you are certain
|
||||
that your specific Xeon processor model includes compatible sensors, you
|
||||
will have to explicitly instantiate the sensor chips from user-space. See
|
||||
method 4 in Documentation/i2c/instantiating-devices. Possible slave
|
||||
addresses are 0x18, 0x1a, 0x29, 0x2b, 0x4c, or 0x4e. It is likely that
|
||||
only temp2 will be correct and temp1 will have to be ignored.
|
||||
|
||||
If you have dual Xeons you may have appear to have two separate
|
||||
adm1021-compatible chips, or two single-temperature sensors, at distinct
|
||||
addresses.
|
||||
Previous generations of the Xeon processor (based on Pentium II/III)
|
||||
didn't have these sensors. Next generations of Xeon processors (533 MHz
|
||||
FSB and faster) lost them, until the Core-based generation which
|
||||
introduced integrated digital thermal sensors. These are supported by
|
||||
the coretemp driver.
|
||||
|
|
|
|||
|
|
@ -32,6 +32,16 @@ Supported chips:
|
|||
Addresses scanned: I2C 0x4c and 0x4d
|
||||
Datasheet: Publicly available at the ON Semiconductor website
|
||||
http://www.onsemi.com/PowerSolutions/product.do?id=ADT7461
|
||||
* Analog Devices ADT7461A
|
||||
Prefix: 'adt7461a'
|
||||
Addresses scanned: I2C 0x4c and 0x4d
|
||||
Datasheet: Publicly available at the ON Semiconductor website
|
||||
http://www.onsemi.com/PowerSolutions/product.do?id=ADT7461A
|
||||
* ON Semiconductor NCT1008
|
||||
Prefix: 'nct1008'
|
||||
Addresses scanned: I2C 0x4c and 0x4d
|
||||
Datasheet: Publicly available at the ON Semiconductor website
|
||||
http://www.onsemi.com/PowerSolutions/product.do?id=NCT1008
|
||||
* Maxim MAX6646
|
||||
Prefix: 'max6646'
|
||||
Addresses scanned: I2C 0x4d
|
||||
|
|
@ -149,7 +159,7 @@ ADM1032:
|
|||
* ALERT is triggered by open remote sensor.
|
||||
* SMBus PEC support for Write Byte and Receive Byte transactions.
|
||||
|
||||
ADT7461:
|
||||
ADT7461, ADT7461A, NCT1008:
|
||||
* Extended temperature range (breaks compatibility)
|
||||
* Lower resolution for remote temperature
|
||||
|
||||
|
|
@ -195,9 +205,9 @@ are exported, one for each channel, but these values are of course linked.
|
|||
Only the local hysteresis can be set from user-space, and the same delta
|
||||
applies to the remote hysteresis.
|
||||
|
||||
The lm90 driver will not update its values more frequently than every
|
||||
other second; reading them more often will do no harm, but will return
|
||||
'old' values.
|
||||
The lm90 driver will not update its values more frequently than configured with
|
||||
the update_interval attribute; reading them more often will do no harm, but will
|
||||
return 'old' values.
|
||||
|
||||
SMBus Alert Support
|
||||
-------------------
|
||||
|
|
@ -205,11 +215,12 @@ SMBus Alert Support
|
|||
This driver has basic support for SMBus alert. When an alert is received,
|
||||
the status register is read and the faulty temperature channel is logged.
|
||||
|
||||
The Analog Devices chips (ADM1032 and ADT7461) do not implement the SMBus
|
||||
alert protocol properly so additional care is needed: the ALERT output is
|
||||
disabled when an alert is received, and is re-enabled only when the alarm
|
||||
is gone. Otherwise the chip would block alerts from other chips in the bus
|
||||
as long as the alarm is active.
|
||||
The Analog Devices chips (ADM1032, ADT7461 and ADT7461A) and ON
|
||||
Semiconductor chips (NCT1008) do not implement the SMBus alert protocol
|
||||
properly so additional care is needed: the ALERT output is disabled when
|
||||
an alert is received, and is re-enabled only when the alarm is gone.
|
||||
Otherwise the chip would block alerts from other chips in the bus as long
|
||||
as the alarm is active.
|
||||
|
||||
PEC Support
|
||||
-----------
|
||||
|
|
|
|||
|
|
@ -0,0 +1,62 @@
|
|||
Kernel driver max16064
|
||||
======================
|
||||
|
||||
Supported chips:
|
||||
* Maxim MAX16064
|
||||
Prefix: 'max16064'
|
||||
Addresses scanned: -
|
||||
Datasheet: http://datasheets.maxim-ic.com/en/ds/MAX16064.pdf
|
||||
|
||||
Author: Guenter Roeck <guenter.roeck@ericsson.com>
|
||||
|
||||
|
||||
Description
|
||||
-----------
|
||||
|
||||
This driver supports hardware montoring for Maxim MAX16064 Quad Power-Supply
|
||||
Controller with Active-Voltage Output Control and PMBus Interface.
|
||||
|
||||
The driver is a client driver to the core PMBus driver.
|
||||
Please see Documentation/hwmon/pmbus for details on PMBus client drivers.
|
||||
|
||||
|
||||
Usage Notes
|
||||
-----------
|
||||
|
||||
This driver does not auto-detect devices. You will have to instantiate the
|
||||
devices explicitly. Please see Documentation/i2c/instantiating-devices for
|
||||
details.
|
||||
|
||||
|
||||
Platform data support
|
||||
---------------------
|
||||
|
||||
The driver supports standard PMBus driver platform data.
|
||||
|
||||
|
||||
Sysfs entries
|
||||
-------------
|
||||
|
||||
The following attributes are supported. Limits are read-write; all other
|
||||
attributes are read-only.
|
||||
|
||||
in[1-4]_label "vout[1-4]"
|
||||
in[1-4]_input Measured voltage. From READ_VOUT register.
|
||||
in[1-4]_min Minumum Voltage. From VOUT_UV_WARN_LIMIT register.
|
||||
in[1-4]_max Maximum voltage. From VOUT_OV_WARN_LIMIT register.
|
||||
in[1-4]_lcrit Critical minumum Voltage. VOUT_UV_FAULT_LIMIT register.
|
||||
in[1-4]_crit Critical maximum voltage. From VOUT_OV_FAULT_LIMIT register.
|
||||
in[1-4]_min_alarm Voltage low alarm. From VOLTAGE_UV_WARNING status.
|
||||
in[1-4]_max_alarm Voltage high alarm. From VOLTAGE_OV_WARNING status.
|
||||
in[1-4]_lcrit_alarm Voltage critical low alarm. From VOLTAGE_UV_FAULT status.
|
||||
in[1-4]_crit_alarm Voltage critical high alarm. From VOLTAGE_OV_FAULT status.
|
||||
|
||||
temp1_input Measured temperature. From READ_TEMPERATURE_1 register.
|
||||
temp1_max Maximum temperature. From OT_WARN_LIMIT register.
|
||||
temp1_crit Critical high temperature. From OT_FAULT_LIMIT register.
|
||||
temp1_max_alarm Chip temperature high alarm. Set by comparing
|
||||
READ_TEMPERATURE_1 with OT_WARN_LIMIT if TEMP_OT_WARNING
|
||||
status is set.
|
||||
temp1_crit_alarm Chip temperature critical high alarm. Set by comparing
|
||||
READ_TEMPERATURE_1 with OT_FAULT_LIMIT if TEMP_OT_FAULT
|
||||
status is set.
|
||||
|
|
@ -0,0 +1,79 @@
|
|||
Kernel driver max34440
|
||||
======================
|
||||
|
||||
Supported chips:
|
||||
* Maxim MAX34440
|
||||
Prefixes: 'max34440'
|
||||
Addresses scanned: -
|
||||
Datasheet: http://datasheets.maxim-ic.com/en/ds/MAX34440.pdf
|
||||
* Maxim MAX34441
|
||||
PMBus 5-Channel Power-Supply Manager and Intelligent Fan Controller
|
||||
Prefixes: 'max34441'
|
||||
Addresses scanned: -
|
||||
Datasheet: http://datasheets.maxim-ic.com/en/ds/MAX34441.pdf
|
||||
|
||||
Author: Guenter Roeck <guenter.roeck@ericsson.com>
|
||||
|
||||
|
||||
Description
|
||||
-----------
|
||||
|
||||
This driver supports hardware montoring for Maxim MAX34440 PMBus 6-Channel
|
||||
Power-Supply Manager and MAX34441 PMBus 5-Channel Power-Supply Manager
|
||||
and Intelligent Fan Controller.
|
||||
|
||||
The driver is a client driver to the core PMBus driver. Please see
|
||||
Documentation/hwmon/pmbus for details on PMBus client drivers.
|
||||
|
||||
|
||||
Usage Notes
|
||||
-----------
|
||||
|
||||
This driver does not auto-detect devices. You will have to instantiate the
|
||||
devices explicitly. Please see Documentation/i2c/instantiating-devices for
|
||||
details.
|
||||
|
||||
|
||||
Platform data support
|
||||
---------------------
|
||||
|
||||
The driver supports standard PMBus driver platform data.
|
||||
|
||||
|
||||
Sysfs entries
|
||||
-------------
|
||||
|
||||
The following attributes are supported. Limits are read-write; all other
|
||||
attributes are read-only.
|
||||
|
||||
in[1-6]_label "vout[1-6]".
|
||||
in[1-6]_input Measured voltage. From READ_VOUT register.
|
||||
in[1-6]_min Minumum Voltage. From VOUT_UV_WARN_LIMIT register.
|
||||
in[1-6]_max Maximum voltage. From VOUT_OV_WARN_LIMIT register.
|
||||
in[1-6]_lcrit Critical minumum Voltage. VOUT_UV_FAULT_LIMIT register.
|
||||
in[1-6]_crit Critical maximum voltage. From VOUT_OV_FAULT_LIMIT register.
|
||||
in[1-6]_min_alarm Voltage low alarm. From VOLTAGE_UV_WARNING status.
|
||||
in[1-6]_max_alarm Voltage high alarm. From VOLTAGE_OV_WARNING status.
|
||||
in[1-6]_lcrit_alarm Voltage critical low alarm. From VOLTAGE_UV_FAULT status.
|
||||
in[1-6]_crit_alarm Voltage critical high alarm. From VOLTAGE_OV_FAULT status.
|
||||
|
||||
curr[1-6]_label "iout[1-6]".
|
||||
curr[1-6]_input Measured current. From READ_IOUT register.
|
||||
curr[1-6]_max Maximum current. From IOUT_OC_WARN_LIMIT register.
|
||||
curr[1-6]_crit Critical maximum current. From IOUT_OC_FAULT_LIMIT register.
|
||||
curr[1-6]_max_alarm Current high alarm. From IOUT_OC_WARNING status.
|
||||
curr[1-6]_crit_alarm Current critical high alarm. From IOUT_OC_FAULT status.
|
||||
|
||||
in6 and curr6 attributes only exist for MAX34440.
|
||||
|
||||
temp[1-8]_input Measured temperatures. From READ_TEMPERATURE_1 register.
|
||||
temp1 is the chip's internal temperature. temp2..temp5
|
||||
are remote I2C temperature sensors. For MAX34441, temp6
|
||||
is a remote thermal-diode sensor. For MAX34440, temp6..8
|
||||
are remote I2C temperature sensors.
|
||||
temp[1-8]_max Maximum temperature. From OT_WARN_LIMIT register.
|
||||
temp[1-8]_crit Critical high temperature. From OT_FAULT_LIMIT register.
|
||||
temp[1-8]_max_alarm Temperature high alarm.
|
||||
temp[1-8]_crit_alarm Temperature critical high alarm.
|
||||
|
||||
temp7 and temp8 attributes only exist for MAX34440.
|
||||
|
|
@ -0,0 +1,69 @@
|
|||
Kernel driver max8688
|
||||
=====================
|
||||
|
||||
Supported chips:
|
||||
* Maxim MAX8688
|
||||
Prefix: 'max8688'
|
||||
Addresses scanned: -
|
||||
Datasheet: http://datasheets.maxim-ic.com/en/ds/MAX8688.pdf
|
||||
|
||||
Author: Guenter Roeck <guenter.roeck@ericsson.com>
|
||||
|
||||
|
||||
Description
|
||||
-----------
|
||||
|
||||
This driver supports hardware montoring for Maxim MAX8688 Digital Power-Supply
|
||||
Controller/Monitor with PMBus Interface.
|
||||
|
||||
The driver is a client driver to the core PMBus driver. Please see
|
||||
Documentation/hwmon/pmbus for details on PMBus client drivers.
|
||||
|
||||
|
||||
Usage Notes
|
||||
-----------
|
||||
|
||||
This driver does not auto-detect devices. You will have to instantiate the
|
||||
devices explicitly. Please see Documentation/i2c/instantiating-devices for
|
||||
details.
|
||||
|
||||
|
||||
Platform data support
|
||||
---------------------
|
||||
|
||||
The driver supports standard PMBus driver platform data.
|
||||
|
||||
|
||||
Sysfs entries
|
||||
-------------
|
||||
|
||||
The following attributes are supported. Limits are read-write; all other
|
||||
attributes are read-only.
|
||||
|
||||
in1_label "vout1"
|
||||
in1_input Measured voltage. From READ_VOUT register.
|
||||
in1_min Minumum Voltage. From VOUT_UV_WARN_LIMIT register.
|
||||
in1_max Maximum voltage. From VOUT_OV_WARN_LIMIT register.
|
||||
in1_lcrit Critical minumum Voltage. VOUT_UV_FAULT_LIMIT register.
|
||||
in1_crit Critical maximum voltage. From VOUT_OV_FAULT_LIMIT register.
|
||||
in1_min_alarm Voltage low alarm. From VOLTAGE_UV_WARNING status.
|
||||
in1_max_alarm Voltage high alarm. From VOLTAGE_OV_WARNING status.
|
||||
in1_lcrit_alarm Voltage critical low alarm. From VOLTAGE_UV_FAULT status.
|
||||
in1_crit_alarm Voltage critical high alarm. From VOLTAGE_OV_FAULT status.
|
||||
|
||||
curr1_label "iout1"
|
||||
curr1_input Measured current. From READ_IOUT register.
|
||||
curr1_max Maximum current. From IOUT_OC_WARN_LIMIT register.
|
||||
curr1_crit Critical maximum current. From IOUT_OC_FAULT_LIMIT register.
|
||||
curr1_max_alarm Current high alarm. From IOUT_OC_WARN_LIMIT register.
|
||||
curr1_crit_alarm Current critical high alarm. From IOUT_OC_FAULT status.
|
||||
|
||||
temp1_input Measured temperature. From READ_TEMPERATURE_1 register.
|
||||
temp1_max Maximum temperature. From OT_WARN_LIMIT register.
|
||||
temp1_crit Critical high temperature. From OT_FAULT_LIMIT register.
|
||||
temp1_max_alarm Chip temperature high alarm. Set by comparing
|
||||
READ_TEMPERATURE_1 with OT_WARN_LIMIT if TEMP_OT_WARNING
|
||||
status is set.
|
||||
temp1_crit_alarm Chip temperature critical high alarm. Set by comparing
|
||||
READ_TEMPERATURE_1 with OT_FAULT_LIMIT if TEMP_OT_FAULT
|
||||
status is set.
|
||||
|
|
@ -13,26 +13,6 @@ Supported chips:
|
|||
Prefix: 'ltc2978'
|
||||
Addresses scanned: -
|
||||
Datasheet: http://cds.linear.com/docs/Datasheet/2978fa.pdf
|
||||
* Maxim MAX16064
|
||||
Quad Power-Supply Controller
|
||||
Prefix: 'max16064'
|
||||
Addresses scanned: -
|
||||
Datasheet: http://datasheets.maxim-ic.com/en/ds/MAX16064.pdf
|
||||
* Maxim MAX34440
|
||||
PMBus 6-Channel Power-Supply Manager
|
||||
Prefixes: 'max34440'
|
||||
Addresses scanned: -
|
||||
Datasheet: http://datasheets.maxim-ic.com/en/ds/MAX34440.pdf
|
||||
* Maxim MAX34441
|
||||
PMBus 5-Channel Power-Supply Manager and Intelligent Fan Controller
|
||||
Prefixes: 'max34441'
|
||||
Addresses scanned: -
|
||||
Datasheet: http://datasheets.maxim-ic.com/en/ds/MAX34441.pdf
|
||||
* Maxim MAX8688
|
||||
Digital Power-Supply Controller/Monitor
|
||||
Prefix: 'max8688'
|
||||
Addresses scanned: -
|
||||
Datasheet: http://datasheets.maxim-ic.com/en/ds/MAX8688.pdf
|
||||
* Generic PMBus devices
|
||||
Prefix: 'pmbus'
|
||||
Addresses scanned: -
|
||||
|
|
@ -175,11 +155,13 @@ currX_crit Critical maximum current.
|
|||
From IIN_OC_FAULT_LIMIT or IOUT_OC_FAULT_LIMIT register.
|
||||
currX_alarm Current high alarm.
|
||||
From IIN_OC_WARNING or IOUT_OC_WARNING status.
|
||||
currX_max_alarm Current high alarm.
|
||||
From IIN_OC_WARN_LIMIT or IOUT_OC_WARN_LIMIT status.
|
||||
currX_lcrit_alarm Output current critical low alarm.
|
||||
From IOUT_UC_FAULT status.
|
||||
currX_crit_alarm Current critical high alarm.
|
||||
From IIN_OC_FAULT or IOUT_OC_FAULT status.
|
||||
currX_label "iin" or "vinY"
|
||||
currX_label "iin" or "ioutY"
|
||||
|
||||
powerX_input Measured power. From READ_PIN or READ_POUT register.
|
||||
powerX_cap Output power cap. From POUT_MAX register.
|
||||
|
|
@ -193,13 +175,13 @@ powerX_crit_alarm Output power critical high alarm.
|
|||
From POUT_OP_FAULT status.
|
||||
powerX_label "pin" or "poutY"
|
||||
|
||||
tempX_input Measured tempererature.
|
||||
tempX_input Measured temperature.
|
||||
From READ_TEMPERATURE_X register.
|
||||
tempX_min Mimimum tempererature. From UT_WARN_LIMIT register.
|
||||
tempX_max Maximum tempererature. From OT_WARN_LIMIT register.
|
||||
tempX_lcrit Critical low tempererature.
|
||||
tempX_min Mimimum temperature. From UT_WARN_LIMIT register.
|
||||
tempX_max Maximum temperature. From OT_WARN_LIMIT register.
|
||||
tempX_lcrit Critical low temperature.
|
||||
From UT_FAULT_LIMIT register.
|
||||
tempX_crit Critical high tempererature.
|
||||
tempX_crit Critical high temperature.
|
||||
From OT_FAULT_LIMIT register.
|
||||
tempX_min_alarm Chip temperature low alarm. Set by comparing
|
||||
READ_TEMPERATURE_X with UT_WARN_LIMIT if
|
||||
|
|
|
|||
|
|
@ -150,8 +150,8 @@ in8_crit_alarm Channel F critical alarm
|
|||
in9_crit_alarm AIN1 critical alarm
|
||||
in10_crit_alarm AIN2 critical alarm
|
||||
|
||||
temp1_input Chip tempererature
|
||||
temp1_min Mimimum chip tempererature
|
||||
temp1_max Maximum chip tempererature
|
||||
temp1_crit Critical chip tempererature
|
||||
temp1_input Chip temperature
|
||||
temp1_min Mimimum chip temperature
|
||||
temp1_max Maximum chip temperature
|
||||
temp1_crit Critical chip temperature
|
||||
temp1_crit_alarm Temperature critical alarm
|
||||
|
|
|
|||
|
|
@ -0,0 +1,109 @@
|
|||
How to Get Your Patch Accepted Into the Hwmon Subsystem
|
||||
-------------------------------------------------------
|
||||
|
||||
This text is is a collection of suggestions for people writing patches or
|
||||
drivers for the hwmon subsystem. Following these suggestions will greatly
|
||||
increase the chances of your change being accepted.
|
||||
|
||||
|
||||
1. General
|
||||
----------
|
||||
|
||||
* It should be unnecessary to mention, but please read and follow
|
||||
Documentation/SubmitChecklist
|
||||
Documentation/SubmittingDrivers
|
||||
Documentation/SubmittingPatches
|
||||
Documentation/CodingStyle
|
||||
|
||||
* If your patch generates checkpatch warnings, please refrain from explanations
|
||||
such as "I don't like that coding style". Keep in mind that each unnecessary
|
||||
warning helps hiding a real problem. If you don't like the kernel coding
|
||||
style, don't write kernel drivers.
|
||||
|
||||
* Please test your patch thoroughly. We are not your test group.
|
||||
Sometimes a patch can not or not completely be tested because of missing
|
||||
hardware. In such cases, you should test-build the code on at least one
|
||||
architecture. If run-time testing was not achieved, it should be written
|
||||
explicitly below the patch header.
|
||||
|
||||
* If your patch (or the driver) is affected by configuration options such as
|
||||
CONFIG_SMP or CONFIG_HOTPLUG, make sure it compiles for all configuration
|
||||
variants.
|
||||
|
||||
|
||||
2. Adding functionality to existing drivers
|
||||
-------------------------------------------
|
||||
|
||||
* Make sure the documentation in Documentation/hwmon/<driver_name> is up to
|
||||
date.
|
||||
|
||||
* Make sure the information in Kconfig is up to date.
|
||||
|
||||
* If the added functionality requires some cleanup or structural changes, split
|
||||
your patch into a cleanup part and the actual addition. This makes it easier
|
||||
to review your changes, and to bisect any resulting problems.
|
||||
|
||||
* Never mix bug fixes, cleanup, and functional enhancements in a single patch.
|
||||
|
||||
|
||||
3. New drivers
|
||||
--------------
|
||||
|
||||
* Running your patch or driver file(s) through checkpatch does not mean its
|
||||
formatting is clean. If unsure about formatting in your new driver, run it
|
||||
through Lindent. Lindent is not perfect, and you may have to do some minor
|
||||
cleanup, but it is a good start.
|
||||
|
||||
* Consider adding yourself to MAINTAINERS.
|
||||
|
||||
* Document the driver in Documentation/hwmon/<driver_name>.
|
||||
|
||||
* Add the driver to Kconfig and Makefile in alphabetical order.
|
||||
|
||||
* Make sure that all dependencies are listed in Kconfig. For new drivers, it
|
||||
is most likely prudent to add a dependency on EXPERIMENTAL.
|
||||
|
||||
* Avoid forward declarations if you can. Rearrange the code if necessary.
|
||||
|
||||
* Avoid calculations in macros and macro-generated functions. While such macros
|
||||
may save a line or so in the source, it obfuscates the code and makes code
|
||||
review more difficult. It may also result in code which is more complicated
|
||||
than necessary. Use inline functions or just regular functions instead.
|
||||
|
||||
* If the driver has a detect function, make sure it is silent. Debug messages
|
||||
and messages printed after a successful detection are acceptable, but it
|
||||
must not print messages such as "Chip XXX not found/supported".
|
||||
|
||||
Keep in mind that the detect function will run for all drivers supporting an
|
||||
address if a chip is detected on that address. Unnecessary messages will just
|
||||
pollute the kernel log and not provide any value.
|
||||
|
||||
* Provide a detect function if and only if a chip can be detected reliably.
|
||||
|
||||
* Avoid writing to chip registers in the detect function. If you have to write,
|
||||
only do it after you have already gathered enough data to be certain that the
|
||||
detection is going to be successful.
|
||||
|
||||
Keep in mind that the chip might not be what your driver believes it is, and
|
||||
writing to it might cause a bad misconfiguration.
|
||||
|
||||
* Make sure there are no race conditions in the probe function. Specifically,
|
||||
completely initialize your chip first, then create sysfs entries and register
|
||||
with the hwmon subsystem.
|
||||
|
||||
* Do not provide support for deprecated sysfs attributes.
|
||||
|
||||
* Do not create non-standard attributes unless really needed. If you have to use
|
||||
non-standard attributes, or you believe you do, discuss it on the mailing list
|
||||
first. Either case, provide a detailed explanation why you need the
|
||||
non-standard attribute(s).
|
||||
Standard attributes are specified in Documentation/hwmon/sysfs-interface.
|
||||
|
||||
* When deciding which sysfs attributes to support, look at the chip's
|
||||
capabilities. While we do not expect your driver to support everything the
|
||||
chip may offer, it should at least support all limits and alarms.
|
||||
|
||||
* Last but not least, please check if a driver for your chip already exists
|
||||
before starting to write a new driver. Especially for temperature sensors,
|
||||
new chips are often variants of previously released chips. In some cases,
|
||||
a presumably new chip may simply have been relabeled.
|
||||
|
|
@ -552,6 +552,16 @@ also have
|
|||
within the array where IO will be blocked. This is currently
|
||||
only supported for raid4/5/6.
|
||||
|
||||
sync_min
|
||||
sync_max
|
||||
The two values, given as numbers of sectors, indicate a range
|
||||
withing the array where 'check'/'repair' will operate. Must be
|
||||
a multiple of chunk_size. When it reaches "sync_max" it will
|
||||
pause, rather than complete.
|
||||
You can use 'select' or 'poll' on "sync_completed" to wait for
|
||||
that number to reach sync_max. Then you can either increase
|
||||
"sync_max", or can write 'idle' to "sync_action".
|
||||
|
||||
|
||||
Each active md device may also have attributes specific to the
|
||||
personality module that manages it.
|
||||
|
|
|
|||
|
|
@ -87,14 +87,14 @@ accumulator. ALSA uses accumulators 0 and 1 for left and right PCM.
|
|||
The result is forwarded to the ADC capture FIFO (thus to the standard capture
|
||||
PCM device).
|
||||
|
||||
name='Music Playback Volume',index=0
|
||||
name='Synth Playback Volume',index=0
|
||||
|
||||
This control is used to attenuate samples for left and right MIDI FX-bus
|
||||
accumulators. ALSA uses accumulators 4 and 5 for left and right MIDI samples.
|
||||
The result samples are forwarded to the front DAC PCM slots of the AC97 codec.
|
||||
|
||||
name='Music Capture Volume',index=0
|
||||
name='Music Capture Switch',index=0
|
||||
name='Synth Capture Volume',index=0
|
||||
name='Synth Capture Switch',index=0
|
||||
|
||||
These controls are used to attenuate samples for left and right MIDI FX-bus
|
||||
accumulator. ALSA uses accumulators 4 and 5 for left and right PCM.
|
||||
|
|
|
|||
|
|
@ -37,7 +37,7 @@ Generic scaling / cropping scheme
|
|||
-1'-
|
||||
|
||||
In the above chart minuses and slashes represent "real" data amounts, points and
|
||||
accents represent "useful" data, basically, CEU scaled amd cropped output,
|
||||
accents represent "useful" data, basically, CEU scaled and cropped output,
|
||||
mapped back onto the client's source plane.
|
||||
|
||||
Such a configuration can be produced by user requests:
|
||||
|
|
@ -65,7 +65,7 @@ Do not touch input rectangle - it is already optimal.
|
|||
|
||||
1. Calculate current sensor scales:
|
||||
|
||||
scale_s = ((3') - (3)) / ((2') - (2))
|
||||
scale_s = ((2') - (2)) / ((3') - (3))
|
||||
|
||||
2. Calculate "effective" input crop (sensor subwindow) - CEU crop scaled back at
|
||||
current sensor scales onto input window - this is user S_CROP:
|
||||
|
|
@ -80,7 +80,7 @@ window:
|
|||
4. Calculate sensor output window by applying combined scales to real input
|
||||
window:
|
||||
|
||||
width_s_out = ((2') - (2)) / scale_comb
|
||||
width_s_out = ((7') - (7)) = ((2') - (2)) / scale_comb
|
||||
|
||||
5. Apply iterative sensor S_FMT for sensor output window.
|
||||
|
||||
|
|
|
|||
|
|
@ -12,6 +12,7 @@ CONTENTS
|
|||
4. Application Programming Interface (API)
|
||||
5. Example Execution Scenarios
|
||||
6. Guidelines
|
||||
7. Debugging
|
||||
|
||||
|
||||
1. Introduction
|
||||
|
|
@ -379,3 +380,42 @@ If q1 has WQ_CPU_INTENSIVE set,
|
|||
* Unless work items are expected to consume a huge amount of CPU
|
||||
cycles, using a bound wq is usually beneficial due to the increased
|
||||
level of locality in wq operations and work item execution.
|
||||
|
||||
|
||||
7. Debugging
|
||||
|
||||
Because the work functions are executed by generic worker threads
|
||||
there are a few tricks needed to shed some light on misbehaving
|
||||
workqueue users.
|
||||
|
||||
Worker threads show up in the process list as:
|
||||
|
||||
root 5671 0.0 0.0 0 0 ? S 12:07 0:00 [kworker/0:1]
|
||||
root 5672 0.0 0.0 0 0 ? S 12:07 0:00 [kworker/1:2]
|
||||
root 5673 0.0 0.0 0 0 ? S 12:12 0:00 [kworker/0:0]
|
||||
root 5674 0.0 0.0 0 0 ? S 12:13 0:00 [kworker/1:0]
|
||||
|
||||
If kworkers are going crazy (using too much cpu), there are two types
|
||||
of possible problems:
|
||||
|
||||
1. Something beeing scheduled in rapid succession
|
||||
2. A single work item that consumes lots of cpu cycles
|
||||
|
||||
The first one can be tracked using tracing:
|
||||
|
||||
$ echo workqueue:workqueue_queue_work > /sys/kernel/debug/tracing/set_event
|
||||
$ cat /sys/kernel/debug/tracing/trace_pipe > out.txt
|
||||
(wait a few secs)
|
||||
^C
|
||||
|
||||
If something is busy looping on work queueing, it would be dominating
|
||||
the output and the offender can be determined with the work item
|
||||
function.
|
||||
|
||||
For the second type of problems it should be possible to just check
|
||||
the stack trace of the offending worker thread.
|
||||
|
||||
$ cat /proc/THE_OFFENDING_KWORKER/stack
|
||||
|
||||
The work item's function should be trivially visible in the stack
|
||||
trace.
|
||||
|
|
|
|||
34
MAINTAINERS
34
MAINTAINERS
|
|
@ -151,6 +151,7 @@ S: Maintained
|
|||
F: drivers/net/hamradio/6pack.c
|
||||
|
||||
8169 10/100/1000 GIGABIT ETHERNET DRIVER
|
||||
M: Realtek linux nic maintainers <nic_swsd@realtek.com>
|
||||
M: Francois Romieu <romieu@fr.zoreil.com>
|
||||
L: netdev@vger.kernel.org
|
||||
S: Maintained
|
||||
|
|
@ -1031,12 +1032,13 @@ W: http://www.fluff.org/ben/linux/
|
|||
S: Maintained
|
||||
F: arch/arm/mach-s3c64xx/
|
||||
|
||||
ARM/S5P ARM ARCHITECTURES
|
||||
ARM/S5P EXYNOS ARM ARCHITECTURES
|
||||
M: Kukjin Kim <kgene.kim@samsung.com>
|
||||
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
|
||||
L: linux-samsung-soc@vger.kernel.org (moderated for non-subscribers)
|
||||
S: Maintained
|
||||
F: arch/arm/mach-s5p*/
|
||||
F: arch/arm/mach-exynos*/
|
||||
|
||||
ARM/SAMSUNG MOBILE MACHINE SUPPORT
|
||||
M: Kyungmin Park <kyungmin.park@samsung.com>
|
||||
|
|
@ -2807,7 +2809,7 @@ GPIO SUBSYSTEM
|
|||
M: Grant Likely <grant.likely@secretlab.ca>
|
||||
S: Maintained
|
||||
T: git git://git.secretlab.ca/git/linux-2.6.git
|
||||
F: Documentation/gpio/gpio.txt
|
||||
F: Documentation/gpio.txt
|
||||
F: drivers/gpio/
|
||||
F: include/linux/gpio*
|
||||
|
||||
|
|
@ -5395,7 +5397,7 @@ F: drivers/media/video/*7146*
|
|||
F: include/media/*7146*
|
||||
|
||||
SAMSUNG AUDIO (ASoC) DRIVERS
|
||||
M: Jassi Brar <jassi.brar@samsung.com>
|
||||
M: Jassi Brar <jassisinghbrar@gmail.com>
|
||||
L: alsa-devel@alsa-project.org (moderated for non-subscribers)
|
||||
S: Supported
|
||||
F: sound/soc/samsung
|
||||
|
|
@ -6554,7 +6556,7 @@ S: Maintained
|
|||
F: drivers/usb/host/uhci*
|
||||
|
||||
USB "USBNET" DRIVER FRAMEWORK
|
||||
M: David Brownell <dbrownell@users.sourceforge.net>
|
||||
M: Oliver Neukum <oneukum@suse.de>
|
||||
L: netdev@vger.kernel.org
|
||||
W: http://www.linux-usb.org/usbnet
|
||||
S: Maintained
|
||||
|
|
@ -6920,6 +6922,18 @@ T: git git://git.kernel.org/pub/scm/linux/kernel/git/mjg59/platform-drivers-x86.
|
|||
S: Maintained
|
||||
F: drivers/platform/x86
|
||||
|
||||
XEN HYPERVISOR INTERFACE
|
||||
M: Jeremy Fitzhardinge <jeremy.fitzhardinge@citrix.com>
|
||||
M: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
|
||||
L: xen-devel@lists.xensource.com (moderated for non-subscribers)
|
||||
L: virtualization@lists.linux-foundation.org
|
||||
S: Supported
|
||||
F: arch/x86/xen/
|
||||
F: drivers/*/xen-*front.c
|
||||
F: drivers/xen/
|
||||
F: arch/x86/include/asm/xen/
|
||||
F: include/xen/
|
||||
|
||||
XEN NETWORK BACKEND DRIVER
|
||||
M: Ian Campbell <ian.campbell@citrix.com>
|
||||
L: xen-devel@lists.xensource.com (moderated for non-subscribers)
|
||||
|
|
@ -6941,18 +6955,6 @@ S: Supported
|
|||
F: arch/x86/xen/*swiotlb*
|
||||
F: drivers/xen/*swiotlb*
|
||||
|
||||
XEN HYPERVISOR INTERFACE
|
||||
M: Jeremy Fitzhardinge <jeremy.fitzhardinge@citrix.com>
|
||||
M: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
|
||||
L: xen-devel@lists.xensource.com (moderated for non-subscribers)
|
||||
L: virtualization@lists.linux-foundation.org
|
||||
S: Supported
|
||||
F: arch/x86/xen/
|
||||
F: drivers/*/xen-*front.c
|
||||
F: drivers/xen/
|
||||
F: arch/x86/include/asm/xen/
|
||||
F: include/xen/
|
||||
|
||||
XFS FILESYSTEM
|
||||
P: Silicon Graphics Inc
|
||||
M: Alex Elder <aelder@sgi.com>
|
||||
|
|
|
|||
2
Makefile
2
Makefile
|
|
@ -1,7 +1,7 @@
|
|||
VERSION = 2
|
||||
PATCHLEVEL = 6
|
||||
SUBLEVEL = 39
|
||||
EXTRAVERSION = -rc4
|
||||
EXTRAVERSION = -rc7
|
||||
NAME = Flesh-Eating Bats with Fangs
|
||||
|
||||
# *DOCUMENTATION*
|
||||
|
|
|
|||
|
|
@ -0,0 +1,48 @@
|
|||
CONFIG_EXPERIMENTAL=y
|
||||
CONFIG_LOG_BUF_SHIFT=14
|
||||
CONFIG_EMBEDDED=y
|
||||
# CONFIG_HOTPLUG is not set
|
||||
# CONFIG_ELF_CORE is not set
|
||||
# CONFIG_FUTEX is not set
|
||||
# CONFIG_TIMERFD is not set
|
||||
# CONFIG_VM_EVENT_COUNTERS is not set
|
||||
# CONFIG_COMPAT_BRK is not set
|
||||
CONFIG_SLAB=y
|
||||
# CONFIG_LBDAF is not set
|
||||
# CONFIG_BLK_DEV_BSG is not set
|
||||
# CONFIG_IOSCHED_DEADLINE is not set
|
||||
# CONFIG_IOSCHED_CFQ is not set
|
||||
# CONFIG_MMU is not set
|
||||
CONFIG_ARCH_AT91=y
|
||||
CONFIG_ARCH_AT91X40=y
|
||||
CONFIG_MACH_AT91EB01=y
|
||||
CONFIG_AT91_EARLY_USART0=y
|
||||
CONFIG_CPU_ARM7TDMI=y
|
||||
CONFIG_SET_MEM_PARAM=y
|
||||
CONFIG_DRAM_BASE=0x01000000
|
||||
CONFIG_DRAM_SIZE=0x00400000
|
||||
CONFIG_FLASH_MEM_BASE=0x01400000
|
||||
CONFIG_PROCESSOR_ID=0x14000040
|
||||
CONFIG_ZBOOT_ROM_TEXT=0x0
|
||||
CONFIG_ZBOOT_ROM_BSS=0x0
|
||||
CONFIG_BINFMT_FLAT=y
|
||||
# CONFIG_SUSPEND is not set
|
||||
# CONFIG_FW_LOADER is not set
|
||||
CONFIG_MTD=y
|
||||
CONFIG_MTD_PARTITIONS=y
|
||||
CONFIG_MTD_CHAR=y
|
||||
CONFIG_MTD_BLOCK=y
|
||||
CONFIG_MTD_RAM=y
|
||||
CONFIG_MTD_ROM=y
|
||||
CONFIG_BLK_DEV_RAM=y
|
||||
# CONFIG_INPUT is not set
|
||||
# CONFIG_SERIO is not set
|
||||
# CONFIG_VT is not set
|
||||
# CONFIG_DEVKMEM is not set
|
||||
# CONFIG_HW_RANDOM is not set
|
||||
# CONFIG_HWMON is not set
|
||||
# CONFIG_USB_SUPPORT is not set
|
||||
CONFIG_EXT2_FS=y
|
||||
# CONFIG_DNOTIFY is not set
|
||||
CONFIG_ROMFS_FS=y
|
||||
# CONFIG_ENABLE_MUST_CHECK is not set
|
||||
|
|
@ -2,6 +2,7 @@
|
|||
#define __ASM_ARM_CPUTYPE_H
|
||||
|
||||
#include <linux/stringify.h>
|
||||
#include <linux/kernel.h>
|
||||
|
||||
#define CPUID_ID 0
|
||||
#define CPUID_CACHETYPE 1
|
||||
|
|
|
|||
|
|
@ -39,10 +39,13 @@ typedef u32 kprobe_opcode_t;
|
|||
struct kprobe;
|
||||
typedef void (kprobe_insn_handler_t)(struct kprobe *, struct pt_regs *);
|
||||
|
||||
typedef unsigned long (kprobe_check_cc)(unsigned long);
|
||||
|
||||
/* Architecture specific copy of original instruction. */
|
||||
struct arch_specific_insn {
|
||||
kprobe_opcode_t *insn;
|
||||
kprobe_insn_handler_t *insn_handler;
|
||||
kprobe_check_cc *insn_check_cc;
|
||||
};
|
||||
|
||||
struct prev_kprobe {
|
||||
|
|
|
|||
|
|
@ -396,6 +396,10 @@
|
|||
#define __NR_fanotify_init (__NR_SYSCALL_BASE+367)
|
||||
#define __NR_fanotify_mark (__NR_SYSCALL_BASE+368)
|
||||
#define __NR_prlimit64 (__NR_SYSCALL_BASE+369)
|
||||
#define __NR_name_to_handle_at (__NR_SYSCALL_BASE+370)
|
||||
#define __NR_open_by_handle_at (__NR_SYSCALL_BASE+371)
|
||||
#define __NR_clock_adjtime (__NR_SYSCALL_BASE+372)
|
||||
#define __NR_syncfs (__NR_SYSCALL_BASE+373)
|
||||
|
||||
/*
|
||||
* The following SWIs are ARM private.
|
||||
|
|
|
|||
|
|
@ -379,6 +379,10 @@
|
|||
CALL(sys_fanotify_init)
|
||||
CALL(sys_fanotify_mark)
|
||||
CALL(sys_prlimit64)
|
||||
/* 370 */ CALL(sys_name_to_handle_at)
|
||||
CALL(sys_open_by_handle_at)
|
||||
CALL(sys_clock_adjtime)
|
||||
CALL(sys_syncfs)
|
||||
#ifndef syscalls_counted
|
||||
.equ syscalls_padding, ((NR_syscalls + 3) & ~3) - NR_syscalls
|
||||
#define syscalls_counted
|
||||
|
|
|
|||
Разница между файлами не показана из-за своего большого размера
Загрузить разницу
|
|
@ -134,6 +134,7 @@ static void __kprobes singlestep(struct kprobe *p, struct pt_regs *regs,
|
|||
struct kprobe_ctlblk *kcb)
|
||||
{
|
||||
regs->ARM_pc += 4;
|
||||
if (p->ainsn.insn_check_cc(regs->ARM_cpsr))
|
||||
p->ainsn.insn_handler(p, regs);
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -746,7 +746,8 @@ perf_callchain_user(struct perf_callchain_entry *entry, struct pt_regs *regs)
|
|||
|
||||
tail = (struct frame_tail __user *)regs->ARM_fp - 1;
|
||||
|
||||
while (tail && !((unsigned long)tail & 0x3))
|
||||
while ((entry->nr < PERF_MAX_STACK_DEPTH) &&
|
||||
tail && !((unsigned long)tail & 0x3))
|
||||
tail = user_backtrace(tail, entry);
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -767,12 +767,20 @@ long arch_ptrace(struct task_struct *child, long request,
|
|||
|
||||
#ifdef CONFIG_HAVE_HW_BREAKPOINT
|
||||
case PTRACE_GETHBPREGS:
|
||||
if (ptrace_get_breakpoints(child) < 0)
|
||||
return -ESRCH;
|
||||
|
||||
ret = ptrace_gethbpregs(child, addr,
|
||||
(unsigned long __user *)data);
|
||||
ptrace_put_breakpoints(child);
|
||||
break;
|
||||
case PTRACE_SETHBPREGS:
|
||||
if (ptrace_get_breakpoints(child) < 0)
|
||||
return -ESRCH;
|
||||
|
||||
ret = ptrace_sethbpregs(child, addr,
|
||||
(unsigned long __user *)data);
|
||||
ptrace_put_breakpoints(child);
|
||||
break;
|
||||
#endif
|
||||
|
||||
|
|
|
|||
|
|
@ -479,7 +479,7 @@ static void broadcast_timer_set_mode(enum clock_event_mode mode,
|
|||
{
|
||||
}
|
||||
|
||||
static void broadcast_timer_setup(struct clock_event_device *evt)
|
||||
static void __cpuinit broadcast_timer_setup(struct clock_event_device *evt)
|
||||
{
|
||||
evt->name = "dummy_timer";
|
||||
evt->features = CLOCK_EVT_FEAT_ONESHOT |
|
||||
|
|
|
|||
|
|
@ -311,7 +311,7 @@ asmlinkage long sys_oabi_semtimedop(int semid,
|
|||
long err;
|
||||
int i;
|
||||
|
||||
if (nsops < 1)
|
||||
if (nsops < 1 || nsops > SEMOPM)
|
||||
return -EINVAL;
|
||||
sops = kmalloc(sizeof(*sops) * nsops, GFP_KERNEL);
|
||||
if (!sops)
|
||||
|
|
|
|||
|
|
@ -83,6 +83,7 @@ config ARCH_AT91CAP9
|
|||
select CPU_ARM926T
|
||||
select GENERIC_CLOCKEVENTS
|
||||
select HAVE_FB_ATMEL
|
||||
select HAVE_NET_MACB
|
||||
|
||||
config ARCH_AT572D940HF
|
||||
bool "AT572D940HF"
|
||||
|
|
|
|||
|
|
@ -30,6 +30,11 @@
|
|||
#include <mach/board.h>
|
||||
#include "generic.h"
|
||||
|
||||
static void __init at91eb01_init_irq(void)
|
||||
{
|
||||
at91x40_init_interrupts(NULL);
|
||||
}
|
||||
|
||||
static void __init at91eb01_map_io(void)
|
||||
{
|
||||
at91x40_initialize(40000000);
|
||||
|
|
@ -38,7 +43,7 @@ static void __init at91eb01_map_io(void)
|
|||
MACHINE_START(AT91EB01, "Atmel AT91 EB01")
|
||||
/* Maintainer: Greg Ungerer <gerg@snapgear.com> */
|
||||
.timer = &at91x40_timer,
|
||||
.init_irq = at91x40_init_interrupts,
|
||||
.init_irq = at91eb01_init_irq,
|
||||
.map_io = at91eb01_map_io,
|
||||
MACHINE_END
|
||||
|
||||
|
|
|
|||
|
|
@ -27,6 +27,7 @@
|
|||
#define ARCH_ID_AT91SAM9G45 0x819b05a0
|
||||
#define ARCH_ID_AT91SAM9G45MRL 0x819b05a2 /* aka 9G45-ES2 & non ES lots */
|
||||
#define ARCH_ID_AT91SAM9G45ES 0x819b05a1 /* 9G45-ES (Engineering Sample) */
|
||||
#define ARCH_ID_AT91SAM9X5 0x819a05a0
|
||||
#define ARCH_ID_AT91CAP9 0x039A03A0
|
||||
|
||||
#define ARCH_ID_AT91SAM9XE128 0x329973a0
|
||||
|
|
@ -55,6 +56,12 @@ static inline unsigned long at91_cpu_fully_identify(void)
|
|||
#define ARCH_EXID_AT91SAM9G46 0x00000003
|
||||
#define ARCH_EXID_AT91SAM9G45 0x00000004
|
||||
|
||||
#define ARCH_EXID_AT91SAM9G15 0x00000000
|
||||
#define ARCH_EXID_AT91SAM9G35 0x00000001
|
||||
#define ARCH_EXID_AT91SAM9X35 0x00000002
|
||||
#define ARCH_EXID_AT91SAM9G25 0x00000003
|
||||
#define ARCH_EXID_AT91SAM9X25 0x00000004
|
||||
|
||||
static inline unsigned long at91_exid_identify(void)
|
||||
{
|
||||
return at91_sys_read(AT91_DBGU_EXID);
|
||||
|
|
@ -143,6 +150,27 @@ static inline unsigned long at91cap9_rev_identify(void)
|
|||
#define cpu_is_at91sam9m11() (0)
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_ARCH_AT91SAM9X5
|
||||
#define cpu_is_at91sam9x5() (at91_cpu_identify() == ARCH_ID_AT91SAM9X5)
|
||||
#define cpu_is_at91sam9g15() (cpu_is_at91sam9x5() && \
|
||||
(at91_exid_identify() == ARCH_EXID_AT91SAM9G15))
|
||||
#define cpu_is_at91sam9g35() (cpu_is_at91sam9x5() && \
|
||||
(at91_exid_identify() == ARCH_EXID_AT91SAM9G35))
|
||||
#define cpu_is_at91sam9x35() (cpu_is_at91sam9x5() && \
|
||||
(at91_exid_identify() == ARCH_EXID_AT91SAM9X35))
|
||||
#define cpu_is_at91sam9g25() (cpu_is_at91sam9x5() && \
|
||||
(at91_exid_identify() == ARCH_EXID_AT91SAM9G25))
|
||||
#define cpu_is_at91sam9x25() (cpu_is_at91sam9x5() && \
|
||||
(at91_exid_identify() == ARCH_EXID_AT91SAM9X25))
|
||||
#else
|
||||
#define cpu_is_at91sam9x5() (0)
|
||||
#define cpu_is_at91sam9g15() (0)
|
||||
#define cpu_is_at91sam9g35() (0)
|
||||
#define cpu_is_at91sam9x35() (0)
|
||||
#define cpu_is_at91sam9g25() (0)
|
||||
#define cpu_is_at91sam9x25() (0)
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_ARCH_AT91CAP9
|
||||
#define cpu_is_at91cap9() (at91_cpu_identify() == ARCH_ID_AT91CAP9)
|
||||
#define cpu_is_at91cap9_revB() (at91cap9_rev_identify() == ARCH_REVISION_CAP9_B)
|
||||
|
|
|
|||
|
|
@ -63,6 +63,7 @@ config MACH_DAVINCI_EVM
|
|||
depends on ARCH_DAVINCI_DM644x
|
||||
select MISC_DEVICES
|
||||
select EEPROM_AT24
|
||||
select I2C
|
||||
help
|
||||
Configure this option to specify the whether the board used
|
||||
for development is a DM644x EVM
|
||||
|
|
@ -72,6 +73,7 @@ config MACH_SFFSDR
|
|||
depends on ARCH_DAVINCI_DM644x
|
||||
select MISC_DEVICES
|
||||
select EEPROM_AT24
|
||||
select I2C
|
||||
help
|
||||
Say Y here to select the Lyrtech Small Form Factor
|
||||
Software Defined Radio (SFFSDR) board.
|
||||
|
|
@ -105,6 +107,7 @@ config MACH_DAVINCI_DM6467_EVM
|
|||
select MACH_DAVINCI_DM6467TEVM
|
||||
select MISC_DEVICES
|
||||
select EEPROM_AT24
|
||||
select I2C
|
||||
help
|
||||
Configure this option to specify the whether the board used
|
||||
for development is a DM6467 EVM
|
||||
|
|
@ -118,6 +121,7 @@ config MACH_DAVINCI_DM365_EVM
|
|||
depends on ARCH_DAVINCI_DM365
|
||||
select MISC_DEVICES
|
||||
select EEPROM_AT24
|
||||
select I2C
|
||||
help
|
||||
Configure this option to specify whether the board used
|
||||
for development is a DM365 EVM
|
||||
|
|
@ -129,6 +133,7 @@ config MACH_DAVINCI_DA830_EVM
|
|||
select GPIO_PCF857X
|
||||
select MISC_DEVICES
|
||||
select EEPROM_AT24
|
||||
select I2C
|
||||
help
|
||||
Say Y here to select the TI DA830/OMAP-L137/AM17x Evaluation Module.
|
||||
|
||||
|
|
@ -205,6 +210,7 @@ config MACH_MITYOMAPL138
|
|||
depends on ARCH_DAVINCI_DA850
|
||||
select MISC_DEVICES
|
||||
select EEPROM_AT24
|
||||
select I2C
|
||||
help
|
||||
Say Y here to select the Critical Link MityDSP-L138/MityARM-1808
|
||||
System on Module. Information on this SoM may be found at
|
||||
|
|
|
|||
|
|
@ -29,7 +29,7 @@
|
|||
#include <mach/mux.h>
|
||||
#include <mach/spi.h>
|
||||
|
||||
#define MITYOMAPL138_PHY_ID "0:03"
|
||||
#define MITYOMAPL138_PHY_ID ""
|
||||
|
||||
#define FACTORY_CONFIG_MAGIC 0x012C0138
|
||||
#define FACTORY_CONFIG_VERSION 0x00010001
|
||||
|
|
@ -414,7 +414,7 @@ static struct resource mityomapl138_nandflash_resource[] = {
|
|||
|
||||
static struct platform_device mityomapl138_nandflash_device = {
|
||||
.name = "davinci_nand",
|
||||
.id = 0,
|
||||
.id = 1,
|
||||
.dev = {
|
||||
.platform_data = &mityomapl138_nandflash_data,
|
||||
},
|
||||
|
|
|
|||
|
|
@ -39,7 +39,8 @@
|
|||
#define DA8XX_GPIO_BASE 0x01e26000
|
||||
#define DA8XX_I2C1_BASE 0x01e28000
|
||||
#define DA8XX_SPI0_BASE 0x01c41000
|
||||
#define DA8XX_SPI1_BASE 0x01f0e000
|
||||
#define DA830_SPI1_BASE 0x01e12000
|
||||
#define DA850_SPI1_BASE 0x01f0e000
|
||||
|
||||
#define DA8XX_EMAC_CTRL_REG_OFFSET 0x3000
|
||||
#define DA8XX_EMAC_MOD_REG_OFFSET 0x2000
|
||||
|
|
@ -762,8 +763,8 @@ static struct resource da8xx_spi0_resources[] = {
|
|||
|
||||
static struct resource da8xx_spi1_resources[] = {
|
||||
[0] = {
|
||||
.start = DA8XX_SPI1_BASE,
|
||||
.end = DA8XX_SPI1_BASE + SZ_4K - 1,
|
||||
.start = DA830_SPI1_BASE,
|
||||
.end = DA830_SPI1_BASE + SZ_4K - 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[1] = {
|
||||
|
|
@ -832,5 +833,10 @@ int __init da8xx_register_spi(int instance, struct spi_board_info *info,
|
|||
|
||||
da8xx_spi_pdata[instance].num_chipselect = len;
|
||||
|
||||
if (instance == 1 && cpu_is_davinci_da850()) {
|
||||
da8xx_spi1_resources[0].start = DA850_SPI1_BASE;
|
||||
da8xx_spi1_resources[0].end = DA850_SPI1_BASE + SZ_4K - 1;
|
||||
}
|
||||
|
||||
return platform_device_register(&da8xx_spi_device[instance]);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -314,7 +314,7 @@ static struct clk timer2_clk = {
|
|||
.name = "timer2",
|
||||
.parent = &pll1_aux_clk,
|
||||
.lpsc = DAVINCI_LPSC_TIMER2,
|
||||
.usecount = 1, /* REVISIT: why can't' this be disabled? */
|
||||
.usecount = 1, /* REVISIT: why can't this be disabled? */
|
||||
};
|
||||
|
||||
static struct clk timer3_clk = {
|
||||
|
|
|
|||
|
|
@ -274,7 +274,7 @@ static struct clk timer2_clk = {
|
|||
.name = "timer2",
|
||||
.parent = &pll1_aux_clk,
|
||||
.lpsc = DAVINCI_LPSC_TIMER2,
|
||||
.usecount = 1, /* REVISIT: why can't' this be disabled? */
|
||||
.usecount = 1, /* REVISIT: why can't this be disabled? */
|
||||
};
|
||||
|
||||
static struct clk_lookup dm644x_clks[] = {
|
||||
|
|
|
|||
|
|
@ -24,6 +24,9 @@
|
|||
|
||||
#define UART_SHIFT 2
|
||||
|
||||
#define davinci_uart_v2p(x) ((x) - PAGE_OFFSET + PLAT_PHYS_OFFSET)
|
||||
#define davinci_uart_p2v(x) ((x) - PLAT_PHYS_OFFSET + PAGE_OFFSET)
|
||||
|
||||
.pushsection .data
|
||||
davinci_uart_phys: .word 0
|
||||
davinci_uart_virt: .word 0
|
||||
|
|
@ -34,7 +37,7 @@ davinci_uart_virt: .word 0
|
|||
/* Use davinci_uart_phys/virt if already configured */
|
||||
10: mrc p15, 0, \rp, c1, c0
|
||||
tst \rp, #1 @ MMU enabled?
|
||||
ldreq \rp, =__virt_to_phys(davinci_uart_phys)
|
||||
ldreq \rp, =davinci_uart_v2p(davinci_uart_phys)
|
||||
ldrne \rp, =davinci_uart_phys
|
||||
add \rv, \rp, #4 @ davinci_uart_virt
|
||||
ldr \rp, [\rp, #0]
|
||||
|
|
@ -48,18 +51,18 @@ davinci_uart_virt: .word 0
|
|||
tst \rp, #1 @ MMU enabled?
|
||||
|
||||
/* Copy uart phys address from decompressor uart info */
|
||||
ldreq \rv, =__virt_to_phys(davinci_uart_phys)
|
||||
ldreq \rv, =davinci_uart_v2p(davinci_uart_phys)
|
||||
ldrne \rv, =davinci_uart_phys
|
||||
ldreq \rp, =DAVINCI_UART_INFO
|
||||
ldrne \rp, =__phys_to_virt(DAVINCI_UART_INFO)
|
||||
ldrne \rp, =davinci_uart_p2v(DAVINCI_UART_INFO)
|
||||
ldr \rp, [\rp, #0]
|
||||
str \rp, [\rv]
|
||||
|
||||
/* Copy uart virt address from decompressor uart info */
|
||||
ldreq \rv, =__virt_to_phys(davinci_uart_virt)
|
||||
ldreq \rv, =davinci_uart_v2p(davinci_uart_virt)
|
||||
ldrne \rv, =davinci_uart_virt
|
||||
ldreq \rp, =DAVINCI_UART_INFO
|
||||
ldrne \rp, =__phys_to_virt(DAVINCI_UART_INFO)
|
||||
ldrne \rp, =davinci_uart_p2v(DAVINCI_UART_INFO)
|
||||
ldr \rp, [\rp, #4]
|
||||
str \rp, [\rv]
|
||||
|
||||
|
|
|
|||
|
|
@ -22,7 +22,7 @@
|
|||
*
|
||||
* This area sits just below the page tables (see arch/arm/kernel/head.S).
|
||||
*/
|
||||
#define DAVINCI_UART_INFO (PHYS_OFFSET + 0x3ff8)
|
||||
#define DAVINCI_UART_INFO (PLAT_PHYS_OFFSET + 0x3ff8)
|
||||
|
||||
#define DAVINCI_UART0_BASE (IO_PHYS + 0x20000)
|
||||
#define DAVINCI_UART1_BASE (IO_PHYS + 0x20400)
|
||||
|
|
|
|||
|
|
@ -257,11 +257,16 @@ static const struct fsl_usb2_platform_data otg_device_pdata __initconst = {
|
|||
.workaround = FLS_USB2_WORKAROUND_ENGCM09152,
|
||||
};
|
||||
|
||||
static int vpr200_usbh_init(struct platform_device *pdev)
|
||||
{
|
||||
return mx35_initialize_usb_hw(pdev->id,
|
||||
MXC_EHCI_INTERFACE_SINGLE_UNI | MXC_EHCI_INTERNAL_PHY);
|
||||
}
|
||||
|
||||
/* USB HOST config */
|
||||
static const struct mxc_usbh_platform_data usb_host_pdata __initconst = {
|
||||
.init = vpr200_usbh_init,
|
||||
.portsc = MXC_EHCI_MODE_SERIAL,
|
||||
.flags = MXC_EHCI_INTERFACE_SINGLE_UNI |
|
||||
MXC_EHCI_INTERNAL_PHY,
|
||||
};
|
||||
|
||||
static struct platform_device *devices[] __initdata = {
|
||||
|
|
|
|||
|
|
@ -193,7 +193,7 @@ static iomux_v3_cfg_t mx53_loco_pads[] = {
|
|||
.wakeup = wake, \
|
||||
}
|
||||
|
||||
static const struct gpio_keys_button loco_buttons[] __initconst = {
|
||||
static struct gpio_keys_button loco_buttons[] = {
|
||||
GPIO_BUTTON(MX53_LOCO_POWER, KEY_POWER, 1, "power", 0),
|
||||
GPIO_BUTTON(MX53_LOCO_UI1, KEY_VOLUMEUP, 1, "volume-up", 0),
|
||||
GPIO_BUTTON(MX53_LOCO_UI2, KEY_VOLUMEDOWN, 1, "volume-down", 0),
|
||||
|
|
|
|||
|
|
@ -295,11 +295,11 @@ static int name##_set_rate(struct clk *clk, unsigned long rate) \
|
|||
unsigned long diff, parent_rate, calc_rate; \
|
||||
int i; \
|
||||
\
|
||||
parent_rate = clk_get_rate(clk->parent); \
|
||||
div_max = BM_CLKCTRL_##dr##_DIV >> BP_CLKCTRL_##dr##_DIV; \
|
||||
bm_busy = BM_CLKCTRL_##dr##_BUSY; \
|
||||
\
|
||||
if (clk->parent == &ref_xtal_clk) { \
|
||||
parent_rate = clk_get_rate(clk->parent); \
|
||||
div = DIV_ROUND_UP(parent_rate, rate); \
|
||||
if (clk == &cpu_clk) { \
|
||||
div_max = BM_CLKCTRL_CPU_DIV_XTAL >> \
|
||||
|
|
@ -309,6 +309,11 @@ static int name##_set_rate(struct clk *clk, unsigned long rate) \
|
|||
if (div == 0 || div > div_max) \
|
||||
return -EINVAL; \
|
||||
} else { \
|
||||
/* \
|
||||
* hack alert: this block modifies clk->parent, too, \
|
||||
* so the base to use it the grand parent. \
|
||||
*/ \
|
||||
parent_rate = clk_get_rate(clk->parent->parent); \
|
||||
rate >>= PARENT_RATE_SHIFT; \
|
||||
parent_rate >>= PARENT_RATE_SHIFT; \
|
||||
diff = parent_rate; \
|
||||
|
|
|
|||
|
|
@ -68,7 +68,7 @@ obj-$(CONFIG_OMAP_SMARTREFLEX) += sr_device.o smartreflex.o
|
|||
obj-$(CONFIG_OMAP_SMARTREFLEX_CLASS3) += smartreflex-class3.o
|
||||
|
||||
AFLAGS_sleep24xx.o :=-Wa,-march=armv6
|
||||
AFLAGS_sleep34xx.o :=-Wa,-march=armv7-a
|
||||
AFLAGS_sleep34xx.o :=-Wa,-march=armv7-a$(plus_sec)
|
||||
|
||||
ifeq ($(CONFIG_PM_VERBOSE),y)
|
||||
CFLAGS_pm_bus.o += -DDEBUG
|
||||
|
|
|
|||
|
|
@ -141,14 +141,19 @@ static void __init rx51_init(void)
|
|||
static void __init rx51_map_io(void)
|
||||
{
|
||||
omap2_set_globals_3xxx();
|
||||
rx51_video_mem_init();
|
||||
omap34xx_map_common_io();
|
||||
}
|
||||
|
||||
static void __init rx51_reserve(void)
|
||||
{
|
||||
rx51_video_mem_init();
|
||||
omap_reserve();
|
||||
}
|
||||
|
||||
MACHINE_START(NOKIA_RX51, "Nokia RX-51 board")
|
||||
/* Maintainer: Lauri Leukkunen <lauri.leukkunen@nokia.com> */
|
||||
.boot_params = 0x80000100,
|
||||
.reserve = omap_reserve,
|
||||
.reserve = rx51_reserve,
|
||||
.map_io = rx51_map_io,
|
||||
.init_early = rx51_init_early,
|
||||
.init_irq = omap_init_irq,
|
||||
|
|
|
|||
|
|
@ -3116,14 +3116,9 @@ static struct omap_clk omap44xx_clks[] = {
|
|||
CLK(NULL, "dsp_fck", &dsp_fck, CK_443X),
|
||||
CLK("omapdss_dss", "sys_clk", &dss_sys_clk, CK_443X),
|
||||
CLK("omapdss_dss", "tv_clk", &dss_tv_clk, CK_443X),
|
||||
CLK("omapdss_dss", "dss_clk", &dss_dss_clk, CK_443X),
|
||||
CLK("omapdss_dss", "video_clk", &dss_48mhz_clk, CK_443X),
|
||||
CLK("omapdss_dss", "fck", &dss_fck, CK_443X),
|
||||
/*
|
||||
* On OMAP4, DSS ick is a dummy clock; this is needed for compatibility
|
||||
* with OMAP2/3.
|
||||
*/
|
||||
CLK("omapdss_dss", "ick", &dummy_ck, CK_443X),
|
||||
CLK("omapdss_dss", "fck", &dss_dss_clk, CK_443X),
|
||||
CLK("omapdss_dss", "ick", &dss_fck, CK_443X),
|
||||
CLK(NULL, "efuse_ctrl_cust_fck", &efuse_ctrl_cust_fck, CK_443X),
|
||||
CLK(NULL, "emif1_fck", &emif1_fck, CK_443X),
|
||||
CLK(NULL, "emif2_fck", &emif2_fck, CK_443X),
|
||||
|
|
|
|||
|
|
@ -247,6 +247,7 @@ struct omap3_cm_regs {
|
|||
u32 per_cm_clksel;
|
||||
u32 emu_cm_clksel;
|
||||
u32 emu_cm_clkstctrl;
|
||||
u32 pll_cm_autoidle;
|
||||
u32 pll_cm_autoidle2;
|
||||
u32 pll_cm_clksel4;
|
||||
u32 pll_cm_clksel5;
|
||||
|
|
@ -319,6 +320,15 @@ void omap3_cm_save_context(void)
|
|||
omap2_cm_read_mod_reg(OMAP3430_EMU_MOD, CM_CLKSEL1);
|
||||
cm_context.emu_cm_clkstctrl =
|
||||
omap2_cm_read_mod_reg(OMAP3430_EMU_MOD, OMAP2_CM_CLKSTCTRL);
|
||||
/*
|
||||
* As per erratum i671, ROM code does not respect the PER DPLL
|
||||
* programming scheme if CM_AUTOIDLE_PLL.AUTO_PERIPH_DPLL == 1.
|
||||
* In this case, even though this register has been saved in
|
||||
* scratchpad contents, we need to restore AUTO_PERIPH_DPLL
|
||||
* by ourselves. So, we need to save it anyway.
|
||||
*/
|
||||
cm_context.pll_cm_autoidle =
|
||||
omap2_cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE);
|
||||
cm_context.pll_cm_autoidle2 =
|
||||
omap2_cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE2);
|
||||
cm_context.pll_cm_clksel4 =
|
||||
|
|
@ -441,6 +451,13 @@ void omap3_cm_restore_context(void)
|
|||
CM_CLKSEL1);
|
||||
omap2_cm_write_mod_reg(cm_context.emu_cm_clkstctrl, OMAP3430_EMU_MOD,
|
||||
OMAP2_CM_CLKSTCTRL);
|
||||
/*
|
||||
* As per erratum i671, ROM code does not respect the PER DPLL
|
||||
* programming scheme if CM_AUTOIDLE_PLL.AUTO_PERIPH_DPLL == 1.
|
||||
* In this case, we need to restore AUTO_PERIPH_DPLL by ourselves.
|
||||
*/
|
||||
omap2_cm_write_mod_reg(cm_context.pll_cm_autoidle, PLL_MOD,
|
||||
CM_AUTOIDLE);
|
||||
omap2_cm_write_mod_reg(cm_context.pll_cm_autoidle2, PLL_MOD,
|
||||
CM_AUTOIDLE2);
|
||||
omap2_cm_write_mod_reg(cm_context.pll_cm_clksel4, PLL_MOD,
|
||||
|
|
|
|||
|
|
@ -316,8 +316,14 @@ void omap3_save_scratchpad_contents(void)
|
|||
omap2_cm_read_mod_reg(WKUP_MOD, CM_CLKSEL);
|
||||
prcm_block_contents.cm_clken_pll =
|
||||
omap2_cm_read_mod_reg(PLL_MOD, CM_CLKEN);
|
||||
/*
|
||||
* As per erratum i671, ROM code does not respect the PER DPLL
|
||||
* programming scheme if CM_AUTOIDLE_PLL..AUTO_PERIPH_DPLL == 1.
|
||||
* Then, in anycase, clear these bits to avoid extra latencies.
|
||||
*/
|
||||
prcm_block_contents.cm_autoidle_pll =
|
||||
omap2_cm_read_mod_reg(PLL_MOD, OMAP3430_CM_AUTOIDLE_PLL);
|
||||
omap2_cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE) &
|
||||
~OMAP3430_AUTO_PERIPH_DPLL_MASK;
|
||||
prcm_block_contents.cm_clksel1_pll =
|
||||
omap2_cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL1_PLL);
|
||||
prcm_block_contents.cm_clksel2_pll =
|
||||
|
|
|
|||
|
|
@ -1639,6 +1639,7 @@ static struct omap_hwmod_ocp_if *omap2420_gpio1_slaves[] = {
|
|||
|
||||
static struct omap_hwmod omap2420_gpio1_hwmod = {
|
||||
.name = "gpio1",
|
||||
.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
|
||||
.mpu_irqs = omap242x_gpio1_irqs,
|
||||
.mpu_irqs_cnt = ARRAY_SIZE(omap242x_gpio1_irqs),
|
||||
.main_clk = "gpios_fck",
|
||||
|
|
@ -1669,6 +1670,7 @@ static struct omap_hwmod_ocp_if *omap2420_gpio2_slaves[] = {
|
|||
|
||||
static struct omap_hwmod omap2420_gpio2_hwmod = {
|
||||
.name = "gpio2",
|
||||
.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
|
||||
.mpu_irqs = omap242x_gpio2_irqs,
|
||||
.mpu_irqs_cnt = ARRAY_SIZE(omap242x_gpio2_irqs),
|
||||
.main_clk = "gpios_fck",
|
||||
|
|
@ -1699,6 +1701,7 @@ static struct omap_hwmod_ocp_if *omap2420_gpio3_slaves[] = {
|
|||
|
||||
static struct omap_hwmod omap2420_gpio3_hwmod = {
|
||||
.name = "gpio3",
|
||||
.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
|
||||
.mpu_irqs = omap242x_gpio3_irqs,
|
||||
.mpu_irqs_cnt = ARRAY_SIZE(omap242x_gpio3_irqs),
|
||||
.main_clk = "gpios_fck",
|
||||
|
|
@ -1729,6 +1732,7 @@ static struct omap_hwmod_ocp_if *omap2420_gpio4_slaves[] = {
|
|||
|
||||
static struct omap_hwmod omap2420_gpio4_hwmod = {
|
||||
.name = "gpio4",
|
||||
.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
|
||||
.mpu_irqs = omap242x_gpio4_irqs,
|
||||
.mpu_irqs_cnt = ARRAY_SIZE(omap242x_gpio4_irqs),
|
||||
.main_clk = "gpios_fck",
|
||||
|
|
@ -1782,7 +1786,7 @@ static struct omap_hwmod_irq_info omap2420_dma_system_irqs[] = {
|
|||
static struct omap_hwmod_addr_space omap2420_dma_system_addrs[] = {
|
||||
{
|
||||
.pa_start = 0x48056000,
|
||||
.pa_end = 0x4a0560ff,
|
||||
.pa_end = 0x48056fff,
|
||||
.flags = ADDR_TYPE_RT
|
||||
},
|
||||
};
|
||||
|
|
|
|||
|
|
@ -1742,6 +1742,7 @@ static struct omap_hwmod_ocp_if *omap2430_gpio1_slaves[] = {
|
|||
|
||||
static struct omap_hwmod omap2430_gpio1_hwmod = {
|
||||
.name = "gpio1",
|
||||
.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
|
||||
.mpu_irqs = omap243x_gpio1_irqs,
|
||||
.mpu_irqs_cnt = ARRAY_SIZE(omap243x_gpio1_irqs),
|
||||
.main_clk = "gpios_fck",
|
||||
|
|
@ -1772,6 +1773,7 @@ static struct omap_hwmod_ocp_if *omap2430_gpio2_slaves[] = {
|
|||
|
||||
static struct omap_hwmod omap2430_gpio2_hwmod = {
|
||||
.name = "gpio2",
|
||||
.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
|
||||
.mpu_irqs = omap243x_gpio2_irqs,
|
||||
.mpu_irqs_cnt = ARRAY_SIZE(omap243x_gpio2_irqs),
|
||||
.main_clk = "gpios_fck",
|
||||
|
|
@ -1802,6 +1804,7 @@ static struct omap_hwmod_ocp_if *omap2430_gpio3_slaves[] = {
|
|||
|
||||
static struct omap_hwmod omap2430_gpio3_hwmod = {
|
||||
.name = "gpio3",
|
||||
.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
|
||||
.mpu_irqs = omap243x_gpio3_irqs,
|
||||
.mpu_irqs_cnt = ARRAY_SIZE(omap243x_gpio3_irqs),
|
||||
.main_clk = "gpios_fck",
|
||||
|
|
@ -1832,6 +1835,7 @@ static struct omap_hwmod_ocp_if *omap2430_gpio4_slaves[] = {
|
|||
|
||||
static struct omap_hwmod omap2430_gpio4_hwmod = {
|
||||
.name = "gpio4",
|
||||
.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
|
||||
.mpu_irqs = omap243x_gpio4_irqs,
|
||||
.mpu_irqs_cnt = ARRAY_SIZE(omap243x_gpio4_irqs),
|
||||
.main_clk = "gpios_fck",
|
||||
|
|
@ -1862,6 +1866,7 @@ static struct omap_hwmod_ocp_if *omap2430_gpio5_slaves[] = {
|
|||
|
||||
static struct omap_hwmod omap2430_gpio5_hwmod = {
|
||||
.name = "gpio5",
|
||||
.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
|
||||
.mpu_irqs = omap243x_gpio5_irqs,
|
||||
.mpu_irqs_cnt = ARRAY_SIZE(omap243x_gpio5_irqs),
|
||||
.main_clk = "gpio5_fck",
|
||||
|
|
@ -1915,7 +1920,7 @@ static struct omap_hwmod_irq_info omap2430_dma_system_irqs[] = {
|
|||
static struct omap_hwmod_addr_space omap2430_dma_system_addrs[] = {
|
||||
{
|
||||
.pa_start = 0x48056000,
|
||||
.pa_end = 0x4a0560ff,
|
||||
.pa_end = 0x48056fff,
|
||||
.flags = ADDR_TYPE_RT
|
||||
},
|
||||
};
|
||||
|
|
|
|||
|
|
@ -2141,6 +2141,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_gpio1_slaves[] = {
|
|||
|
||||
static struct omap_hwmod omap3xxx_gpio1_hwmod = {
|
||||
.name = "gpio1",
|
||||
.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
|
||||
.mpu_irqs = omap3xxx_gpio1_irqs,
|
||||
.mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_gpio1_irqs),
|
||||
.main_clk = "gpio1_ick",
|
||||
|
|
@ -2177,6 +2178,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_gpio2_slaves[] = {
|
|||
|
||||
static struct omap_hwmod omap3xxx_gpio2_hwmod = {
|
||||
.name = "gpio2",
|
||||
.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
|
||||
.mpu_irqs = omap3xxx_gpio2_irqs,
|
||||
.mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_gpio2_irqs),
|
||||
.main_clk = "gpio2_ick",
|
||||
|
|
@ -2213,6 +2215,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_gpio3_slaves[] = {
|
|||
|
||||
static struct omap_hwmod omap3xxx_gpio3_hwmod = {
|
||||
.name = "gpio3",
|
||||
.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
|
||||
.mpu_irqs = omap3xxx_gpio3_irqs,
|
||||
.mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_gpio3_irqs),
|
||||
.main_clk = "gpio3_ick",
|
||||
|
|
@ -2249,6 +2252,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_gpio4_slaves[] = {
|
|||
|
||||
static struct omap_hwmod omap3xxx_gpio4_hwmod = {
|
||||
.name = "gpio4",
|
||||
.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
|
||||
.mpu_irqs = omap3xxx_gpio4_irqs,
|
||||
.mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_gpio4_irqs),
|
||||
.main_clk = "gpio4_ick",
|
||||
|
|
@ -2285,6 +2289,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_gpio5_slaves[] = {
|
|||
|
||||
static struct omap_hwmod omap3xxx_gpio5_hwmod = {
|
||||
.name = "gpio5",
|
||||
.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
|
||||
.mpu_irqs = omap3xxx_gpio5_irqs,
|
||||
.mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_gpio5_irqs),
|
||||
.main_clk = "gpio5_ick",
|
||||
|
|
@ -2321,6 +2326,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_gpio6_slaves[] = {
|
|||
|
||||
static struct omap_hwmod omap3xxx_gpio6_hwmod = {
|
||||
.name = "gpio6",
|
||||
.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
|
||||
.mpu_irqs = omap3xxx_gpio6_irqs,
|
||||
.mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_gpio6_irqs),
|
||||
.main_clk = "gpio6_ick",
|
||||
|
|
@ -2386,7 +2392,7 @@ static struct omap_hwmod_irq_info omap3xxx_dma_system_irqs[] = {
|
|||
static struct omap_hwmod_addr_space omap3xxx_dma_system_addrs[] = {
|
||||
{
|
||||
.pa_start = 0x48056000,
|
||||
.pa_end = 0x4a0560ff,
|
||||
.pa_end = 0x48056fff,
|
||||
.flags = ADDR_TYPE_RT
|
||||
},
|
||||
};
|
||||
|
|
|
|||
|
|
@ -885,7 +885,7 @@ static struct omap_hwmod_ocp_if *omap44xx_dma_system_masters[] = {
|
|||
static struct omap_hwmod_addr_space omap44xx_dma_system_addrs[] = {
|
||||
{
|
||||
.pa_start = 0x4a056000,
|
||||
.pa_end = 0x4a0560ff,
|
||||
.pa_end = 0x4a056fff,
|
||||
.flags = ADDR_TYPE_RT
|
||||
},
|
||||
};
|
||||
|
|
|
|||
|
|
@ -196,11 +196,11 @@ static irqreturn_t omap3_l3_app_irq(int irq, void *_l3)
|
|||
/* No timeout error for debug sources */
|
||||
}
|
||||
|
||||
base = ((l3->rt) + (*(omap3_l3_bases[int_type] + err_source)));
|
||||
|
||||
/* identify the error source */
|
||||
for (err_source = 0; !(status & (1 << err_source)); err_source++)
|
||||
;
|
||||
|
||||
base = l3->rt + *(omap3_l3_bases[int_type] + err_source);
|
||||
error = omap3_l3_readll(base, L3_ERROR_LOG);
|
||||
|
||||
if (error) {
|
||||
|
|
|
|||
|
|
@ -89,6 +89,7 @@ static void omap2_init_processor_devices(void)
|
|||
if (cpu_is_omap44xx()) {
|
||||
_init_omap_device("l3_main_1", &l3_dev);
|
||||
_init_omap_device("dsp", &dsp_dev);
|
||||
_init_omap_device("iva", &iva_dev);
|
||||
} else {
|
||||
_init_omap_device("l3_main", &l3_dev);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -114,7 +114,6 @@ static int __init _config_common_vdd_data(struct omap_vdd_info *vdd)
|
|||
sys_clk_speed /= 1000;
|
||||
|
||||
/* Generic voltage parameters */
|
||||
vdd->curr_volt = 1200000;
|
||||
vdd->volt_scale = vp_forceupdate_scale_voltage;
|
||||
vdd->vp_enabled = false;
|
||||
|
||||
|
|
|
|||
|
|
@ -711,7 +711,7 @@ static struct regulator_consumer_supply bq24022_consumers[] = {
|
|||
static struct regulator_init_data bq24022_init_data = {
|
||||
.constraints = {
|
||||
.max_uA = 500000,
|
||||
.valid_ops_mask = REGULATOR_CHANGE_CURRENT,
|
||||
.valid_ops_mask = REGULATOR_CHANGE_CURRENT|REGULATOR_CHANGE_STATUS,
|
||||
},
|
||||
.num_consumer_supplies = ARRAY_SIZE(bq24022_consumers),
|
||||
.consumer_supplies = bq24022_consumers,
|
||||
|
|
|
|||
|
|
@ -599,7 +599,7 @@ static struct regulator_consumer_supply bq24022_consumers[] = {
|
|||
static struct regulator_init_data bq24022_init_data = {
|
||||
.constraints = {
|
||||
.max_uA = 500000,
|
||||
.valid_ops_mask = REGULATOR_CHANGE_CURRENT,
|
||||
.valid_ops_mask = REGULATOR_CHANGE_CURRENT | REGULATOR_CHANGE_STATUS,
|
||||
},
|
||||
.num_consumer_supplies = ARRAY_SIZE(bq24022_consumers),
|
||||
.consumer_supplies = bq24022_consumers,
|
||||
|
|
|
|||
|
|
@ -409,6 +409,10 @@ struct platform_device s3c24xx_pwm_device = {
|
|||
.num_resources = 0,
|
||||
};
|
||||
|
||||
static struct platform_device gta02_dfbmcs320_device = {
|
||||
.name = "dfbmcs320",
|
||||
};
|
||||
|
||||
static struct i2c_board_info gta02_i2c_devs[] __initdata = {
|
||||
{
|
||||
I2C_BOARD_INFO("pcf50633", 0x73),
|
||||
|
|
@ -523,6 +527,7 @@ static struct platform_device *gta02_devices[] __initdata = {
|
|||
&s3c_device_iis,
|
||||
&samsung_asoc_dma,
|
||||
&s3c_device_i2c0,
|
||||
>a02_dfbmcs320_device,
|
||||
>a02_buttons_device,
|
||||
&s3c_device_adc,
|
||||
&s3c_device_ts,
|
||||
|
|
|
|||
|
|
@ -178,16 +178,15 @@ static struct i2c_board_info __initdata mop500_i2c0_devices[] = {
|
|||
.irq = NOMADIK_GPIO_TO_IRQ(217),
|
||||
.platform_data = &mop500_tc35892_data,
|
||||
},
|
||||
};
|
||||
|
||||
/* I2C0 devices only available prior to HREFv60 */
|
||||
static struct i2c_board_info __initdata mop500_i2c0_old_devices[] = {
|
||||
/* I2C0 devices only available prior to HREFv60 */
|
||||
{
|
||||
I2C_BOARD_INFO("tps61052", 0x33),
|
||||
.platform_data = &mop500_tps61052_data,
|
||||
},
|
||||
};
|
||||
|
||||
#define NUM_PRE_V60_I2C0_DEVICES 1
|
||||
|
||||
static struct i2c_board_info __initdata mop500_i2c2_devices[] = {
|
||||
{
|
||||
/* lp5521 LED driver, 1st device */
|
||||
|
|
@ -425,6 +424,8 @@ static void __init mop500_uart_init(void)
|
|||
|
||||
static void __init mop500_init_machine(void)
|
||||
{
|
||||
int i2c0_devs;
|
||||
|
||||
/*
|
||||
* The HREFv60 board removed a GPIO expander and routed
|
||||
* all these GPIO pins to the internal GPIO controller
|
||||
|
|
@ -448,11 +449,11 @@ static void __init mop500_init_machine(void)
|
|||
|
||||
platform_device_register(&ab8500_device);
|
||||
|
||||
i2c_register_board_info(0, mop500_i2c0_devices,
|
||||
ARRAY_SIZE(mop500_i2c0_devices));
|
||||
if (!machine_is_hrefv60())
|
||||
i2c_register_board_info(0, mop500_i2c0_old_devices,
|
||||
ARRAY_SIZE(mop500_i2c0_old_devices));
|
||||
i2c0_devs = ARRAY_SIZE(mop500_i2c0_devices);
|
||||
if (machine_is_hrefv60())
|
||||
i2c0_devs -= NUM_PRE_V60_I2C0_DEVICES;
|
||||
|
||||
i2c_register_board_info(0, mop500_i2c0_devices, i2c0_devs);
|
||||
i2c_register_board_info(2, mop500_i2c2_devices,
|
||||
ARRAY_SIZE(mop500_i2c2_devices));
|
||||
}
|
||||
|
|
|
|||
|
|
@ -395,7 +395,7 @@ ENTRY(xscale_dma_a0_map_area)
|
|||
teq r2, #DMA_TO_DEVICE
|
||||
beq xscale_dma_clean_range
|
||||
b xscale_dma_flush_range
|
||||
ENDPROC(xscsale_dma_a0_map_area)
|
||||
ENDPROC(xscale_dma_a0_map_area)
|
||||
|
||||
/*
|
||||
* dma_unmap_area(start, size, dir)
|
||||
|
|
|
|||
|
|
@ -295,6 +295,12 @@ static int mxc_gpio_direction_output(struct gpio_chip *chip,
|
|||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* This lock class tells lockdep that GPIO irqs are in a different
|
||||
* category than their parents, so it won't report false recursion.
|
||||
*/
|
||||
static struct lock_class_key gpio_lock_class;
|
||||
|
||||
int __init mxc_gpio_init(struct mxc_gpio_port *port, int cnt)
|
||||
{
|
||||
int i, j;
|
||||
|
|
@ -311,6 +317,7 @@ int __init mxc_gpio_init(struct mxc_gpio_port *port, int cnt)
|
|||
__raw_writel(~0, port[i].base + GPIO_ISR);
|
||||
for (j = port[i].virtual_irq_start;
|
||||
j < port[i].virtual_irq_start + 32; j++) {
|
||||
irq_set_lockdep_class(j, &gpio_lock_class);
|
||||
irq_set_chip_and_handler(j, &gpio_irq_chip,
|
||||
handle_level_irq);
|
||||
set_irq_flags(j, IRQF_VALID);
|
||||
|
|
|
|||
|
|
@ -124,6 +124,8 @@ imx_ssi_fiq_start:
|
|||
1:
|
||||
@ return from FIQ
|
||||
subs pc, lr, #4
|
||||
|
||||
.align
|
||||
imx_ssi_fiq_base:
|
||||
.word 0x0
|
||||
imx_ssi_fiq_rx_buffer:
|
||||
|
|
|
|||
|
|
@ -300,6 +300,8 @@ void __init paging_init(void)
|
|||
zones_size[ZONE_DMA] = m68k_memory[i].size >> PAGE_SHIFT;
|
||||
free_area_init_node(i, zones_size,
|
||||
m68k_memory[i].addr >> PAGE_SHIFT, NULL);
|
||||
if (node_present_pages(i))
|
||||
node_set_state(i, N_NORMAL_MEMORY);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -266,8 +266,10 @@ static void __init setup_bootmem(void)
|
|||
}
|
||||
memset(pfnnid_map, 0xff, sizeof(pfnnid_map));
|
||||
|
||||
for (i = 0; i < npmem_ranges; i++)
|
||||
for (i = 0; i < npmem_ranges; i++) {
|
||||
node_set_state(i, N_NORMAL_MEMORY);
|
||||
node_set_online(i);
|
||||
}
|
||||
#endif
|
||||
|
||||
/*
|
||||
|
|
|
|||
|
|
@ -393,8 +393,8 @@ typedef struct fec {
|
|||
uint fec_addr_low; /* lower 32 bits of station address */
|
||||
ushort fec_addr_high; /* upper 16 bits of station address */
|
||||
ushort res1; /* reserved */
|
||||
uint fec_hash_table_high; /* upper 32-bits of hash table */
|
||||
uint fec_hash_table_low; /* lower 32-bits of hash table */
|
||||
uint fec_grp_hash_table_high; /* upper 32-bits of hash table */
|
||||
uint fec_grp_hash_table_low; /* lower 32-bits of hash table */
|
||||
uint fec_r_des_start; /* beginning of Rx descriptor ring */
|
||||
uint fec_x_des_start; /* beginning of Tx descriptor ring */
|
||||
uint fec_r_buff_size; /* Rx buffer size */
|
||||
|
|
|
|||
|
|
@ -60,7 +60,7 @@
|
|||
*
|
||||
* Obviously, the GART is not cache coherent and so any change to it
|
||||
* must be flushed to memory (or maybe just make the GART space non
|
||||
* cachable). AGP memory itself does't seem to be cache coherent neither.
|
||||
* cachable). AGP memory itself doesn't seem to be cache coherent neither.
|
||||
*
|
||||
* In order to invalidate the GART (which is probably necessary to inval
|
||||
* the bridge internal TLBs), the following sequence has to be written,
|
||||
|
|
|
|||
|
|
@ -933,12 +933,16 @@ int ptrace_set_debugreg(struct task_struct *task, unsigned long addr,
|
|||
if (data && !(data & DABR_TRANSLATION))
|
||||
return -EIO;
|
||||
#ifdef CONFIG_HAVE_HW_BREAKPOINT
|
||||
if (ptrace_get_breakpoints(task) < 0)
|
||||
return -ESRCH;
|
||||
|
||||
bp = thread->ptrace_bps[0];
|
||||
if ((!data) || !(data & (DABR_DATA_WRITE | DABR_DATA_READ))) {
|
||||
if (bp) {
|
||||
unregister_hw_breakpoint(bp);
|
||||
thread->ptrace_bps[0] = NULL;
|
||||
}
|
||||
ptrace_put_breakpoints(task);
|
||||
return 0;
|
||||
}
|
||||
if (bp) {
|
||||
|
|
@ -948,9 +952,12 @@ int ptrace_set_debugreg(struct task_struct *task, unsigned long addr,
|
|||
(DABR_DATA_WRITE | DABR_DATA_READ),
|
||||
&attr.bp_type);
|
||||
ret = modify_user_hw_breakpoint(bp, &attr);
|
||||
if (ret)
|
||||
if (ret) {
|
||||
ptrace_put_breakpoints(task);
|
||||
return ret;
|
||||
}
|
||||
thread->ptrace_bps[0] = bp;
|
||||
ptrace_put_breakpoints(task);
|
||||
thread->dabr = data;
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -965,9 +972,12 @@ int ptrace_set_debugreg(struct task_struct *task, unsigned long addr,
|
|||
ptrace_triggered, task);
|
||||
if (IS_ERR(bp)) {
|
||||
thread->ptrace_bps[0] = NULL;
|
||||
ptrace_put_breakpoints(task);
|
||||
return PTR_ERR(bp);
|
||||
}
|
||||
|
||||
ptrace_put_breakpoints(task);
|
||||
|
||||
#endif /* CONFIG_HAVE_HW_BREAKPOINT */
|
||||
|
||||
/* Move contents to the DABR register */
|
||||
|
|
|
|||
|
|
@ -76,7 +76,7 @@ static void prng_seed(int nbytes)
|
|||
|
||||
/* Add the entropy */
|
||||
while (nbytes >= 8) {
|
||||
*((__u64 *)parm_block) ^= *((__u64 *)buf+i*8);
|
||||
*((__u64 *)parm_block) ^= *((__u64 *)(buf+i));
|
||||
prng_add_entropy();
|
||||
i += 8;
|
||||
nbytes -= 8;
|
||||
|
|
|
|||
|
|
@ -48,10 +48,10 @@ sie_irq_handler:
|
|||
tm __TI_flags+7(%r2),_TIF_EXIT_SIE
|
||||
jz 0f
|
||||
larl %r2,sie_exit # work pending, leave sie
|
||||
stg %r2,__LC_RETURN_PSW+8
|
||||
stg %r2,SPI_PSW+8(0,%r15)
|
||||
br %r14
|
||||
0: larl %r2,sie_reenter # re-enter with guest id
|
||||
stg %r2,__LC_RETURN_PSW+8
|
||||
stg %r2,SPI_PSW+8(0,%r15)
|
||||
1: br %r14
|
||||
|
||||
/*
|
||||
|
|
|
|||
|
|
@ -543,7 +543,6 @@ static void pfault_interrupt(unsigned int ext_int_code,
|
|||
struct task_struct *tsk;
|
||||
__u16 subcode;
|
||||
|
||||
kstat_cpu(smp_processor_id()).irqs[EXTINT_PFL]++;
|
||||
/*
|
||||
* Get the external interruption subcode & pfault
|
||||
* initial/completion signal bit. VM stores this
|
||||
|
|
@ -553,14 +552,15 @@ static void pfault_interrupt(unsigned int ext_int_code,
|
|||
subcode = ext_int_code >> 16;
|
||||
if ((subcode & 0xff00) != __SUBCODE_MASK)
|
||||
return;
|
||||
kstat_cpu(smp_processor_id()).irqs[EXTINT_PFL]++;
|
||||
|
||||
/*
|
||||
* Get the token (= address of the task structure of the affected task).
|
||||
*/
|
||||
#ifdef CONFIG_64BIT
|
||||
tsk = *(struct task_struct **) param64;
|
||||
tsk = (struct task_struct *) param64;
|
||||
#else
|
||||
tsk = *(struct task_struct **) param32;
|
||||
tsk = (struct task_struct *) param32;
|
||||
#endif
|
||||
|
||||
if (subcode & 0x0080) {
|
||||
|
|
|
|||
|
|
@ -24,12 +24,13 @@ static void change_page_attr(unsigned long addr, int numpages,
|
|||
WARN_ON_ONCE(1);
|
||||
continue;
|
||||
}
|
||||
ptep = pte_offset_kernel(pmdp, addr + i * PAGE_SIZE);
|
||||
ptep = pte_offset_kernel(pmdp, addr);
|
||||
|
||||
pte = *ptep;
|
||||
pte = set(pte);
|
||||
ptep_invalidate(&init_mm, addr + i * PAGE_SIZE, ptep);
|
||||
ptep_invalidate(&init_mm, addr, ptep);
|
||||
*ptep = pte;
|
||||
addr += PAGE_SIZE;
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -117,7 +117,11 @@ void user_enable_single_step(struct task_struct *child)
|
|||
|
||||
set_tsk_thread_flag(child, TIF_SINGLESTEP);
|
||||
|
||||
if (ptrace_get_breakpoints(child) < 0)
|
||||
return;
|
||||
|
||||
set_single_step(child, pc);
|
||||
ptrace_put_breakpoints(child);
|
||||
}
|
||||
|
||||
void user_disable_single_step(struct task_struct *child)
|
||||
|
|
|
|||
|
|
@ -47,7 +47,7 @@ config HOSTFS
|
|||
|
||||
config HPPFS
|
||||
tristate "HoneyPot ProcFS (EXPERIMENTAL)"
|
||||
depends on EXPERIMENTAL
|
||||
depends on EXPERIMENTAL && PROC_FS
|
||||
help
|
||||
hppfs (HoneyPot ProcFS) is a filesystem which allows UML /proc
|
||||
entries to be overridden, removed, or fabricated from the host.
|
||||
|
|
|
|||
|
|
@ -49,7 +49,10 @@ static inline struct thread_info *current_thread_info(void)
|
|||
{
|
||||
struct thread_info *ti;
|
||||
unsigned long mask = THREAD_SIZE - 1;
|
||||
ti = (struct thread_info *) (((unsigned long) &ti) & ~mask);
|
||||
void *p;
|
||||
|
||||
asm volatile ("" : "=r" (p) : "0" (&ti));
|
||||
ti = (struct thread_info *) (((unsigned long)p) & ~mask);
|
||||
return ti;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@
|
|||
|
||||
obj-y = bug.o bugs.o checksum.o delay.o fault.o ksyms.o ldt.o ptrace.o \
|
||||
ptrace_user.o setjmp.o signal.o stub.o stub_segv.o syscalls.o sysrq.o \
|
||||
sys_call_table.o tls.o
|
||||
sys_call_table.o tls.o atomic64_cx8_32.o
|
||||
|
||||
obj-$(CONFIG_BINFMT_ELF) += elfcore.o
|
||||
|
||||
|
|
|
|||
|
|
@ -0,0 +1,225 @@
|
|||
/*
|
||||
* atomic64_t for 586+
|
||||
*
|
||||
* Copied from arch/x86/lib/atomic64_cx8_32.S
|
||||
*
|
||||
* Copyright © 2010 Luca Barbieri
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
*/
|
||||
|
||||
#include <linux/linkage.h>
|
||||
#include <asm/alternative-asm.h>
|
||||
#include <asm/dwarf2.h>
|
||||
|
||||
.macro SAVE reg
|
||||
pushl_cfi %\reg
|
||||
CFI_REL_OFFSET \reg, 0
|
||||
.endm
|
||||
|
||||
.macro RESTORE reg
|
||||
popl_cfi %\reg
|
||||
CFI_RESTORE \reg
|
||||
.endm
|
||||
|
||||
.macro read64 reg
|
||||
movl %ebx, %eax
|
||||
movl %ecx, %edx
|
||||
/* we need LOCK_PREFIX since otherwise cmpxchg8b always does the write */
|
||||
LOCK_PREFIX
|
||||
cmpxchg8b (\reg)
|
||||
.endm
|
||||
|
||||
ENTRY(atomic64_read_cx8)
|
||||
CFI_STARTPROC
|
||||
|
||||
read64 %ecx
|
||||
ret
|
||||
CFI_ENDPROC
|
||||
ENDPROC(atomic64_read_cx8)
|
||||
|
||||
ENTRY(atomic64_set_cx8)
|
||||
CFI_STARTPROC
|
||||
|
||||
1:
|
||||
/* we don't need LOCK_PREFIX since aligned 64-bit writes
|
||||
* are atomic on 586 and newer */
|
||||
cmpxchg8b (%esi)
|
||||
jne 1b
|
||||
|
||||
ret
|
||||
CFI_ENDPROC
|
||||
ENDPROC(atomic64_set_cx8)
|
||||
|
||||
ENTRY(atomic64_xchg_cx8)
|
||||
CFI_STARTPROC
|
||||
|
||||
movl %ebx, %eax
|
||||
movl %ecx, %edx
|
||||
1:
|
||||
LOCK_PREFIX
|
||||
cmpxchg8b (%esi)
|
||||
jne 1b
|
||||
|
||||
ret
|
||||
CFI_ENDPROC
|
||||
ENDPROC(atomic64_xchg_cx8)
|
||||
|
||||
.macro addsub_return func ins insc
|
||||
ENTRY(atomic64_\func\()_return_cx8)
|
||||
CFI_STARTPROC
|
||||
SAVE ebp
|
||||
SAVE ebx
|
||||
SAVE esi
|
||||
SAVE edi
|
||||
|
||||
movl %eax, %esi
|
||||
movl %edx, %edi
|
||||
movl %ecx, %ebp
|
||||
|
||||
read64 %ebp
|
||||
1:
|
||||
movl %eax, %ebx
|
||||
movl %edx, %ecx
|
||||
\ins\()l %esi, %ebx
|
||||
\insc\()l %edi, %ecx
|
||||
LOCK_PREFIX
|
||||
cmpxchg8b (%ebp)
|
||||
jne 1b
|
||||
|
||||
10:
|
||||
movl %ebx, %eax
|
||||
movl %ecx, %edx
|
||||
RESTORE edi
|
||||
RESTORE esi
|
||||
RESTORE ebx
|
||||
RESTORE ebp
|
||||
ret
|
||||
CFI_ENDPROC
|
||||
ENDPROC(atomic64_\func\()_return_cx8)
|
||||
.endm
|
||||
|
||||
addsub_return add add adc
|
||||
addsub_return sub sub sbb
|
||||
|
||||
.macro incdec_return func ins insc
|
||||
ENTRY(atomic64_\func\()_return_cx8)
|
||||
CFI_STARTPROC
|
||||
SAVE ebx
|
||||
|
||||
read64 %esi
|
||||
1:
|
||||
movl %eax, %ebx
|
||||
movl %edx, %ecx
|
||||
\ins\()l $1, %ebx
|
||||
\insc\()l $0, %ecx
|
||||
LOCK_PREFIX
|
||||
cmpxchg8b (%esi)
|
||||
jne 1b
|
||||
|
||||
10:
|
||||
movl %ebx, %eax
|
||||
movl %ecx, %edx
|
||||
RESTORE ebx
|
||||
ret
|
||||
CFI_ENDPROC
|
||||
ENDPROC(atomic64_\func\()_return_cx8)
|
||||
.endm
|
||||
|
||||
incdec_return inc add adc
|
||||
incdec_return dec sub sbb
|
||||
|
||||
ENTRY(atomic64_dec_if_positive_cx8)
|
||||
CFI_STARTPROC
|
||||
SAVE ebx
|
||||
|
||||
read64 %esi
|
||||
1:
|
||||
movl %eax, %ebx
|
||||
movl %edx, %ecx
|
||||
subl $1, %ebx
|
||||
sbb $0, %ecx
|
||||
js 2f
|
||||
LOCK_PREFIX
|
||||
cmpxchg8b (%esi)
|
||||
jne 1b
|
||||
|
||||
2:
|
||||
movl %ebx, %eax
|
||||
movl %ecx, %edx
|
||||
RESTORE ebx
|
||||
ret
|
||||
CFI_ENDPROC
|
||||
ENDPROC(atomic64_dec_if_positive_cx8)
|
||||
|
||||
ENTRY(atomic64_add_unless_cx8)
|
||||
CFI_STARTPROC
|
||||
SAVE ebp
|
||||
SAVE ebx
|
||||
/* these just push these two parameters on the stack */
|
||||
SAVE edi
|
||||
SAVE esi
|
||||
|
||||
movl %ecx, %ebp
|
||||
movl %eax, %esi
|
||||
movl %edx, %edi
|
||||
|
||||
read64 %ebp
|
||||
1:
|
||||
cmpl %eax, 0(%esp)
|
||||
je 4f
|
||||
2:
|
||||
movl %eax, %ebx
|
||||
movl %edx, %ecx
|
||||
addl %esi, %ebx
|
||||
adcl %edi, %ecx
|
||||
LOCK_PREFIX
|
||||
cmpxchg8b (%ebp)
|
||||
jne 1b
|
||||
|
||||
movl $1, %eax
|
||||
3:
|
||||
addl $8, %esp
|
||||
CFI_ADJUST_CFA_OFFSET -8
|
||||
RESTORE ebx
|
||||
RESTORE ebp
|
||||
ret
|
||||
4:
|
||||
cmpl %edx, 4(%esp)
|
||||
jne 2b
|
||||
xorl %eax, %eax
|
||||
jmp 3b
|
||||
CFI_ENDPROC
|
||||
ENDPROC(atomic64_add_unless_cx8)
|
||||
|
||||
ENTRY(atomic64_inc_not_zero_cx8)
|
||||
CFI_STARTPROC
|
||||
SAVE ebx
|
||||
|
||||
read64 %esi
|
||||
1:
|
||||
testl %eax, %eax
|
||||
je 4f
|
||||
2:
|
||||
movl %eax, %ebx
|
||||
movl %edx, %ecx
|
||||
addl $1, %ebx
|
||||
adcl $0, %ecx
|
||||
LOCK_PREFIX
|
||||
cmpxchg8b (%esi)
|
||||
jne 1b
|
||||
|
||||
movl $1, %eax
|
||||
3:
|
||||
RESTORE ebx
|
||||
ret
|
||||
4:
|
||||
testl %edx, %edx
|
||||
jne 2b
|
||||
jmp 3b
|
||||
CFI_ENDPROC
|
||||
ENDPROC(atomic64_inc_not_zero_cx8)
|
||||
|
|
@ -91,7 +91,7 @@ static int detect_memory_e801(void)
|
|||
if (oreg.ax > 15*1024) {
|
||||
return -1; /* Bogus! */
|
||||
} else if (oreg.ax == 15*1024) {
|
||||
boot_params.alt_mem_k = (oreg.dx << 6) + oreg.ax;
|
||||
boot_params.alt_mem_k = (oreg.bx << 6) + oreg.ax;
|
||||
} else {
|
||||
/*
|
||||
* This ignores memory above 16MB if we have a memory
|
||||
|
|
|
|||
|
|
@ -66,7 +66,7 @@ static inline void gart_set_size_and_enable(struct pci_dev *dev, u32 order)
|
|||
* Don't enable translation but enable GART IO and CPU accesses.
|
||||
* Also, set DISTLBWALKPRB since GART tables memory is UC.
|
||||
*/
|
||||
ctl = DISTLBWALKPRB | order << 1;
|
||||
ctl = order << 1;
|
||||
|
||||
pci_write_config_dword(dev, AMD64_GARTAPERTURECTL, ctl);
|
||||
}
|
||||
|
|
@ -83,7 +83,7 @@ static inline void enable_gart_translation(struct pci_dev *dev, u64 addr)
|
|||
|
||||
/* Enable GART translation for this hammer. */
|
||||
pci_read_config_dword(dev, AMD64_GARTAPERTURECTL, &ctl);
|
||||
ctl |= GARTEN;
|
||||
ctl |= GARTEN | DISTLBWALKPRB;
|
||||
ctl &= ~(DISGARTCPU | DISGARTIO);
|
||||
pci_write_config_dword(dev, AMD64_GARTAPERTURECTL, ctl);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -150,7 +150,7 @@ void setup_IO_APIC_irq_extra(u32 gsi);
|
|||
extern void ioapic_and_gsi_init(void);
|
||||
extern void ioapic_insert_resources(void);
|
||||
|
||||
int io_apic_setup_irq_pin(unsigned int irq, int node, struct io_apic_irq_attr *attr);
|
||||
int io_apic_setup_irq_pin_once(unsigned int irq, int node, struct io_apic_irq_attr *attr);
|
||||
|
||||
extern struct IO_APIC_route_entry **alloc_ioapic_entries(void);
|
||||
extern void free_ioapic_entries(struct IO_APIC_route_entry **ioapic_entries);
|
||||
|
|
|
|||
|
|
@ -51,7 +51,7 @@ static inline void numa_remove_cpu(int cpu) { }
|
|||
#endif /* CONFIG_NUMA */
|
||||
|
||||
#ifdef CONFIG_DEBUG_PER_CPU_MAPS
|
||||
struct cpumask __cpuinit *debug_cpumask_set_cpu(int cpu, int enable);
|
||||
void debug_cpumask_set_cpu(int cpu, int node, bool enable);
|
||||
#endif
|
||||
|
||||
#endif /* _ASM_X86_NUMA_H */
|
||||
|
|
|
|||
|
|
@ -499,7 +499,7 @@ out:
|
|||
* Don't enable translation yet but enable GART IO and CPU
|
||||
* accesses and set DISTLBWALKPRB since GART table memory is UC.
|
||||
*/
|
||||
u32 ctl = DISTLBWALKPRB | aper_order << 1;
|
||||
u32 ctl = aper_order << 1;
|
||||
|
||||
bus = amd_nb_bus_dev_ranges[i].bus;
|
||||
dev_base = amd_nb_bus_dev_ranges[i].dev_base;
|
||||
|
|
|
|||
|
|
@ -128,7 +128,7 @@ static int __init parse_noapic(char *str)
|
|||
}
|
||||
early_param("noapic", parse_noapic);
|
||||
|
||||
static int io_apic_setup_irq_pin_once(unsigned int irq, int node,
|
||||
static int io_apic_setup_irq_pin(unsigned int irq, int node,
|
||||
struct io_apic_irq_attr *attr);
|
||||
|
||||
/* Will be called in mpparse/acpi/sfi codes for saving IRQ info */
|
||||
|
|
@ -3570,7 +3570,7 @@ int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev)
|
|||
}
|
||||
#endif /* CONFIG_HT_IRQ */
|
||||
|
||||
int
|
||||
static int
|
||||
io_apic_setup_irq_pin(unsigned int irq, int node, struct io_apic_irq_attr *attr)
|
||||
{
|
||||
struct irq_cfg *cfg = alloc_irq_and_cfg_at(irq, node);
|
||||
|
|
@ -3585,7 +3585,7 @@ io_apic_setup_irq_pin(unsigned int irq, int node, struct io_apic_irq_attr *attr)
|
|||
return ret;
|
||||
}
|
||||
|
||||
static int io_apic_setup_irq_pin_once(unsigned int irq, int node,
|
||||
int io_apic_setup_irq_pin_once(unsigned int irq, int node,
|
||||
struct io_apic_irq_attr *attr)
|
||||
{
|
||||
unsigned int id = attr->ioapic, pin = attr->ioapic_pin;
|
||||
|
|
|
|||
|
|
@ -228,6 +228,7 @@
|
|||
#include <linux/kthread.h>
|
||||
#include <linux/jiffies.h>
|
||||
#include <linux/acpi.h>
|
||||
#include <linux/syscore_ops.h>
|
||||
|
||||
#include <asm/system.h>
|
||||
#include <asm/uaccess.h>
|
||||
|
|
@ -1238,6 +1239,7 @@ static int suspend(int vetoable)
|
|||
|
||||
local_irq_disable();
|
||||
sysdev_suspend(PMSG_SUSPEND);
|
||||
syscore_suspend();
|
||||
|
||||
local_irq_enable();
|
||||
|
||||
|
|
@ -1255,6 +1257,7 @@ static int suspend(int vetoable)
|
|||
apm_error("suspend", err);
|
||||
err = (err == APM_SUCCESS) ? 0 : -EIO;
|
||||
|
||||
syscore_resume();
|
||||
sysdev_resume();
|
||||
local_irq_enable();
|
||||
|
||||
|
|
@ -1280,6 +1283,7 @@ static void standby(void)
|
|||
|
||||
local_irq_disable();
|
||||
sysdev_suspend(PMSG_SUSPEND);
|
||||
syscore_suspend();
|
||||
local_irq_enable();
|
||||
|
||||
err = set_system_power_state(APM_STATE_STANDBY);
|
||||
|
|
@ -1287,6 +1291,7 @@ static void standby(void)
|
|||
apm_error("standby", err);
|
||||
|
||||
local_irq_disable();
|
||||
syscore_resume();
|
||||
sysdev_resume();
|
||||
local_irq_enable();
|
||||
|
||||
|
|
|
|||
|
|
@ -698,7 +698,7 @@ cpu_dev_register(amd_cpu_dev);
|
|||
*/
|
||||
|
||||
const int amd_erratum_400[] =
|
||||
AMD_OSVW_ERRATUM(1, AMD_MODEL_RANGE(0xf, 0x41, 0x2, 0xff, 0xf),
|
||||
AMD_OSVW_ERRATUM(1, AMD_MODEL_RANGE(0x0f, 0x4, 0x2, 0xff, 0xf),
|
||||
AMD_MODEL_RANGE(0x10, 0x2, 0x1, 0xff, 0xf));
|
||||
EXPORT_SYMBOL_GPL(amd_erratum_400);
|
||||
|
||||
|
|
|
|||
|
|
@ -586,8 +586,12 @@ static int x86_setup_perfctr(struct perf_event *event)
|
|||
return -EOPNOTSUPP;
|
||||
}
|
||||
|
||||
/*
|
||||
* Do not allow config1 (extended registers) to propagate,
|
||||
* there's no sane user-space generalization yet:
|
||||
*/
|
||||
if (attr->type == PERF_TYPE_RAW)
|
||||
return x86_pmu_extra_regs(event->attr.config, event);
|
||||
return 0;
|
||||
|
||||
if (attr->type == PERF_TYPE_HW_CACHE)
|
||||
return set_ext_hw_attr(hwc, event);
|
||||
|
|
@ -609,8 +613,8 @@ static int x86_setup_perfctr(struct perf_event *event)
|
|||
/*
|
||||
* Branch tracing:
|
||||
*/
|
||||
if ((attr->config == PERF_COUNT_HW_BRANCH_INSTRUCTIONS) &&
|
||||
(hwc->sample_period == 1)) {
|
||||
if (attr->config == PERF_COUNT_HW_BRANCH_INSTRUCTIONS &&
|
||||
!attr->freq && hwc->sample_period == 1) {
|
||||
/* BTS is not supported by this architecture. */
|
||||
if (!x86_pmu.bts_active)
|
||||
return -EOPNOTSUPP;
|
||||
|
|
@ -1284,6 +1288,16 @@ static int x86_pmu_handle_irq(struct pt_regs *regs)
|
|||
|
||||
cpuc = &__get_cpu_var(cpu_hw_events);
|
||||
|
||||
/*
|
||||
* Some chipsets need to unmask the LVTPC in a particular spot
|
||||
* inside the nmi handler. As a result, the unmasking was pushed
|
||||
* into all the nmi handlers.
|
||||
*
|
||||
* This generic handler doesn't seem to have any issues where the
|
||||
* unmasking occurs so it was left at the top.
|
||||
*/
|
||||
apic_write(APIC_LVTPC, APIC_DM_NMI);
|
||||
|
||||
for (idx = 0; idx < x86_pmu.num_counters; idx++) {
|
||||
if (!test_bit(idx, cpuc->active_mask)) {
|
||||
/*
|
||||
|
|
@ -1370,8 +1384,6 @@ perf_event_nmi_handler(struct notifier_block *self,
|
|||
return NOTIFY_DONE;
|
||||
}
|
||||
|
||||
apic_write(APIC_LVTPC, APIC_DM_NMI);
|
||||
|
||||
handled = x86_pmu.handle_irq(args->regs);
|
||||
if (!handled)
|
||||
return NOTIFY_DONE;
|
||||
|
|
|
|||
|
|
@ -8,7 +8,7 @@ static __initconst const u64 amd_hw_cache_event_ids
|
|||
[ C(L1D) ] = {
|
||||
[ C(OP_READ) ] = {
|
||||
[ C(RESULT_ACCESS) ] = 0x0040, /* Data Cache Accesses */
|
||||
[ C(RESULT_MISS) ] = 0x0041, /* Data Cache Misses */
|
||||
[ C(RESULT_MISS) ] = 0x0141, /* Data Cache Misses */
|
||||
},
|
||||
[ C(OP_WRITE) ] = {
|
||||
[ C(RESULT_ACCESS) ] = 0x0142, /* Data Cache Refills :system */
|
||||
|
|
@ -427,7 +427,9 @@ static __initconst const struct x86_pmu amd_pmu = {
|
|||
*
|
||||
* Exceptions:
|
||||
*
|
||||
* 0x000 FP PERF_CTL[3], PERF_CTL[5:3] (*)
|
||||
* 0x003 FP PERF_CTL[3]
|
||||
* 0x004 FP PERF_CTL[3], PERF_CTL[5:3] (*)
|
||||
* 0x00B FP PERF_CTL[3]
|
||||
* 0x00D FP PERF_CTL[3]
|
||||
* 0x023 DE PERF_CTL[2:0]
|
||||
|
|
@ -448,6 +450,8 @@ static __initconst const struct x86_pmu amd_pmu = {
|
|||
* 0x0DF LS PERF_CTL[5:0]
|
||||
* 0x1D6 EX PERF_CTL[5:0]
|
||||
* 0x1D8 EX PERF_CTL[5:0]
|
||||
*
|
||||
* (*) depending on the umask all FPU counters may be used
|
||||
*/
|
||||
|
||||
static struct event_constraint amd_f15_PMC0 = EVENT_CONSTRAINT(0, 0x01, 0);
|
||||
|
|
@ -460,18 +464,28 @@ static struct event_constraint amd_f15_PMC53 = EVENT_CONSTRAINT(0, 0x38, 0);
|
|||
static struct event_constraint *
|
||||
amd_get_event_constraints_f15h(struct cpu_hw_events *cpuc, struct perf_event *event)
|
||||
{
|
||||
unsigned int event_code = amd_get_event_code(&event->hw);
|
||||
struct hw_perf_event *hwc = &event->hw;
|
||||
unsigned int event_code = amd_get_event_code(hwc);
|
||||
|
||||
switch (event_code & AMD_EVENT_TYPE_MASK) {
|
||||
case AMD_EVENT_FP:
|
||||
switch (event_code) {
|
||||
case 0x000:
|
||||
if (!(hwc->config & 0x0000F000ULL))
|
||||
break;
|
||||
if (!(hwc->config & 0x00000F00ULL))
|
||||
break;
|
||||
return &amd_f15_PMC3;
|
||||
case 0x004:
|
||||
if (hweight_long(hwc->config & ARCH_PERFMON_EVENTSEL_UMASK) <= 1)
|
||||
break;
|
||||
return &amd_f15_PMC3;
|
||||
case 0x003:
|
||||
case 0x00B:
|
||||
case 0x00D:
|
||||
return &amd_f15_PMC3;
|
||||
default:
|
||||
return &amd_f15_PMC53;
|
||||
}
|
||||
return &amd_f15_PMC53;
|
||||
case AMD_EVENT_LS:
|
||||
case AMD_EVENT_DC:
|
||||
case AMD_EVENT_EX_LS:
|
||||
|
|
|
|||
|
|
@ -25,7 +25,7 @@ struct intel_percore {
|
|||
/*
|
||||
* Intel PerfMon, used on Core and later.
|
||||
*/
|
||||
static const u64 intel_perfmon_event_map[] =
|
||||
static u64 intel_perfmon_event_map[PERF_COUNT_HW_MAX] __read_mostly =
|
||||
{
|
||||
[PERF_COUNT_HW_CPU_CYCLES] = 0x003c,
|
||||
[PERF_COUNT_HW_INSTRUCTIONS] = 0x00c0,
|
||||
|
|
@ -184,26 +184,23 @@ static __initconst const u64 snb_hw_cache_event_ids
|
|||
},
|
||||
},
|
||||
[ C(LL ) ] = {
|
||||
/*
|
||||
* TBD: Need Off-core Response Performance Monitoring support
|
||||
*/
|
||||
[ C(OP_READ) ] = {
|
||||
/* OFFCORE_RESPONSE_0.ANY_DATA.LOCAL_CACHE */
|
||||
/* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
|
||||
[ C(RESULT_ACCESS) ] = 0x01b7,
|
||||
/* OFFCORE_RESPONSE_1.ANY_DATA.ANY_LLC_MISS */
|
||||
[ C(RESULT_MISS) ] = 0x01bb,
|
||||
/* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */
|
||||
[ C(RESULT_MISS) ] = 0x01b7,
|
||||
},
|
||||
[ C(OP_WRITE) ] = {
|
||||
/* OFFCORE_RESPONSE_0.ANY_RFO.LOCAL_CACHE */
|
||||
/* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
|
||||
[ C(RESULT_ACCESS) ] = 0x01b7,
|
||||
/* OFFCORE_RESPONSE_1.ANY_RFO.ANY_LLC_MISS */
|
||||
[ C(RESULT_MISS) ] = 0x01bb,
|
||||
/* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
|
||||
[ C(RESULT_MISS) ] = 0x01b7,
|
||||
},
|
||||
[ C(OP_PREFETCH) ] = {
|
||||
/* OFFCORE_RESPONSE_0.PREFETCH.LOCAL_CACHE */
|
||||
/* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
|
||||
[ C(RESULT_ACCESS) ] = 0x01b7,
|
||||
/* OFFCORE_RESPONSE_1.PREFETCH.ANY_LLC_MISS */
|
||||
[ C(RESULT_MISS) ] = 0x01bb,
|
||||
/* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
|
||||
[ C(RESULT_MISS) ] = 0x01b7,
|
||||
},
|
||||
},
|
||||
[ C(DTLB) ] = {
|
||||
|
|
@ -285,26 +282,26 @@ static __initconst const u64 westmere_hw_cache_event_ids
|
|||
},
|
||||
[ C(LL ) ] = {
|
||||
[ C(OP_READ) ] = {
|
||||
/* OFFCORE_RESPONSE_0.ANY_DATA.LOCAL_CACHE */
|
||||
/* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
|
||||
[ C(RESULT_ACCESS) ] = 0x01b7,
|
||||
/* OFFCORE_RESPONSE_1.ANY_DATA.ANY_LLC_MISS */
|
||||
[ C(RESULT_MISS) ] = 0x01bb,
|
||||
/* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */
|
||||
[ C(RESULT_MISS) ] = 0x01b7,
|
||||
},
|
||||
/*
|
||||
* Use RFO, not WRITEBACK, because a write miss would typically occur
|
||||
* on RFO.
|
||||
*/
|
||||
[ C(OP_WRITE) ] = {
|
||||
/* OFFCORE_RESPONSE_1.ANY_RFO.LOCAL_CACHE */
|
||||
[ C(RESULT_ACCESS) ] = 0x01bb,
|
||||
/* OFFCORE_RESPONSE_0.ANY_RFO.ANY_LLC_MISS */
|
||||
/* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
|
||||
[ C(RESULT_ACCESS) ] = 0x01b7,
|
||||
/* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
|
||||
[ C(RESULT_MISS) ] = 0x01b7,
|
||||
},
|
||||
[ C(OP_PREFETCH) ] = {
|
||||
/* OFFCORE_RESPONSE_0.PREFETCH.LOCAL_CACHE */
|
||||
/* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
|
||||
[ C(RESULT_ACCESS) ] = 0x01b7,
|
||||
/* OFFCORE_RESPONSE_1.PREFETCH.ANY_LLC_MISS */
|
||||
[ C(RESULT_MISS) ] = 0x01bb,
|
||||
/* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
|
||||
[ C(RESULT_MISS) ] = 0x01b7,
|
||||
},
|
||||
},
|
||||
[ C(DTLB) ] = {
|
||||
|
|
@ -352,16 +349,36 @@ static __initconst const u64 westmere_hw_cache_event_ids
|
|||
};
|
||||
|
||||
/*
|
||||
* OFFCORE_RESPONSE MSR bits (subset), See IA32 SDM Vol 3 30.6.1.3
|
||||
* Nehalem/Westmere MSR_OFFCORE_RESPONSE bits;
|
||||
* See IA32 SDM Vol 3B 30.6.1.3
|
||||
*/
|
||||
|
||||
#define DMND_DATA_RD (1 << 0)
|
||||
#define DMND_RFO (1 << 1)
|
||||
#define DMND_WB (1 << 3)
|
||||
#define PF_DATA_RD (1 << 4)
|
||||
#define PF_DATA_RFO (1 << 5)
|
||||
#define RESP_UNCORE_HIT (1 << 8)
|
||||
#define RESP_MISS (0xf600) /* non uncore hit */
|
||||
#define NHM_DMND_DATA_RD (1 << 0)
|
||||
#define NHM_DMND_RFO (1 << 1)
|
||||
#define NHM_DMND_IFETCH (1 << 2)
|
||||
#define NHM_DMND_WB (1 << 3)
|
||||
#define NHM_PF_DATA_RD (1 << 4)
|
||||
#define NHM_PF_DATA_RFO (1 << 5)
|
||||
#define NHM_PF_IFETCH (1 << 6)
|
||||
#define NHM_OFFCORE_OTHER (1 << 7)
|
||||
#define NHM_UNCORE_HIT (1 << 8)
|
||||
#define NHM_OTHER_CORE_HIT_SNP (1 << 9)
|
||||
#define NHM_OTHER_CORE_HITM (1 << 10)
|
||||
/* reserved */
|
||||
#define NHM_REMOTE_CACHE_FWD (1 << 12)
|
||||
#define NHM_REMOTE_DRAM (1 << 13)
|
||||
#define NHM_LOCAL_DRAM (1 << 14)
|
||||
#define NHM_NON_DRAM (1 << 15)
|
||||
|
||||
#define NHM_ALL_DRAM (NHM_REMOTE_DRAM|NHM_LOCAL_DRAM)
|
||||
|
||||
#define NHM_DMND_READ (NHM_DMND_DATA_RD)
|
||||
#define NHM_DMND_WRITE (NHM_DMND_RFO|NHM_DMND_WB)
|
||||
#define NHM_DMND_PREFETCH (NHM_PF_DATA_RD|NHM_PF_DATA_RFO)
|
||||
|
||||
#define NHM_L3_HIT (NHM_UNCORE_HIT|NHM_OTHER_CORE_HIT_SNP|NHM_OTHER_CORE_HITM)
|
||||
#define NHM_L3_MISS (NHM_NON_DRAM|NHM_ALL_DRAM|NHM_REMOTE_CACHE_FWD)
|
||||
#define NHM_L3_ACCESS (NHM_L3_HIT|NHM_L3_MISS)
|
||||
|
||||
static __initconst const u64 nehalem_hw_cache_extra_regs
|
||||
[PERF_COUNT_HW_CACHE_MAX]
|
||||
|
|
@ -370,16 +387,16 @@ static __initconst const u64 nehalem_hw_cache_extra_regs
|
|||
{
|
||||
[ C(LL ) ] = {
|
||||
[ C(OP_READ) ] = {
|
||||
[ C(RESULT_ACCESS) ] = DMND_DATA_RD|RESP_UNCORE_HIT,
|
||||
[ C(RESULT_MISS) ] = DMND_DATA_RD|RESP_MISS,
|
||||
[ C(RESULT_ACCESS) ] = NHM_DMND_READ|NHM_L3_ACCESS,
|
||||
[ C(RESULT_MISS) ] = NHM_DMND_READ|NHM_L3_MISS,
|
||||
},
|
||||
[ C(OP_WRITE) ] = {
|
||||
[ C(RESULT_ACCESS) ] = DMND_RFO|DMND_WB|RESP_UNCORE_HIT,
|
||||
[ C(RESULT_MISS) ] = DMND_RFO|DMND_WB|RESP_MISS,
|
||||
[ C(RESULT_ACCESS) ] = NHM_DMND_WRITE|NHM_L3_ACCESS,
|
||||
[ C(RESULT_MISS) ] = NHM_DMND_WRITE|NHM_L3_MISS,
|
||||
},
|
||||
[ C(OP_PREFETCH) ] = {
|
||||
[ C(RESULT_ACCESS) ] = PF_DATA_RD|PF_DATA_RFO|RESP_UNCORE_HIT,
|
||||
[ C(RESULT_MISS) ] = PF_DATA_RD|PF_DATA_RFO|RESP_MISS,
|
||||
[ C(RESULT_ACCESS) ] = NHM_DMND_PREFETCH|NHM_L3_ACCESS,
|
||||
[ C(RESULT_MISS) ] = NHM_DMND_PREFETCH|NHM_L3_MISS,
|
||||
},
|
||||
}
|
||||
};
|
||||
|
|
@ -391,12 +408,12 @@ static __initconst const u64 nehalem_hw_cache_event_ids
|
|||
{
|
||||
[ C(L1D) ] = {
|
||||
[ C(OP_READ) ] = {
|
||||
[ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI */
|
||||
[ C(RESULT_MISS) ] = 0x0140, /* L1D_CACHE_LD.I_STATE */
|
||||
[ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */
|
||||
[ C(RESULT_MISS) ] = 0x0151, /* L1D.REPL */
|
||||
},
|
||||
[ C(OP_WRITE) ] = {
|
||||
[ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI */
|
||||
[ C(RESULT_MISS) ] = 0x0141, /* L1D_CACHE_ST.I_STATE */
|
||||
[ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */
|
||||
[ C(RESULT_MISS) ] = 0x0251, /* L1D.M_REPL */
|
||||
},
|
||||
[ C(OP_PREFETCH) ] = {
|
||||
[ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS */
|
||||
|
|
@ -933,6 +950,16 @@ static int intel_pmu_handle_irq(struct pt_regs *regs)
|
|||
|
||||
cpuc = &__get_cpu_var(cpu_hw_events);
|
||||
|
||||
/*
|
||||
* Some chipsets need to unmask the LVTPC in a particular spot
|
||||
* inside the nmi handler. As a result, the unmasking was pushed
|
||||
* into all the nmi handlers.
|
||||
*
|
||||
* This handler doesn't seem to have any issues with the unmasking
|
||||
* so it was left at the top.
|
||||
*/
|
||||
apic_write(APIC_LVTPC, APIC_DM_NMI);
|
||||
|
||||
intel_pmu_disable_all();
|
||||
handled = intel_pmu_drain_bts_buffer();
|
||||
status = intel_pmu_get_status();
|
||||
|
|
@ -998,6 +1025,9 @@ intel_bts_constraints(struct perf_event *event)
|
|||
struct hw_perf_event *hwc = &event->hw;
|
||||
unsigned int hw_event, bts_event;
|
||||
|
||||
if (event->attr.freq)
|
||||
return NULL;
|
||||
|
||||
hw_event = hwc->config & INTEL_ARCH_EVENT_MASK;
|
||||
bts_event = x86_pmu.event_map(PERF_COUNT_HW_BRANCH_INSTRUCTIONS);
|
||||
|
||||
|
|
@ -1409,6 +1439,18 @@ static __init int intel_pmu_init(void)
|
|||
x86_pmu.percore_constraints = intel_nehalem_percore_constraints;
|
||||
x86_pmu.enable_all = intel_pmu_nhm_enable_all;
|
||||
x86_pmu.extra_regs = intel_nehalem_extra_regs;
|
||||
|
||||
if (ebx & 0x40) {
|
||||
/*
|
||||
* Erratum AAJ80 detected, we work it around by using
|
||||
* the BR_MISP_EXEC.ANY event. This will over-count
|
||||
* branch-misses, but it's still much better than the
|
||||
* architectural event which is often completely bogus:
|
||||
*/
|
||||
intel_perfmon_event_map[PERF_COUNT_HW_BRANCH_MISSES] = 0x7f89;
|
||||
|
||||
pr_cont("erratum AAJ80 worked around, ");
|
||||
}
|
||||
pr_cont("Nehalem events, ");
|
||||
break;
|
||||
|
||||
|
|
@ -1425,6 +1467,7 @@ static __init int intel_pmu_init(void)
|
|||
|
||||
case 37: /* 32 nm nehalem, "Clarkdale" */
|
||||
case 44: /* 32 nm nehalem, "Gulftown" */
|
||||
case 47: /* 32 nm Xeon E7 */
|
||||
memcpy(hw_cache_event_ids, westmere_hw_cache_event_ids,
|
||||
sizeof(hw_cache_event_ids));
|
||||
memcpy(hw_cache_extra_regs, nehalem_hw_cache_extra_regs,
|
||||
|
|
|
|||
|
|
@ -947,14 +947,23 @@ static int p4_pmu_handle_irq(struct pt_regs *regs)
|
|||
if (!x86_perf_event_set_period(event))
|
||||
continue;
|
||||
if (perf_event_overflow(event, 1, &data, regs))
|
||||
p4_pmu_disable_event(event);
|
||||
x86_pmu_stop(event, 0);
|
||||
}
|
||||
|
||||
if (handled) {
|
||||
/* p4 quirk: unmask it again */
|
||||
apic_write(APIC_LVTPC, apic_read(APIC_LVTPC) & ~APIC_LVT_MASKED);
|
||||
if (handled)
|
||||
inc_irq_stat(apic_perf_irqs);
|
||||
}
|
||||
|
||||
/*
|
||||
* When dealing with the unmasking of the LVTPC on P4 perf hw, it has
|
||||
* been observed that the OVF bit flag has to be cleared first _before_
|
||||
* the LVTPC can be unmasked.
|
||||
*
|
||||
* The reason is the NMI line will continue to be asserted while the OVF
|
||||
* bit is set. This causes a second NMI to generate if the LVTPC is
|
||||
* unmasked before the OVF bit is cleared, leading to unknown NMI
|
||||
* messages.
|
||||
*/
|
||||
apic_write(APIC_LVTPC, APIC_DM_NMI);
|
||||
|
||||
return handled;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -391,7 +391,7 @@ static int ioapic_xlate(struct irq_domain *id, const u32 *intspec, u32 intsize,
|
|||
|
||||
set_io_apic_irq_attr(&attr, idx, line, it->trigger, it->polarity);
|
||||
|
||||
return io_apic_setup_irq_pin(*out_hwirq, cpu_to_node(0), &attr);
|
||||
return io_apic_setup_irq_pin_once(*out_hwirq, cpu_to_node(0), &attr);
|
||||
}
|
||||
|
||||
static void __init ioapic_add_ofnode(struct device_node *np)
|
||||
|
|
|
|||
|
|
@ -81,6 +81,9 @@ static u32 gart_unmapped_entry;
|
|||
#define AGPEXTERN
|
||||
#endif
|
||||
|
||||
/* GART can only remap to physical addresses < 1TB */
|
||||
#define GART_MAX_PHYS_ADDR (1ULL << 40)
|
||||
|
||||
/* backdoor interface to AGP driver */
|
||||
AGPEXTERN int agp_memory_reserved;
|
||||
AGPEXTERN __u32 *agp_gatt_table;
|
||||
|
|
@ -212,9 +215,13 @@ static dma_addr_t dma_map_area(struct device *dev, dma_addr_t phys_mem,
|
|||
size_t size, int dir, unsigned long align_mask)
|
||||
{
|
||||
unsigned long npages = iommu_num_pages(phys_mem, size, PAGE_SIZE);
|
||||
unsigned long iommu_page = alloc_iommu(dev, npages, align_mask);
|
||||
unsigned long iommu_page;
|
||||
int i;
|
||||
|
||||
if (unlikely(phys_mem + size > GART_MAX_PHYS_ADDR))
|
||||
return bad_dma_addr;
|
||||
|
||||
iommu_page = alloc_iommu(dev, npages, align_mask);
|
||||
if (iommu_page == -1) {
|
||||
if (!nonforced_iommu(dev, phys_mem, size))
|
||||
return phys_mem;
|
||||
|
|
|
|||
|
|
@ -608,6 +608,9 @@ static int ptrace_write_dr7(struct task_struct *tsk, unsigned long data)
|
|||
unsigned len, type;
|
||||
struct perf_event *bp;
|
||||
|
||||
if (ptrace_get_breakpoints(tsk) < 0)
|
||||
return -ESRCH;
|
||||
|
||||
data &= ~DR_CONTROL_RESERVED;
|
||||
old_dr7 = ptrace_get_dr7(thread->ptrace_bps);
|
||||
restore:
|
||||
|
|
@ -655,6 +658,9 @@ restore:
|
|||
}
|
||||
goto restore;
|
||||
}
|
||||
|
||||
ptrace_put_breakpoints(tsk);
|
||||
|
||||
return ((orig_ret < 0) ? orig_ret : rc);
|
||||
}
|
||||
|
||||
|
|
@ -668,10 +674,17 @@ static unsigned long ptrace_get_debugreg(struct task_struct *tsk, int n)
|
|||
|
||||
if (n < HBP_NUM) {
|
||||
struct perf_event *bp;
|
||||
|
||||
if (ptrace_get_breakpoints(tsk) < 0)
|
||||
return -ESRCH;
|
||||
|
||||
bp = thread->ptrace_bps[n];
|
||||
if (!bp)
|
||||
return 0;
|
||||
val = 0;
|
||||
else
|
||||
val = bp->hw.info.address;
|
||||
|
||||
ptrace_put_breakpoints(tsk);
|
||||
} else if (n == 6) {
|
||||
val = thread->debugreg6;
|
||||
} else if (n == 7) {
|
||||
|
|
@ -686,6 +699,10 @@ static int ptrace_set_breakpoint_addr(struct task_struct *tsk, int nr,
|
|||
struct perf_event *bp;
|
||||
struct thread_struct *t = &tsk->thread;
|
||||
struct perf_event_attr attr;
|
||||
int err = 0;
|
||||
|
||||
if (ptrace_get_breakpoints(tsk) < 0)
|
||||
return -ESRCH;
|
||||
|
||||
if (!t->ptrace_bps[nr]) {
|
||||
ptrace_breakpoint_init(&attr);
|
||||
|
|
@ -709,24 +726,23 @@ static int ptrace_set_breakpoint_addr(struct task_struct *tsk, int nr,
|
|||
* writing for the user. And anyway this is the previous
|
||||
* behaviour.
|
||||
*/
|
||||
if (IS_ERR(bp))
|
||||
return PTR_ERR(bp);
|
||||
if (IS_ERR(bp)) {
|
||||
err = PTR_ERR(bp);
|
||||
goto put;
|
||||
}
|
||||
|
||||
t->ptrace_bps[nr] = bp;
|
||||
} else {
|
||||
int err;
|
||||
|
||||
bp = t->ptrace_bps[nr];
|
||||
|
||||
attr = bp->attr;
|
||||
attr.bp_addr = addr;
|
||||
err = modify_user_hw_breakpoint(bp, &attr);
|
||||
if (err)
|
||||
return err;
|
||||
}
|
||||
|
||||
|
||||
return 0;
|
||||
put:
|
||||
ptrace_put_breakpoints(tsk);
|
||||
return err;
|
||||
}
|
||||
|
||||
/*
|
||||
|
|
|
|||
|
|
@ -21,26 +21,26 @@ r_base = .
|
|||
/* Get our own relocated address */
|
||||
call 1f
|
||||
1: popl %ebx
|
||||
subl $1b, %ebx
|
||||
subl $(1b - r_base), %ebx
|
||||
|
||||
/* Compute the equivalent real-mode segment */
|
||||
movl %ebx, %ecx
|
||||
shrl $4, %ecx
|
||||
|
||||
/* Patch post-real-mode segment jump */
|
||||
movw dispatch_table(%ebx,%eax,2),%ax
|
||||
movw %ax, 101f(%ebx)
|
||||
movw %cx, 102f(%ebx)
|
||||
movw (dispatch_table - r_base)(%ebx,%eax,2),%ax
|
||||
movw %ax, (101f - r_base)(%ebx)
|
||||
movw %cx, (102f - r_base)(%ebx)
|
||||
|
||||
/* Set up the IDT for real mode. */
|
||||
lidtl machine_real_restart_idt(%ebx)
|
||||
lidtl (machine_real_restart_idt - r_base)(%ebx)
|
||||
|
||||
/*
|
||||
* Set up a GDT from which we can load segment descriptors for real
|
||||
* mode. The GDT is not used in real mode; it is just needed here to
|
||||
* prepare the descriptors.
|
||||
*/
|
||||
lgdtl machine_real_restart_gdt(%ebx)
|
||||
lgdtl (machine_real_restart_gdt - r_base)(%ebx)
|
||||
|
||||
/*
|
||||
* Load the data segment registers with 16-bit compatible values
|
||||
|
|
|
|||
|
|
@ -312,26 +312,6 @@ void __cpuinit smp_store_cpu_info(int id)
|
|||
identify_secondary_cpu(c);
|
||||
}
|
||||
|
||||
static void __cpuinit check_cpu_siblings_on_same_node(int cpu1, int cpu2)
|
||||
{
|
||||
int node1 = early_cpu_to_node(cpu1);
|
||||
int node2 = early_cpu_to_node(cpu2);
|
||||
|
||||
/*
|
||||
* Our CPU scheduler assumes all logical cpus in the same physical cpu
|
||||
* share the same node. But, buggy ACPI or NUMA emulation might assign
|
||||
* them to different node. Fix it.
|
||||
*/
|
||||
if (node1 != node2) {
|
||||
pr_warning("CPU %d in node %d and CPU %d in node %d are in the same physical CPU. forcing same node %d\n",
|
||||
cpu1, node1, cpu2, node2, node2);
|
||||
|
||||
numa_remove_cpu(cpu1);
|
||||
numa_set_node(cpu1, node2);
|
||||
numa_add_cpu(cpu1);
|
||||
}
|
||||
}
|
||||
|
||||
static void __cpuinit link_thread_siblings(int cpu1, int cpu2)
|
||||
{
|
||||
cpumask_set_cpu(cpu1, cpu_sibling_mask(cpu2));
|
||||
|
|
@ -340,7 +320,6 @@ static void __cpuinit link_thread_siblings(int cpu1, int cpu2)
|
|||
cpumask_set_cpu(cpu2, cpu_core_mask(cpu1));
|
||||
cpumask_set_cpu(cpu1, cpu_llc_shared_mask(cpu2));
|
||||
cpumask_set_cpu(cpu2, cpu_llc_shared_mask(cpu1));
|
||||
check_cpu_siblings_on_same_node(cpu1, cpu2);
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -382,12 +361,10 @@ void __cpuinit set_cpu_sibling_map(int cpu)
|
|||
per_cpu(cpu_llc_id, cpu) == per_cpu(cpu_llc_id, i)) {
|
||||
cpumask_set_cpu(i, cpu_llc_shared_mask(cpu));
|
||||
cpumask_set_cpu(cpu, cpu_llc_shared_mask(i));
|
||||
check_cpu_siblings_on_same_node(cpu, i);
|
||||
}
|
||||
if (c->phys_proc_id == cpu_data(i).phys_proc_id) {
|
||||
cpumask_set_cpu(i, cpu_core_mask(cpu));
|
||||
cpumask_set_cpu(cpu, cpu_core_mask(i));
|
||||
check_cpu_siblings_on_same_node(cpu, i);
|
||||
/*
|
||||
* Does this new cpu bringup a new core?
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -213,53 +213,48 @@ int early_cpu_to_node(int cpu)
|
|||
return per_cpu(x86_cpu_to_node_map, cpu);
|
||||
}
|
||||
|
||||
struct cpumask __cpuinit *debug_cpumask_set_cpu(int cpu, int enable)
|
||||
void debug_cpumask_set_cpu(int cpu, int node, bool enable)
|
||||
{
|
||||
int node = early_cpu_to_node(cpu);
|
||||
struct cpumask *mask;
|
||||
char buf[64];
|
||||
|
||||
if (node == NUMA_NO_NODE) {
|
||||
/* early_cpu_to_node() already emits a warning and trace */
|
||||
return NULL;
|
||||
return;
|
||||
}
|
||||
mask = node_to_cpumask_map[node];
|
||||
if (!mask) {
|
||||
pr_err("node_to_cpumask_map[%i] NULL\n", node);
|
||||
dump_stack();
|
||||
return NULL;
|
||||
}
|
||||
|
||||
cpulist_scnprintf(buf, sizeof(buf), mask);
|
||||
printk(KERN_DEBUG "%s cpu %d node %d: mask now %s\n",
|
||||
enable ? "numa_add_cpu" : "numa_remove_cpu",
|
||||
cpu, node, buf);
|
||||
return mask;
|
||||
}
|
||||
|
||||
# ifndef CONFIG_NUMA_EMU
|
||||
static void __cpuinit numa_set_cpumask(int cpu, int enable)
|
||||
{
|
||||
struct cpumask *mask;
|
||||
|
||||
mask = debug_cpumask_set_cpu(cpu, enable);
|
||||
if (!mask)
|
||||
return;
|
||||
}
|
||||
|
||||
if (enable)
|
||||
cpumask_set_cpu(cpu, mask);
|
||||
else
|
||||
cpumask_clear_cpu(cpu, mask);
|
||||
|
||||
cpulist_scnprintf(buf, sizeof(buf), mask);
|
||||
printk(KERN_DEBUG "%s cpu %d node %d: mask now %s\n",
|
||||
enable ? "numa_add_cpu" : "numa_remove_cpu",
|
||||
cpu, node, buf);
|
||||
return;
|
||||
}
|
||||
|
||||
# ifndef CONFIG_NUMA_EMU
|
||||
static void __cpuinit numa_set_cpumask(int cpu, bool enable)
|
||||
{
|
||||
debug_cpumask_set_cpu(cpu, early_cpu_to_node(cpu), enable);
|
||||
}
|
||||
|
||||
void __cpuinit numa_add_cpu(int cpu)
|
||||
{
|
||||
numa_set_cpumask(cpu, 1);
|
||||
numa_set_cpumask(cpu, true);
|
||||
}
|
||||
|
||||
void __cpuinit numa_remove_cpu(int cpu)
|
||||
{
|
||||
numa_set_cpumask(cpu, 0);
|
||||
numa_set_cpumask(cpu, false);
|
||||
}
|
||||
# endif /* !CONFIG_NUMA_EMU */
|
||||
|
||||
|
|
|
|||
|
|
@ -306,7 +306,7 @@ int __init numa_cleanup_meminfo(struct numa_meminfo *mi)
|
|||
bi->end = min(bi->end, high);
|
||||
|
||||
/* and there's no empty block */
|
||||
if (bi->start == bi->end) {
|
||||
if (bi->start >= bi->end) {
|
||||
numa_remove_memblk_from(i--, mi);
|
||||
continue;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -454,10 +454,9 @@ void __cpuinit numa_remove_cpu(int cpu)
|
|||
cpumask_clear_cpu(cpu, node_to_cpumask_map[i]);
|
||||
}
|
||||
#else /* !CONFIG_DEBUG_PER_CPU_MAPS */
|
||||
static void __cpuinit numa_set_cpumask(int cpu, int enable)
|
||||
static void __cpuinit numa_set_cpumask(int cpu, bool enable)
|
||||
{
|
||||
struct cpumask *mask;
|
||||
int nid, physnid, i;
|
||||
int nid, physnid;
|
||||
|
||||
nid = early_cpu_to_node(cpu);
|
||||
if (nid == NUMA_NO_NODE) {
|
||||
|
|
@ -467,28 +466,21 @@ static void __cpuinit numa_set_cpumask(int cpu, int enable)
|
|||
|
||||
physnid = emu_nid_to_phys[nid];
|
||||
|
||||
for_each_online_node(i) {
|
||||
for_each_online_node(nid) {
|
||||
if (emu_nid_to_phys[nid] != physnid)
|
||||
continue;
|
||||
|
||||
mask = debug_cpumask_set_cpu(cpu, enable);
|
||||
if (!mask)
|
||||
return;
|
||||
|
||||
if (enable)
|
||||
cpumask_set_cpu(cpu, mask);
|
||||
else
|
||||
cpumask_clear_cpu(cpu, mask);
|
||||
debug_cpumask_set_cpu(cpu, nid, enable);
|
||||
}
|
||||
}
|
||||
|
||||
void __cpuinit numa_add_cpu(int cpu)
|
||||
{
|
||||
numa_set_cpumask(cpu, 1);
|
||||
numa_set_cpumask(cpu, true);
|
||||
}
|
||||
|
||||
void __cpuinit numa_remove_cpu(int cpu)
|
||||
{
|
||||
numa_set_cpumask(cpu, 0);
|
||||
numa_set_cpumask(cpu, false);
|
||||
}
|
||||
#endif /* !CONFIG_DEBUG_PER_CPU_MAPS */
|
||||
|
|
|
|||
|
|
@ -347,7 +347,7 @@
|
|||
"pciclass0c03";
|
||||
|
||||
reg = <0x16800 0x0 0x0 0x0 0x0>;
|
||||
interrupts = <22 3>;
|
||||
interrupts = <22 1>;
|
||||
};
|
||||
|
||||
usb@d,1 {
|
||||
|
|
@ -357,7 +357,7 @@
|
|||
"pciclass0c03";
|
||||
|
||||
reg = <0x16900 0x0 0x0 0x0 0x0>;
|
||||
interrupts = <22 3>;
|
||||
interrupts = <22 1>;
|
||||
};
|
||||
|
||||
sata@e,0 {
|
||||
|
|
@ -367,7 +367,7 @@
|
|||
"pciclass0106";
|
||||
|
||||
reg = <0x17000 0x0 0x0 0x0 0x0>;
|
||||
interrupts = <23 3>;
|
||||
interrupts = <23 1>;
|
||||
};
|
||||
|
||||
flash@f,0 {
|
||||
|
|
|
|||
|
|
@ -1463,6 +1463,119 @@ static int xen_pgd_alloc(struct mm_struct *mm)
|
|||
return ret;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_X86_64
|
||||
static __initdata u64 __last_pgt_set_rw = 0;
|
||||
static __initdata u64 __pgt_buf_start = 0;
|
||||
static __initdata u64 __pgt_buf_end = 0;
|
||||
static __initdata u64 __pgt_buf_top = 0;
|
||||
/*
|
||||
* As a consequence of the commit:
|
||||
*
|
||||
* commit 4b239f458c229de044d6905c2b0f9fe16ed9e01e
|
||||
* Author: Yinghai Lu <yinghai@kernel.org>
|
||||
* Date: Fri Dec 17 16:58:28 2010 -0800
|
||||
*
|
||||
* x86-64, mm: Put early page table high
|
||||
*
|
||||
* at some point init_memory_mapping is going to reach the pagetable pages
|
||||
* area and map those pages too (mapping them as normal memory that falls
|
||||
* in the range of addresses passed to init_memory_mapping as argument).
|
||||
* Some of those pages are already pagetable pages (they are in the range
|
||||
* pgt_buf_start-pgt_buf_end) therefore they are going to be mapped RO and
|
||||
* everything is fine.
|
||||
* Some of these pages are not pagetable pages yet (they fall in the range
|
||||
* pgt_buf_end-pgt_buf_top; for example the page at pgt_buf_end) so they
|
||||
* are going to be mapped RW. When these pages become pagetable pages and
|
||||
* are hooked into the pagetable, xen will find that the guest has already
|
||||
* a RW mapping of them somewhere and fail the operation.
|
||||
* The reason Xen requires pagetables to be RO is that the hypervisor needs
|
||||
* to verify that the pagetables are valid before using them. The validation
|
||||
* operations are called "pinning".
|
||||
*
|
||||
* In order to fix the issue we mark all the pages in the entire range
|
||||
* pgt_buf_start-pgt_buf_top as RO, however when the pagetable allocation
|
||||
* is completed only the range pgt_buf_start-pgt_buf_end is reserved by
|
||||
* init_memory_mapping. Hence the kernel is going to crash as soon as one
|
||||
* of the pages in the range pgt_buf_end-pgt_buf_top is reused (b/c those
|
||||
* ranges are RO).
|
||||
*
|
||||
* For this reason, 'mark_rw_past_pgt' is introduced which is called _after_
|
||||
* the init_memory_mapping has completed (in a perfect world we would
|
||||
* call this function from init_memory_mapping, but lets ignore that).
|
||||
*
|
||||
* Because we are called _after_ init_memory_mapping the pgt_buf_[start,
|
||||
* end,top] have all changed to new values (b/c init_memory_mapping
|
||||
* is called and setting up another new page-table). Hence, the first time
|
||||
* we enter this function, we save away the pgt_buf_start value and update
|
||||
* the pgt_buf_[end,top].
|
||||
*
|
||||
* When we detect that the "old" pgt_buf_start through pgt_buf_end
|
||||
* PFNs have been reserved (so memblock_x86_reserve_range has been called),
|
||||
* we immediately set out to RW the "old" pgt_buf_end through pgt_buf_top.
|
||||
*
|
||||
* And then we update those "old" pgt_buf_[end|top] with the new ones
|
||||
* so that we can redo this on the next pagetable.
|
||||
*/
|
||||
static __init void mark_rw_past_pgt(void) {
|
||||
|
||||
if (pgt_buf_end > pgt_buf_start) {
|
||||
u64 addr, size;
|
||||
|
||||
/* Save it away. */
|
||||
if (!__pgt_buf_start) {
|
||||
__pgt_buf_start = pgt_buf_start;
|
||||
__pgt_buf_end = pgt_buf_end;
|
||||
__pgt_buf_top = pgt_buf_top;
|
||||
return;
|
||||
}
|
||||
/* If we get the range that starts at __pgt_buf_end that means
|
||||
* the range is reserved, and that in 'init_memory_mapping'
|
||||
* the 'memblock_x86_reserve_range' has been called with the
|
||||
* outdated __pgt_buf_start, __pgt_buf_end (the "new"
|
||||
* pgt_buf_[start|end|top] refer now to a new pagetable.
|
||||
* Note: we are called _after_ the pgt_buf_[..] have been
|
||||
* updated.*/
|
||||
|
||||
addr = memblock_x86_find_in_range_size(PFN_PHYS(__pgt_buf_start),
|
||||
&size, PAGE_SIZE);
|
||||
|
||||
/* Still not reserved, meaning 'memblock_x86_reserve_range'
|
||||
* hasn't been called yet. Update the _end and _top.*/
|
||||
if (addr == PFN_PHYS(__pgt_buf_start)) {
|
||||
__pgt_buf_end = pgt_buf_end;
|
||||
__pgt_buf_top = pgt_buf_top;
|
||||
return;
|
||||
}
|
||||
|
||||
/* OK, the area is reserved, meaning it is time for us to
|
||||
* set RW for the old end->top PFNs. */
|
||||
|
||||
/* ..unless we had already done this. */
|
||||
if (__pgt_buf_end == __last_pgt_set_rw)
|
||||
return;
|
||||
|
||||
addr = PFN_PHYS(__pgt_buf_end);
|
||||
|
||||
/* set as RW the rest */
|
||||
printk(KERN_DEBUG "xen: setting RW the range %llx - %llx\n",
|
||||
PFN_PHYS(__pgt_buf_end), PFN_PHYS(__pgt_buf_top));
|
||||
|
||||
while (addr < PFN_PHYS(__pgt_buf_top)) {
|
||||
make_lowmem_page_readwrite(__va(addr));
|
||||
addr += PAGE_SIZE;
|
||||
}
|
||||
/* And update everything so that we are ready for the next
|
||||
* pagetable (the one created for regions past 4GB) */
|
||||
__last_pgt_set_rw = __pgt_buf_end;
|
||||
__pgt_buf_start = pgt_buf_start;
|
||||
__pgt_buf_end = pgt_buf_end;
|
||||
__pgt_buf_top = pgt_buf_top;
|
||||
}
|
||||
return;
|
||||
}
|
||||
#else
|
||||
static __init void mark_rw_past_pgt(void) { }
|
||||
#endif
|
||||
static void xen_pgd_free(struct mm_struct *mm, pgd_t *pgd)
|
||||
{
|
||||
#ifdef CONFIG_X86_64
|
||||
|
|
@ -1473,17 +1586,29 @@ static void xen_pgd_free(struct mm_struct *mm, pgd_t *pgd)
|
|||
#endif
|
||||
}
|
||||
|
||||
#ifdef CONFIG_X86_32
|
||||
static __init pte_t mask_rw_pte(pte_t *ptep, pte_t pte)
|
||||
{
|
||||
unsigned long pfn = pte_pfn(pte);
|
||||
|
||||
#ifdef CONFIG_X86_32
|
||||
/* If there's an existing pte, then don't allow _PAGE_RW to be set */
|
||||
if (pte_val_ma(*ptep) & _PAGE_PRESENT)
|
||||
pte = __pte_ma(((pte_val_ma(*ptep) & _PAGE_RW) | ~_PAGE_RW) &
|
||||
pte_val_ma(pte));
|
||||
#endif
|
||||
|
||||
return pte;
|
||||
}
|
||||
#else /* CONFIG_X86_64 */
|
||||
static __init pte_t mask_rw_pte(pte_t *ptep, pte_t pte)
|
||||
{
|
||||
unsigned long pfn = pte_pfn(pte);
|
||||
|
||||
/*
|
||||
* A bit of optimization. We do not need to call the workaround
|
||||
* when xen_set_pte_init is called with a PTE with 0 as PFN.
|
||||
* That is b/c the pagetable at that point are just being populated
|
||||
* with empty values and we can save some cycles by not calling
|
||||
* the 'memblock' code.*/
|
||||
if (pfn)
|
||||
mark_rw_past_pgt();
|
||||
/*
|
||||
* If the new pfn is within the range of the newly allocated
|
||||
* kernel pagetable, and it isn't being mapped into an
|
||||
|
|
@ -1491,12 +1616,13 @@ static __init pte_t mask_rw_pte(pte_t *ptep, pte_t pte)
|
|||
* it is RO.
|
||||
*/
|
||||
if (((!is_early_ioremap_ptep(ptep) &&
|
||||
pfn >= pgt_buf_start && pfn < pgt_buf_end)) ||
|
||||
pfn >= pgt_buf_start && pfn < pgt_buf_top)) ||
|
||||
(is_early_ioremap_ptep(ptep) && pfn != (pgt_buf_end - 1)))
|
||||
pte = pte_wrprotect(pte);
|
||||
|
||||
return pte;
|
||||
}
|
||||
#endif /* CONFIG_X86_64 */
|
||||
|
||||
/* Init-time set_pte while constructing initial pagetables, which
|
||||
doesn't allow RO pagetable pages to be remapped RW */
|
||||
|
|
@ -1992,6 +2118,8 @@ __init void xen_ident_map_ISA(void)
|
|||
|
||||
static __init void xen_post_allocator_init(void)
|
||||
{
|
||||
mark_rw_past_pgt();
|
||||
|
||||
#ifdef CONFIG_XEN_DEBUG
|
||||
pv_mmu_ops.make_pte = PV_CALLEE_SAVE(xen_make_pte_debug);
|
||||
#endif
|
||||
|
|
|
|||
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