drm/i915: Set INSTPM_FORCE_ORDERING via LRI on gen8, drop it on gen9+
INSTPM is saved in the logical context so we should initialize it using LRIs on gen8. It actually defaults to 1 starting from HSW, but let's keep the write around anyway. Also drop the INSTPM_FORCE_ORDERING setup entirely on gen9+ since it's now a reserved bit. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
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64987fc59d
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9cc8302061
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@ -800,6 +800,8 @@ static int bdw_init_workarounds(struct intel_engine_cs *ring)
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struct drm_device *dev = ring->dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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WA_SET_BIT_MASKED(INSTPM, INSTPM_FORCE_ORDERING);
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/* WaDisablePartialInstShootdown:bdw */
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/* WaDisableThreadStallDopClockGating:bdw (pre-production) */
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WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
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@ -861,6 +863,8 @@ static int chv_init_workarounds(struct intel_engine_cs *ring)
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struct drm_device *dev = ring->dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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WA_SET_BIT_MASKED(INSTPM, INSTPM_FORCE_ORDERING);
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/* WaDisablePartialInstShootdown:chv */
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/* WaDisableThreadStallDopClockGating:chv */
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WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
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@ -1132,7 +1136,7 @@ static int init_render_ring(struct intel_engine_cs *ring)
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_MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
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}
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if (INTEL_INFO(dev)->gen >= 6)
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if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8)
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I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
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if (HAS_L3_DPF(dev))
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