arm64: CPU support
This patch adds AArch64 CPU specific functionality. It assumes that the implementation is generic to AArch64 and does not require specific identification. Different CPU implementations may require the setting of various ACTLR_EL1 bits but such information is not currently available and it should ideally be pushed to firmware. Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Acked-by: Tony Lindgren <tony@atomide.com> Acked-by: Nicolas Pitre <nico@linaro.org> Acked-by: Olof Johansson <olof@lixom.net> Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
This commit is contained in:
Catalin Marinas
Родитель
b3901d54dc
Коммит
9cce7a435f
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@ -0,0 +1,30 @@
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/*
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* arch/arm64/include/asm/cputable.h
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*
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* Copyright (C) 2012 ARM Ltd.
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
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||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef __ASM_CPUTABLE_H
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#define __ASM_CPUTABLE_H
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struct cpu_info {
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unsigned int cpu_id_val;
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unsigned int cpu_id_mask;
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const char *cpu_name;
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unsigned long (*cpu_setup)(void);
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};
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extern struct cpu_info *lookup_processor_type(unsigned int);
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#endif
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@ -0,0 +1,49 @@
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/*
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* Copyright (C) 2012 ARM Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
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*
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||||
* This program is distributed in the hope that it will be useful,
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||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
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||||
* You should have received a copy of the GNU General Public License
|
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef __ASM_CPUTYPE_H
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#define __ASM_CPUTYPE_H
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#define ID_MIDR_EL1 "midr_el1"
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#define ID_CTR_EL0 "ctr_el0"
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#define ID_AA64PFR0_EL1 "id_aa64pfr0_el1"
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#define ID_AA64DFR0_EL1 "id_aa64dfr0_el1"
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#define ID_AA64AFR0_EL1 "id_aa64afr0_el1"
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#define ID_AA64ISAR0_EL1 "id_aa64isar0_el1"
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#define ID_AA64MMFR0_EL1 "id_aa64mmfr0_el1"
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#define read_cpuid(reg) ({ \
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u64 __val; \
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asm("mrs %0, " reg : "=r" (__val)); \
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__val; \
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})
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/*
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* The CPU ID never changes at run time, so we might as well tell the
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* compiler that it's constant. Use this function to read the CPU ID
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* rather than directly reading processor_id or read_cpuid() directly.
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*/
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static inline u32 __attribute_const__ read_cpuid_id(void)
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{
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return read_cpuid(ID_MIDR_EL1);
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}
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static inline u32 __attribute_const__ read_cpuid_cachetype(void)
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{
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return read_cpuid(ID_CTR_EL0);
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}
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#endif
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@ -0,0 +1,50 @@
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/*
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* Based on arch/arm/include/asm/proc-fns.h
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*
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* Copyright (C) 1997-1999 Russell King
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* Copyright (C) 2000 Deep Blue Solutions Ltd
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* Copyright (C) 2012 ARM Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
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* GNU General Public License for more details.
|
||||
*
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* You should have received a copy of the GNU General Public License
|
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef __ASM_PROCFNS_H
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#define __ASM_PROCFNS_H
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#ifdef __KERNEL__
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#ifndef __ASSEMBLY__
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#include <asm/page.h>
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struct mm_struct;
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extern void cpu_cache_off(void);
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extern void cpu_do_idle(void);
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extern void cpu_do_switch_mm(unsigned long pgd_phys, struct mm_struct *mm);
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extern void cpu_reset(unsigned long addr) __attribute__((noreturn));
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#include <asm/memory.h>
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#define cpu_switch_mm(pgd,mm) cpu_do_switch_mm(virt_to_phys(pgd),mm)
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#define cpu_get_pgd() \
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({ \
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unsigned long pg; \
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asm("mrs %0, ttbr0_el1\n" \
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: "=r" (pg)); \
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pg &= ~0xffff000000003ffful; \
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(pgd_t *)phys_to_virt(pg); \
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})
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#endif /* __ASSEMBLY__ */
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#endif /* __KERNEL__ */
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#endif /* __ASM_PROCFNS_H */
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@ -0,0 +1,175 @@
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/*
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* Based on arch/arm/include/asm/processor.h
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*
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* Copyright (C) 1995-1999 Russell King
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* Copyright (C) 2012 ARM Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
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||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef __ASM_PROCESSOR_H
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#define __ASM_PROCESSOR_H
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/*
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* Default implementation of macro that returns current
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* instruction pointer ("program counter").
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*/
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#define current_text_addr() ({ __label__ _l; _l: &&_l;})
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#ifdef __KERNEL__
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#include <linux/string.h>
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#include <asm/fpsimd.h>
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#include <asm/hw_breakpoint.h>
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#include <asm/ptrace.h>
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#include <asm/types.h>
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#ifdef __KERNEL__
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#define STACK_TOP_MAX TASK_SIZE_64
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#ifdef CONFIG_COMPAT
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#define AARCH32_VECTORS_BASE 0xffff0000
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#define STACK_TOP (test_thread_flag(TIF_32BIT) ? \
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AARCH32_VECTORS_BASE : STACK_TOP_MAX)
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#else
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#define STACK_TOP STACK_TOP_MAX
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#endif /* CONFIG_COMPAT */
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#endif /* __KERNEL__ */
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struct debug_info {
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/* Have we suspended stepping by a debugger? */
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int suspended_step;
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/* Allow breakpoints and watchpoints to be disabled for this thread. */
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int bps_disabled;
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int wps_disabled;
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/* Hardware breakpoints pinned to this task. */
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struct perf_event *hbp_break[ARM_MAX_BRP];
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struct perf_event *hbp_watch[ARM_MAX_WRP];
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};
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struct cpu_context {
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unsigned long x19;
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unsigned long x20;
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unsigned long x21;
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unsigned long x22;
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unsigned long x23;
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unsigned long x24;
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unsigned long x25;
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unsigned long x26;
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unsigned long x27;
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unsigned long x28;
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unsigned long fp;
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unsigned long sp;
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unsigned long pc;
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};
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struct thread_struct {
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struct cpu_context cpu_context; /* cpu context */
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unsigned long tp_value;
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struct fpsimd_state fpsimd_state;
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unsigned long fault_address; /* fault info */
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struct debug_info debug; /* debugging */
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};
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#define INIT_THREAD { }
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static inline void start_thread_common(struct pt_regs *regs, unsigned long pc)
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{
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memset(regs, 0, sizeof(*regs));
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regs->syscallno = ~0UL;
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regs->pc = pc;
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}
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static inline void start_thread(struct pt_regs *regs, unsigned long pc,
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unsigned long sp)
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{
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unsigned long *stack = (unsigned long *)sp;
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start_thread_common(regs, pc);
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regs->pstate = PSR_MODE_EL0t;
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regs->sp = sp;
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regs->regs[2] = stack[2]; /* x2 (envp) */
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regs->regs[1] = stack[1]; /* x1 (argv) */
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regs->regs[0] = stack[0]; /* x0 (argc) */
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}
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#ifdef CONFIG_COMPAT
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static inline void compat_start_thread(struct pt_regs *regs, unsigned long pc,
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unsigned long sp)
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{
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unsigned int *stack = (unsigned int *)sp;
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start_thread_common(regs, pc);
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regs->pstate = COMPAT_PSR_MODE_USR;
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if (pc & 1)
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regs->pstate |= COMPAT_PSR_T_BIT;
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regs->compat_sp = sp;
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regs->regs[2] = stack[2]; /* x2 (envp) */
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regs->regs[1] = stack[1]; /* x1 (argv) */
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regs->regs[0] = stack[0]; /* x0 (argc) */
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}
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#endif
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/* Forward declaration, a strange C thing */
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struct task_struct;
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/* Free all resources held by a thread. */
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extern void release_thread(struct task_struct *);
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/* Prepare to copy thread state - unlazy all lazy status */
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#define prepare_to_copy(tsk) do { } while (0)
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unsigned long get_wchan(struct task_struct *p);
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#define cpu_relax() barrier()
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/* Thread switching */
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extern struct task_struct *cpu_switch_to(struct task_struct *prev,
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struct task_struct *next);
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/*
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* Create a new kernel thread
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*/
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extern int kernel_thread(int (*fn)(void *), void *arg, unsigned long flags);
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#define task_pt_regs(p) \
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((struct pt_regs *)(THREAD_START_SP + task_stack_page(p)) - 1)
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#define KSTK_EIP(tsk) task_pt_regs(tsk)->pc
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#define KSTK_ESP(tsk) task_pt_regs(tsk)->sp
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/*
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* Prefetching support
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*/
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#define ARCH_HAS_PREFETCH
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static inline void prefetch(const void *ptr)
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{
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asm volatile("prfm pldl1keep, %a0\n" : : "p" (ptr));
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}
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#define ARCH_HAS_PREFETCHW
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static inline void prefetchw(const void *ptr)
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{
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asm volatile("prfm pstl1keep, %a0\n" : : "p" (ptr));
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}
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#define ARCH_HAS_SPINLOCK_PREFETCH
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static inline void spin_lock_prefetch(const void *x)
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{
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prefetchw(x);
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}
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#define HAVE_ARCH_PICK_MMAP_LAYOUT
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#endif
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#endif /* __ASM_PROCESSOR_H */
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@ -0,0 +1,33 @@
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/*
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* arch/arm64/kernel/cputable.c
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*
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* Copyright (C) 2012 ARM Ltd.
|
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*
|
||||
* This program is free software: you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
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*/
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#include <linux/init.h>
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#include <asm/cputable.h>
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extern unsigned long __cpu_setup(void);
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struct cpu_info __initdata cpu_table[] = {
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{
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.cpu_id_val = 0x000f0000,
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.cpu_id_mask = 0x000f0000,
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.cpu_name = "AArch64 Processor",
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.cpu_setup = __cpu_setup,
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},
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{ /* Empty */ },
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};
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@ -0,0 +1,186 @@
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/*
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* Based on arch/arm/mm/proc.S
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*
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* Copyright (C) 2001 Deep Blue Solutions Ltd.
|
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* Copyright (C) 2012 ARM Ltd.
|
||||
* Author: Catalin Marinas <catalin.marinas@arm.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
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#include <linux/init.h>
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#include <linux/linkage.h>
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#include <asm/assembler.h>
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#include <asm/asm-offsets.h>
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#include <asm/hwcap.h>
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#include <asm/pgtable-hwdef.h>
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#include <asm/pgtable.h>
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#include "proc-macros.S"
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#ifndef CONFIG_SMP
|
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/* PTWs cacheable, inner/outer WBWA not shareable */
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#define TCR_FLAGS TCR_IRGN_WBWA | TCR_ORGN_WBWA
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#else
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/* PTWs cacheable, inner/outer WBWA shareable */
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#define TCR_FLAGS TCR_IRGN_WBWA | TCR_ORGN_WBWA | TCR_SHARED
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#endif
|
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#define MAIR(attr, mt) ((attr) << ((mt) * 8))
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|
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/*
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* cpu_cache_off()
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*
|
||||
* Turn the CPU D-cache off.
|
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*/
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ENTRY(cpu_cache_off)
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mrs x0, sctlr_el1
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bic x0, x0, #1 << 2 // clear SCTLR.C
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msr sctlr_el1, x0
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isb
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ret
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ENDPROC(cpu_cache_off)
|
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|
||||
/*
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||||
* cpu_reset(loc)
|
||||
*
|
||||
* Perform a soft reset of the system. Put the CPU into the same state
|
||||
* as it would be if it had been reset, and branch to what would be the
|
||||
* reset vector. It must be executed with the flat identity mapping.
|
||||
*
|
||||
* - loc - location to jump to for soft reset
|
||||
*/
|
||||
.align 5
|
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ENTRY(cpu_reset)
|
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mrs x1, sctlr_el1
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||||
bic x1, x1, #1
|
||||
msr sctlr_el1, x1 // disable the MMU
|
||||
isb
|
||||
ret x0
|
||||
ENDPROC(cpu_reset)
|
||||
|
||||
/*
|
||||
* cpu_do_idle()
|
||||
*
|
||||
* Idle the processor (wait for interrupt).
|
||||
*/
|
||||
ENTRY(cpu_do_idle)
|
||||
dsb sy // WFI may enter a low-power mode
|
||||
wfi
|
||||
ret
|
||||
ENDPROC(cpu_do_idle)
|
||||
|
||||
/*
|
||||
* cpu_switch_mm(pgd_phys, tsk)
|
||||
*
|
||||
* Set the translation table base pointer to be pgd_phys.
|
||||
*
|
||||
* - pgd_phys - physical address of new TTB
|
||||
*/
|
||||
ENTRY(cpu_do_switch_mm)
|
||||
mmid w1, x1 // get mm->context.id
|
||||
bfi x0, x1, #48, #16 // set the ASID
|
||||
msr ttbr0_el1, x0 // set TTBR0
|
||||
isb
|
||||
ret
|
||||
ENDPROC(cpu_do_switch_mm)
|
||||
|
||||
cpu_name:
|
||||
.ascii "AArch64 Processor"
|
||||
.align
|
||||
|
||||
.section ".text.init", #alloc, #execinstr
|
||||
|
||||
/*
|
||||
* __cpu_setup
|
||||
*
|
||||
* Initialise the processor for turning the MMU on. Return in x0 the
|
||||
* value of the SCTLR_EL1 register.
|
||||
*/
|
||||
ENTRY(__cpu_setup)
|
||||
#ifdef CONFIG_SMP
|
||||
/* TODO: only do this for certain CPUs */
|
||||
/*
|
||||
* Enable SMP/nAMP mode.
|
||||
*/
|
||||
mrs x0, actlr_el1
|
||||
tbnz x0, #6, 1f // already enabled?
|
||||
orr x0, x0, #1 << 6
|
||||
msr actlr_el1, x0
|
||||
1:
|
||||
#endif
|
||||
/*
|
||||
* Preserve the link register across the function call.
|
||||
*/
|
||||
mov x28, lr
|
||||
bl __flush_dcache_all
|
||||
mov lr, x28
|
||||
ic iallu // I+BTB cache invalidate
|
||||
dsb sy
|
||||
|
||||
mov x0, #3 << 20
|
||||
msr cpacr_el1, x0 // Enable FP/ASIMD
|
||||
mov x0, #1
|
||||
msr oslar_el1, x0 // Set the debug OS lock
|
||||
tlbi vmalle1is // invalidate I + D TLBs
|
||||
/*
|
||||
* Memory region attributes for LPAE:
|
||||
*
|
||||
* n = AttrIndx[2:0]
|
||||
* n MAIR
|
||||
* DEVICE_nGnRnE 000 00000000
|
||||
* DEVICE_nGnRE 001 00000100
|
||||
* DEVICE_GRE 010 00001100
|
||||
* NORMAL_NC 011 01000100
|
||||
* NORMAL 100 11111111
|
||||
*/
|
||||
ldr x5, =MAIR(0x00, MT_DEVICE_nGnRnE) | \
|
||||
MAIR(0x04, MT_DEVICE_nGnRE) | \
|
||||
MAIR(0x0c, MT_DEVICE_GRE) | \
|
||||
MAIR(0x44, MT_NORMAL_NC) | \
|
||||
MAIR(0xff, MT_NORMAL)
|
||||
msr mair_el1, x5
|
||||
/*
|
||||
* Prepare SCTLR
|
||||
*/
|
||||
adr x5, crval
|
||||
ldp w5, w6, [x5]
|
||||
mrs x0, sctlr_el1
|
||||
bic x0, x0, x5 // clear bits
|
||||
orr x0, x0, x6 // set bits
|
||||
/*
|
||||
* Set/prepare TCR and TTBR. We use 512GB (39-bit) address range for
|
||||
* both user and kernel.
|
||||
*/
|
||||
ldr x10, =TCR_TxSZ(VA_BITS) | TCR_FLAGS | TCR_IPS_40BIT | \
|
||||
TCR_ASID16 | (1 << 31)
|
||||
#ifdef CONFIG_ARM64_64K_PAGES
|
||||
orr x10, x10, TCR_TG0_64K
|
||||
orr x10, x10, TCR_TG1_64K
|
||||
#endif
|
||||
msr tcr_el1, x10
|
||||
ret // return to head.S
|
||||
ENDPROC(__cpu_setup)
|
||||
|
||||
/*
|
||||
* n n T
|
||||
* U E WT T UD US IHBS
|
||||
* CE0 XWHW CZ ME TEEA S
|
||||
* .... .IEE .... NEAI TE.I ..AD DEN0 ACAM
|
||||
* 0011 0... 1101 ..0. ..0. 10.. .... .... < hardware reserved
|
||||
* .... .100 .... 01.1 11.1 ..01 0001 1101 < software settings
|
||||
*/
|
||||
.type crval, #object
|
||||
crval:
|
||||
.word 0x030802e2 // clear
|
||||
.word 0x0405d11d // set
|
||||
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