MIPS: Alchemy: add helpers to access static memory ctrl registers.
This patch changes the static memory controller registers to offsets from base, prefixes them with AU1000_ to avoid silent failures due to changed addresses and introduces helpers to access them. No functional changes, comparing assembly of a few select functions shows no differences. Signed-off-by: Manuel Lauss <manuel.lauss@gmail.com> Cc: Linux-MIPS <linux-mips@linux-mips.org> Patchwork: https://patchwork.linux-mips.org/patch/7463/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Manuel Lauss
Ralf Baechle
Родитель
1d09de7dc7
Коммит
9cf12167e9
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@ -64,18 +64,18 @@ static void save_core_regs(void)
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sleep_sys_pinfunc = alchemy_rdsys(AU1000_SYS_PINFUNC);
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/* Save the static memory controller configuration. */
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sleep_static_memctlr[0][0] = au_readl(MEM_STCFG0);
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sleep_static_memctlr[0][1] = au_readl(MEM_STTIME0);
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sleep_static_memctlr[0][2] = au_readl(MEM_STADDR0);
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sleep_static_memctlr[1][0] = au_readl(MEM_STCFG1);
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sleep_static_memctlr[1][1] = au_readl(MEM_STTIME1);
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sleep_static_memctlr[1][2] = au_readl(MEM_STADDR1);
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sleep_static_memctlr[2][0] = au_readl(MEM_STCFG2);
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sleep_static_memctlr[2][1] = au_readl(MEM_STTIME2);
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sleep_static_memctlr[2][2] = au_readl(MEM_STADDR2);
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sleep_static_memctlr[3][0] = au_readl(MEM_STCFG3);
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sleep_static_memctlr[3][1] = au_readl(MEM_STTIME3);
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sleep_static_memctlr[3][2] = au_readl(MEM_STADDR3);
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sleep_static_memctlr[0][0] = alchemy_rdsmem(AU1000_MEM_STCFG0);
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sleep_static_memctlr[0][1] = alchemy_rdsmem(AU1000_MEM_STTIME0);
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sleep_static_memctlr[0][2] = alchemy_rdsmem(AU1000_MEM_STADDR0);
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sleep_static_memctlr[1][0] = alchemy_rdsmem(AU1000_MEM_STCFG1);
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sleep_static_memctlr[1][1] = alchemy_rdsmem(AU1000_MEM_STTIME1);
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sleep_static_memctlr[1][2] = alchemy_rdsmem(AU1000_MEM_STADDR1);
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sleep_static_memctlr[2][0] = alchemy_rdsmem(AU1000_MEM_STCFG2);
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sleep_static_memctlr[2][1] = alchemy_rdsmem(AU1000_MEM_STTIME2);
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sleep_static_memctlr[2][2] = alchemy_rdsmem(AU1000_MEM_STADDR2);
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sleep_static_memctlr[3][0] = alchemy_rdsmem(AU1000_MEM_STCFG3);
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sleep_static_memctlr[3][1] = alchemy_rdsmem(AU1000_MEM_STTIME3);
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sleep_static_memctlr[3][2] = alchemy_rdsmem(AU1000_MEM_STADDR3);
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}
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static void restore_core_regs(void)
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@ -95,18 +95,18 @@ static void restore_core_regs(void)
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alchemy_wrsys(sleep_sys_pinfunc, AU1000_SYS_PINFUNC);
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/* Restore the static memory controller configuration. */
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au_writel(sleep_static_memctlr[0][0], MEM_STCFG0);
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au_writel(sleep_static_memctlr[0][1], MEM_STTIME0);
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au_writel(sleep_static_memctlr[0][2], MEM_STADDR0);
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au_writel(sleep_static_memctlr[1][0], MEM_STCFG1);
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au_writel(sleep_static_memctlr[1][1], MEM_STTIME1);
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au_writel(sleep_static_memctlr[1][2], MEM_STADDR1);
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au_writel(sleep_static_memctlr[2][0], MEM_STCFG2);
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au_writel(sleep_static_memctlr[2][1], MEM_STTIME2);
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au_writel(sleep_static_memctlr[2][2], MEM_STADDR2);
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au_writel(sleep_static_memctlr[3][0], MEM_STCFG3);
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au_writel(sleep_static_memctlr[3][1], MEM_STTIME3);
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au_writel(sleep_static_memctlr[3][2], MEM_STADDR3);
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alchemy_wrsmem(sleep_static_memctlr[0][0], AU1000_MEM_STCFG0);
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alchemy_wrsmem(sleep_static_memctlr[0][1], AU1000_MEM_STTIME0);
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alchemy_wrsmem(sleep_static_memctlr[0][2], AU1000_MEM_STADDR0);
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alchemy_wrsmem(sleep_static_memctlr[1][0], AU1000_MEM_STCFG1);
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alchemy_wrsmem(sleep_static_memctlr[1][1], AU1000_MEM_STTIME1);
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alchemy_wrsmem(sleep_static_memctlr[1][2], AU1000_MEM_STADDR1);
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alchemy_wrsmem(sleep_static_memctlr[2][0], AU1000_MEM_STCFG2);
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alchemy_wrsmem(sleep_static_memctlr[2][1], AU1000_MEM_STTIME2);
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alchemy_wrsmem(sleep_static_memctlr[2][2], AU1000_MEM_STADDR2);
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alchemy_wrsmem(sleep_static_memctlr[3][0], AU1000_MEM_STCFG3);
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alchemy_wrsmem(sleep_static_memctlr[3][1], AU1000_MEM_STTIME3);
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alchemy_wrsmem(sleep_static_memctlr[3][2], AU1000_MEM_STADDR3);
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}
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void au_sleep(void)
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@ -246,7 +246,7 @@ static void au1200_nand_cmd_ctrl(struct mtd_info *mtd, int cmd,
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static int au1200_nand_device_ready(struct mtd_info *mtd)
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{
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return __raw_readl((void __iomem *)MEM_STSTAT) & 1;
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return alchemy_rdsmem(AU1000_MEM_STSTAT) & 1;
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}
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static struct mtd_partition db1200_nand_parts[] = {
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@ -169,7 +169,7 @@ static void au1300_nand_cmd_ctrl(struct mtd_info *mtd, int cmd,
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static int au1300_nand_device_ready(struct mtd_info *mtd)
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{
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return __raw_readl((void __iomem *)MEM_STSTAT) & 1;
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return alchemy_rdsmem(AU1000_MEM_STSTAT) & 1;
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}
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static struct mtd_partition db1300_nand_parts[] = {
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@ -151,7 +151,7 @@ static void au1550_nand_cmd_ctrl(struct mtd_info *mtd, int cmd,
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static int au1550_nand_device_ready(struct mtd_info *mtd)
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{
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return __raw_readl((void __iomem *)MEM_STSTAT) & 1;
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return alchemy_rdsmem(AU1000_MEM_STSTAT) & 1;
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}
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static struct mtd_partition db1550_nand_parts[] = {
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@ -217,7 +217,7 @@ static struct platform_device pb1550_nand_dev = {
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static void __init pb1550_nand_setup(void)
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{
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int boot_swapboot = (au_readl(MEM_STSTAT) & (0x7 << 1)) |
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int boot_swapboot = (alchemy_rdsmem(AU1000_MEM_STSTAT) & (0x7 << 1)) |
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((bcsr_read(BCSR_STATUS) >> 6) & 0x1);
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gpio_direction_input(206); /* de-assert NAND CS# */
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@ -309,25 +309,21 @@
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#define AU1550_MEM_SDSREF 0x08D0
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#define AU1550_MEM_SDSLEEP MEM_SDSREF
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/* Static Bus Controller */
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#define MEM_STCFG0 0xB4001000
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#define MEM_STTIME0 0xB4001004
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#define MEM_STADDR0 0xB4001008
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#define MEM_STCFG1 0xB4001010
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#define MEM_STTIME1 0xB4001014
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#define MEM_STADDR1 0xB4001018
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#define MEM_STCFG2 0xB4001020
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#define MEM_STTIME2 0xB4001024
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#define MEM_STADDR2 0xB4001028
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#define MEM_STCFG3 0xB4001030
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#define MEM_STTIME3 0xB4001034
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#define MEM_STADDR3 0xB4001038
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#define MEM_STNDCTL 0xB4001100
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#define MEM_STSTAT 0xB4001104
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/* Static Bus Controller register offsets */
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#define AU1000_MEM_STCFG0 0x000
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#define AU1000_MEM_STTIME0 0x004
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#define AU1000_MEM_STADDR0 0x008
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#define AU1000_MEM_STCFG1 0x010
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#define AU1000_MEM_STTIME1 0x014
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#define AU1000_MEM_STADDR1 0x018
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#define AU1000_MEM_STCFG2 0x020
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#define AU1000_MEM_STTIME2 0x024
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#define AU1000_MEM_STADDR2 0x028
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#define AU1000_MEM_STCFG3 0x030
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#define AU1000_MEM_STTIME3 0x034
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#define AU1000_MEM_STADDR3 0x038
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#define AU1000_MEM_STNDCTL 0x100
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#define AU1000_MEM_STSTAT 0x104
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#define MEM_STNAND_CMD 0x0
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#define MEM_STNAND_ADDR 0x4
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@ -713,6 +709,22 @@ static inline void alchemy_wrsys(unsigned long v, int regofs)
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wmb(); /* drain writebuffer */
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}
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/* helpers to access static memctrl registers */
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static inline unsigned long alchemy_rdsmem(int regofs)
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{
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void __iomem *b = (void __iomem *)KSEG1ADDR(AU1000_STATIC_MEM_PHYS_ADDR);
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return __raw_readl(b + regofs);
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}
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static inline void alchemy_wrsmem(unsigned long v, int regofs)
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{
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void __iomem *b = (void __iomem *)KSEG1ADDR(AU1000_STATIC_MEM_PHYS_ADDR);
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__raw_writel(v, b + regofs);
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wmb(); /* drain writebuffer */
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}
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/* Early Au1000 have a write-only SYS_CPUPLL register. */
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static inline int au1xxx_cpu_has_pll_wo(void)
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{
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@ -223,12 +223,12 @@ static void au1550_hwcontrol(struct mtd_info *mtd, int cmd)
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case NAND_CTL_SETNCE:
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/* assert (force assert) chip enable */
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au_writel((1 << (4 + ctx->cs)), MEM_STNDCTL);
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alchemy_wrsmem((1 << (4 + ctx->cs)), AU1000_MEM_STNDCTL);
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break;
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case NAND_CTL_CLRNCE:
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/* deassert chip enable */
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au_writel(0, MEM_STNDCTL);
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alchemy_wrsmem(0, AU1000_MEM_STNDCTL);
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break;
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}
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@ -240,9 +240,7 @@ static void au1550_hwcontrol(struct mtd_info *mtd, int cmd)
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int au1550_device_ready(struct mtd_info *mtd)
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{
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int ret = (au_readl(MEM_STSTAT) & 0x1) ? 1 : 0;
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au_sync();
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return ret;
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return (alchemy_rdsmem(AU1000_MEM_STSTAT) & 0x1) ? 1 : 0;
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}
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/**
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