usb: dwc2: host: Properly set even/odd frame
When setting up ISO and INT transfers dwc2 needs to specify whether the
transfer is for an even or an odd frame (or microframe if the controller
is running in high speed mode).
The controller appears to use this as a simple way to figure out if a
transfer should happen right away (in the current microframe) or should
happen at the start of the next microframe. Said another way:
- If you set "odd" and the current frame number is odd it appears that
the controller will try to transfer right away. Same thing if you set
"even" and the current frame number is even.
- If the oddness you set and the oddness of the frame number are
_different_, the transfer will be delayed until the frame number
changes.
As I understand it, the above technique allows you to plan ahead of time
where possible by always working on the next frame. ...but it still
allows you to properly respond immediately to things that happened in
the previous frame.
The old dwc2_hc_set_even_odd_frame() didn't really handle this concept.
It always looked at the frame number and setup the transfer to happen in
the next frame. In some cases that meant that certain transactions
would be transferred in the wrong frame.
We'll try our best to set the even / odd to do the transfer in the
scheduled frame. If that fails then we'll do an ugly "schedule ASAP".
We'll also modify the scheduler code to handle this and not try to
schedule a second transfer for the same frame.
Note that this change relies on the work to redo the microframe
scheduler. It can work atop ("usb: dwc2: host: Manage frame nums better
in scheduler") but it works even better after ("usb: dwc2: host: Totally
redo the microframe scheduler").
With this change my stressful USB test (USB webcam + USB audio +
keyboards) has less audio crackling than before.
Acked-by: John Youn <johnyoun@synopsys.com>
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Tested-by: Heiko Stuebner <heiko@sntech.de>
Tested-by: Stefan Wahren <stefan.wahren@i2se.com>
Signed-off-by: Felipe Balbi <balbi@kernel.org>
This commit is contained in:
Douglas Anderson
Felipe Balbi
Родитель
fae4e82609
Коммит
9cf1a601d2
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@ -1703,9 +1703,97 @@ static void dwc2_hc_set_even_odd_frame(struct dwc2_hsotg *hsotg,
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{
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if (chan->ep_type == USB_ENDPOINT_XFER_INT ||
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chan->ep_type == USB_ENDPOINT_XFER_ISOC) {
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/* 1 if _next_ frame is odd, 0 if it's even */
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if (!(dwc2_hcd_get_frame_number(hsotg) & 0x1))
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int host_speed;
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int xfer_ns;
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int xfer_us;
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int bytes_in_fifo;
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u16 fifo_space;
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u16 frame_number;
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u16 wire_frame;
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/*
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* Try to figure out if we're an even or odd frame. If we set
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* even and the current frame number is even the the transfer
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* will happen immediately. Similar if both are odd. If one is
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* even and the other is odd then the transfer will happen when
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* the frame number ticks.
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*
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* There's a bit of a balancing act to get this right.
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* Sometimes we may want to send data in the current frame (AK
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* right away). We might want to do this if the frame number
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* _just_ ticked, but we might also want to do this in order
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* to continue a split transaction that happened late in a
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* microframe (so we didn't know to queue the next transfer
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* until the frame number had ticked). The problem is that we
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* need a lot of knowledge to know if there's actually still
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* time to send things or if it would be better to wait until
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* the next frame.
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*
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* We can look at how much time is left in the current frame
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* and make a guess about whether we'll have time to transfer.
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* We'll do that.
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*/
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/* Get speed host is running at */
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host_speed = (chan->speed != USB_SPEED_HIGH &&
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!chan->do_split) ? chan->speed : USB_SPEED_HIGH;
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/* See how many bytes are in the periodic FIFO right now */
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fifo_space = (dwc2_readl(hsotg->regs + HPTXSTS) &
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TXSTS_FSPCAVAIL_MASK) >> TXSTS_FSPCAVAIL_SHIFT;
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bytes_in_fifo = sizeof(u32) *
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(hsotg->core_params->host_perio_tx_fifo_size -
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fifo_space);
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/*
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* Roughly estimate bus time for everything in the periodic
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* queue + our new transfer. This is "rough" because we're
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* using a function that makes takes into account IN/OUT
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* and INT/ISO and we're just slamming in one value for all
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* transfers. This should be an over-estimate and that should
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* be OK, but we can probably tighten it.
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*/
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xfer_ns = usb_calc_bus_time(host_speed, false, false,
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chan->xfer_len + bytes_in_fifo);
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xfer_us = NS_TO_US(xfer_ns);
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/* See what frame number we'll be at by the time we finish */
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frame_number = dwc2_hcd_get_future_frame_number(hsotg, xfer_us);
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/* This is when we were scheduled to be on the wire */
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wire_frame = dwc2_frame_num_inc(chan->qh->next_active_frame, 1);
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/*
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* If we'd finish _after_ the frame we're scheduled in then
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* it's hopeless. Just schedule right away and hope for the
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* best. Note that it _might_ be wise to call back into the
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* scheduler to pick a better frame, but this is better than
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* nothing.
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*/
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if (dwc2_frame_num_gt(frame_number, wire_frame)) {
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dwc2_sch_vdbg(hsotg,
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"QH=%p EO MISS fr=%04x=>%04x (%+d)\n",
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chan->qh, wire_frame, frame_number,
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dwc2_frame_num_dec(frame_number,
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wire_frame));
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wire_frame = frame_number;
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/*
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* We picked a different frame number; communicate this
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* back to the scheduler so it doesn't try to schedule
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* another in the same frame.
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*
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* Remember that next_active_frame is 1 before the wire
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* frame.
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*/
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chan->qh->next_active_frame =
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dwc2_frame_num_dec(frame_number, 1);
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}
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if (wire_frame & 1)
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*hcchar |= HCCHAR_ODDFRM;
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else
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*hcchar &= ~HCCHAR_ODDFRM;
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}
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}
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@ -985,6 +985,14 @@ static int dwc2_next_periodic_start(struct dwc2_hsotg *hsotg,
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* and next_active_frame are always 1 frame before we want things
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* to be active and we assume we can still get scheduled in the
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* current frame number.
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* - It's possible for start_active_frame (now incremented) to be
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* next_active_frame if we got an EO MISS (even_odd miss) which
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* basically means that we detected there wasn't enough time for
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* the last packet and dwc2_hc_set_even_odd_frame() rescheduled us
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* at the last second. We want to make sure we don't schedule
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* another transfer for the same frame. My test webcam doesn't seem
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* terribly upset by missing a transfer but really doesn't like when
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* we do two transfers in the same frame.
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* - Some misses are expected. Specifically, in order to work
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* perfectly dwc2 really needs quite spectacular interrupt latency
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* requirements. It needs to be able to handle its interrupts
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@ -995,7 +1003,8 @@ static int dwc2_next_periodic_start(struct dwc2_hsotg *hsotg,
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* guarantee that a system will have interrupt latency < 125 us, so
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* we have to be robust to some misses.
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*/
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if (dwc2_frame_num_gt(prev_frame_number, qh->start_active_frame)) {
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if (qh->start_active_frame == qh->next_active_frame ||
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dwc2_frame_num_gt(prev_frame_number, qh->start_active_frame)) {
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u16 ideal_start = qh->start_active_frame;
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/* Adjust interval as per gcd with plan length. */
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