drm/amd/display: Partition DPCD address space and break up transactions
[WHY] SCR for DP 2.0 spec says that multiple LTTPRs must not be accessed in a single AUX transaction. There may be other places in future where breaking up AUX accesses is necessary. [HOW] Partition the entire DPCD address space into blocks. When an incoming AUX request spans multiple blocks, break up the request into multiple requests. Signed-off-by: Wesley Chalmers <Wesley.Chalmers@amd.com> Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Anson Jacob <Anson.Jacob@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Wesley Chalmers
Alex Deucher
Родитель
95ad72f4ad
Коммит
9cf9498f66
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@ -43,6 +43,60 @@ static enum dc_status internal_link_write_dpcd(
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return DC_OK;
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}
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/*
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* Partition the entire DPCD address space
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* XXX: This partitioning must cover the entire DPCD address space,
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* and must contain no gaps or overlapping address ranges.
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*/
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static const struct dpcd_address_range mandatory_dpcd_partitions[] = {
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{ 0, DP_TRAINING_PATTERN_SET_PHY_REPEATER(DP_PHY_LTTPR1) - 1},
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{ DP_TRAINING_PATTERN_SET_PHY_REPEATER(DP_PHY_LTTPR1), DP_TRAINING_PATTERN_SET_PHY_REPEATER(DP_PHY_LTTPR2) - 1 },
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{ DP_TRAINING_PATTERN_SET_PHY_REPEATER(DP_PHY_LTTPR2), DP_TRAINING_PATTERN_SET_PHY_REPEATER(DP_PHY_LTTPR3) - 1 },
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{ DP_TRAINING_PATTERN_SET_PHY_REPEATER(DP_PHY_LTTPR3), DP_TRAINING_PATTERN_SET_PHY_REPEATER(DP_PHY_LTTPR4) - 1 },
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{ DP_TRAINING_PATTERN_SET_PHY_REPEATER(DP_PHY_LTTPR4), DP_TRAINING_PATTERN_SET_PHY_REPEATER(DP_PHY_LTTPR5) - 1 },
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{ DP_TRAINING_PATTERN_SET_PHY_REPEATER(DP_PHY_LTTPR5), DP_TRAINING_PATTERN_SET_PHY_REPEATER(DP_PHY_LTTPR6) - 1 },
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{ DP_TRAINING_PATTERN_SET_PHY_REPEATER(DP_PHY_LTTPR6), DP_TRAINING_PATTERN_SET_PHY_REPEATER(DP_PHY_LTTPR7) - 1 },
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{ DP_TRAINING_PATTERN_SET_PHY_REPEATER(DP_PHY_LTTPR7), DP_TRAINING_PATTERN_SET_PHY_REPEATER(DP_PHY_LTTPR8) - 1 },
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{ DP_TRAINING_PATTERN_SET_PHY_REPEATER(DP_PHY_LTTPR8), DP_FEC_STATUS_PHY_REPEATER(DP_PHY_LTTPR1) - 1 },
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/*
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* The FEC registers are contiguous
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*/
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{ DP_FEC_STATUS_PHY_REPEATER(DP_PHY_LTTPR1), DP_FEC_STATUS_PHY_REPEATER(DP_PHY_LTTPR1) - 1 },
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{ DP_FEC_STATUS_PHY_REPEATER(DP_PHY_LTTPR2), DP_FEC_STATUS_PHY_REPEATER(DP_PHY_LTTPR2) - 1 },
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{ DP_FEC_STATUS_PHY_REPEATER(DP_PHY_LTTPR3), DP_FEC_STATUS_PHY_REPEATER(DP_PHY_LTTPR3) - 1 },
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{ DP_FEC_STATUS_PHY_REPEATER(DP_PHY_LTTPR4), DP_FEC_STATUS_PHY_REPEATER(DP_PHY_LTTPR4) - 1 },
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{ DP_FEC_STATUS_PHY_REPEATER(DP_PHY_LTTPR5), DP_FEC_STATUS_PHY_REPEATER(DP_PHY_LTTPR5) - 1 },
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{ DP_FEC_STATUS_PHY_REPEATER(DP_PHY_LTTPR6), DP_FEC_STATUS_PHY_REPEATER(DP_PHY_LTTPR6) - 1 },
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{ DP_FEC_STATUS_PHY_REPEATER(DP_PHY_LTTPR7), DP_FEC_STATUS_PHY_REPEATER(DP_PHY_LTTPR7) - 1 },
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{ DP_FEC_STATUS_PHY_REPEATER(DP_PHY_LTTPR8), DP_LTTPR_MAX_ADD },
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/* all remaining DPCD addresses */
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{ DP_LTTPR_MAX_ADD + 1, DP_DPCD_MAX_ADD } };
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static inline bool do_addresses_intersect_with_range(
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const struct dpcd_address_range *range,
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const uint32_t start_address,
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const uint32_t end_address)
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{
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return start_address <= range->end && end_address >= range->start;
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}
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static uint32_t dpcd_get_next_partition_size(const uint32_t address, const uint32_t size)
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{
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const uint32_t end_address = END_ADDRESS(address, size);
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uint32_t partition_iterator = 0;
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/*
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* find current partition
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* this loop spins forever if partition map above is not surjective
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*/
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while (!do_addresses_intersect_with_range(&mandatory_dpcd_partitions[partition_iterator],
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address, end_address))
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partition_iterator++;
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if (end_address < mandatory_dpcd_partitions[partition_iterator].end)
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return size;
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return ADDRESS_RANGE_SIZE(address, mandatory_dpcd_partitions[partition_iterator].end);
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}
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/*
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* Ranges of DPCD addresses that must be read in a single transaction
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* XXX: Do not allow any two address ranges in this array to overlap
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@ -115,12 +169,28 @@ enum dc_status core_link_read_dpcd(
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uint32_t size)
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{
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uint32_t extended_address;
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uint32_t partitioned_address;
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uint8_t *extended_data;
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uint32_t extended_size;
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/* size of the remaining partitioned address space */
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uint32_t size_left_to_read;
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enum dc_status status;
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/* size of the next partition to be read from */
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uint32_t partition_size;
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uint32_t data_index = 0;
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dpcd_extend_address_range(address, data, size, &extended_address, &extended_data, &extended_size);
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status = internal_link_read_dpcd(link, extended_address, extended_data, extended_size);
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partitioned_address = extended_address;
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size_left_to_read = extended_size;
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while (size_left_to_read) {
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partition_size = dpcd_get_next_partition_size(partitioned_address, size_left_to_read);
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status = internal_link_read_dpcd(link, partitioned_address, &extended_data[data_index], partition_size);
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if (status != DC_OK)
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break;
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partitioned_address += partition_size;
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data_index += partition_size;
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size_left_to_read -= partition_size;
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}
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dpcd_reduce_address_range(extended_address, extended_data, extended_size, address, data, size);
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return status;
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}
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@ -131,5 +201,18 @@ enum dc_status core_link_write_dpcd(
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const uint8_t *data,
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uint32_t size)
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{
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return internal_link_write_dpcd(link, address, data, size);
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uint32_t partition_size;
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uint32_t data_index = 0;
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enum dc_status status;
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while (size) {
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partition_size = dpcd_get_next_partition_size(address, size);
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status = internal_link_write_dpcd(link, address, &data[data_index], partition_size);
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if (status != DC_OK)
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break;
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address += partition_size;
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data_index += partition_size;
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size -= partition_size;
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}
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return status;
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}
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@ -1377,10 +1377,27 @@ enum drm_dp_phy {
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#define DP_SYMBOL_ERROR_COUNT_LANE1_PHY_REPEATER1 0xf0037 /* 1.3 */
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#define DP_SYMBOL_ERROR_COUNT_LANE2_PHY_REPEATER1 0xf0039 /* 1.3 */
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#define DP_SYMBOL_ERROR_COUNT_LANE3_PHY_REPEATER1 0xf003b /* 1.3 */
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#define __DP_FEC1_BASE 0xf0290 /* 1.4 */
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#define __DP_FEC2_BASE 0xf0298 /* 1.4 */
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#define DP_FEC_BASE(dp_phy) \
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(__DP_FEC1_BASE + ((__DP_FEC2_BASE - __DP_FEC1_BASE) * \
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((dp_phy) - DP_PHY_LTTPR1)))
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#define DP_FEC_REG(dp_phy, fec1_reg) \
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(DP_FEC_BASE(dp_phy) - DP_FEC_BASE(DP_PHY_LTTPR1) + fec1_reg)
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#define DP_FEC_STATUS_PHY_REPEATER1 0xf0290 /* 1.4 */
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#define DP_FEC_STATUS_PHY_REPEATER(dp_phy) \
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DP_FEC_REG(dp_phy, DP_FEC_STATUS_PHY_REPEATER1)
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#define DP_FEC_ERROR_COUNT_PHY_REPEATER1 0xf0291 /* 1.4 */
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#define DP_FEC_CAPABILITY_PHY_REPEATER1 0xf0294 /* 1.4a */
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#define DP_LTTPR_MAX_ADD 0xf02ff /* 1.4 */
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#define DP_DPCD_MAX_ADD 0xfffff /* 1.4 */
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/* Repeater modes */
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#define DP_PHY_REPEATER_MODE_TRANSPARENT 0x55 /* 1.3 */
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#define DP_PHY_REPEATER_MODE_NON_TRANSPARENT 0xaa /* 1.3 */
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