Enable atomic64 ops in C6X

- define L1_CACHE_SHIFT
   - select GENERIC_ATOMIC64
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1.4.12 (GNU/Linux)
 
 iQIcBAABAgAGBQJQLk4dAAoJEOiN4VijXeFPPSoP/1rKoqVS46928wdHAFQbFMB2
 0bzU7W9B2NkQ7ZSVPV17qOkMA7N/TUWGYz30llkwLckkPmizQlDr4r4tRxosT38c
 a7jb90Ga8hZDbtNJBnD6GZbP6N0+2wGW/vCnJnOBc9tv5EqLSsoEXyoZrikmwcLN
 bW0/tzIo1B6S7FJPJq1fuZx42Ed6JgBAlWeieEYQvVdi5f8GAxLo4gOGP9rTwDkw
 sRipkLjniruuSPpTvP2OwI47kRmmbTjbSG+RSt9oWIniuP18EUUTE3aGU6NUcen4
 CzxRc4YpsfPoZPNs6QzOuU60abXNvqCSrYQ7AWfJqFwPpXyYzIiuOc/NolsO06cQ
 vdImlf5UUZPVfLUSMVsLtsJElosxUowYYa4912nRdiucOraVBmZlPOMRdwXNKQvU
 1PW7WH/b1VhawBENQzWzRU5w8Q4kDRu6J+xTx4UJUc0XTQ3Jhk+BU3uok5e3bMQM
 F1Pt6dWlafrFQhDTAKDaz9tX/xZRxt4ML3kIgBcB5XGFx09YrXsnmiktmEuYJd+Z
 QGa5gb+1PUgj6m6yWhOLcwT0tdL7AAeCOA53zTMC6NVEjfau7JvWtUiR/daeBiQa
 AOQVcDVGcIHwsM9BrKu2AcdSGNdW2dSD6SRwSAPAKSCcBiL05q18Q3k4bPj4/3KV
 vUrI160WeI2SwwaCTt5M
 =VtQY
 -----END PGP SIGNATURE-----

Merge tag 'for-linus' of git://linux-c6x.org/git/projects/linux-c6x-upstreaming

Pull C6X atomic64 support from Mark Salter:
 "Enable atomic64 ops in C6X
   - define L1_CACHE_SHIFT
   - select GENERIC_ATOMIC64"

* tag 'for-linus' of git://linux-c6x.org/git/projects/linux-c6x-upstreaming:
  C6X: select GENERIC_ATOMIC64
  C6X: add Lx_CACHE_SHIFT defines

arch/c6x/Kconfig

@@ -6,6 +6,7 @@
 config C6X
 	def_bool y
 	select CLKDEV_LOOKUP
+	select GENERIC_ATOMIC64
 	select GENERIC_IRQ_SHOW
 	select HAVE_ARCH_TRACEHOOK
 	select HAVE_DMA_API_DEBUG

arch/c6x/include/asm/cache.h

@@ -1,7 +1,7 @@
 /*
  *  Port on Texas Instruments TMS320C6x architecture
  *
- *  Copyright (C) 2005, 2006, 2009, 2010 Texas Instruments Incorporated
+ *  Copyright (C) 2005, 2006, 2009, 2010, 2012 Texas Instruments Incorporated
  *  Author: Aurelien Jacquiot (aurelien.jacquiot@jaluna.com)
  *
  *  This program is free software; you can redistribute it and/or modify
@@ -16,9 +16,14 @@
 /*
  * Cache line size
  */
-#define L1D_CACHE_BYTES   64
-#define L1P_CACHE_BYTES   32
-#define L2_CACHE_BYTES	  128
+#define L1D_CACHE_SHIFT   6
+#define L1D_CACHE_BYTES   (1 << L1D_CACHE_SHIFT)
+
+#define L1P_CACHE_SHIFT   5
+#define L1P_CACHE_BYTES   (1 << L1P_CACHE_SHIFT)
+
+#define L2_CACHE_SHIFT    7
+#define L2_CACHE_BYTES    (1 << L2_CACHE_SHIFT)
 
 /*
  * L2 used as cache
@@ -29,7 +34,8 @@
  * For practical reasons the L1_CACHE_BYTES defines should not be smaller than
  * the L2 line size
  */
-#define L1_CACHE_BYTES        L2_CACHE_BYTES
+#define L1_CACHE_SHIFT        L2_CACHE_SHIFT
+#define L1_CACHE_BYTES        (1 << L1_CACHE_SHIFT)
 
 #define L2_CACHE_ALIGN_LOW(x) \
 	(((x) & ~(L2_CACHE_BYTES - 1)))