spi: dw: revisit FIFO size detection again
The commitd297933cc7
(spi: dw: Fix detecting FIFO depth) tries to fix the logic of the FIFO detection based on the description on the comments. However, there is a slight difference between numbers in TX Level and TX FIFO size. So, by specification the FIFO size would be in a range 2-256 bytes. From TX Level prospective it means we can set threshold in the range 0-(FIFO size - 1) bytes. Hence there are currently two issues: a) FIFO size 2 bytes is actually skipped since TX Level is 1 bit and could be either 0 or 1 byte; b) FIFO size is incorrectly decreased by 1 which already done by meaning of TX Level register. This patch fixes it eventually right. Fixes:d297933cc7
(spi: dw: Fix detecting FIFO depth) Reviewed-by: Axel Lin <axel.lin@ingics.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Mark Brown <broonie@kernel.org> Cc: stable@vger.kernel.org
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307ed83c8c
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9d239d353c
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@ -621,14 +621,14 @@ static void spi_hw_init(struct device *dev, struct dw_spi *dws)
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if (!dws->fifo_len) {
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u32 fifo;
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for (fifo = 2; fifo <= 256; fifo++) {
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for (fifo = 1; fifo < 256; fifo++) {
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dw_writew(dws, DW_SPI_TXFLTR, fifo);
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if (fifo != dw_readw(dws, DW_SPI_TXFLTR))
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break;
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}
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dw_writew(dws, DW_SPI_TXFLTR, 0);
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dws->fifo_len = (fifo == 2) ? 0 : fifo - 1;
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dws->fifo_len = (fifo == 1) ? 0 : fifo;
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dev_dbg(dev, "Detected FIFO size: %u bytes\n", dws->fifo_len);
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}
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}
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