[TG3]: Add TG3_FLG2_IS_NIC flag.
Add Tg3_FLG2_IS_NIC flag to unambiguously determine whether the device is NIC or onboard. Previously, the EEPROM_WRITE_PROT flag was overloaded to also mean onboard. With the separation, we can support some devices that are onboard but do not use eeprom write protect. Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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676917d488
Коммит
9d26e21342
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@ -1062,7 +1062,7 @@ static void tg3_frob_aux_power(struct tg3 *tp)
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{
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{
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struct tg3 *tp_peer = tp;
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struct tg3 *tp_peer = tp;
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if ((tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) != 0)
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if ((tp->tg3_flags2 & TG3_FLG2_IS_NIC) == 0)
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return;
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return;
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if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
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if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
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@ -1213,8 +1213,8 @@ static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
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power_control);
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power_control);
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udelay(100); /* Delay after power state change */
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udelay(100); /* Delay after power state change */
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/* Switch out of Vaux if it is not a LOM */
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/* Switch out of Vaux if it is a NIC */
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if (!(tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
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if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
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tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
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tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
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return 0;
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return 0;
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@ -6397,16 +6397,17 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
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udelay(40);
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udelay(40);
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/* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
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/* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
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* If TG3_FLAG_EEPROM_WRITE_PROT is set, we should read the
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* If TG3_FLG2_IS_NIC is zero, we should read the
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* register to preserve the GPIO settings for LOMs. The GPIOs,
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* register to preserve the GPIO settings for LOMs. The GPIOs,
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* whether used as inputs or outputs, are set by boot code after
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* whether used as inputs or outputs, are set by boot code after
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* reset.
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* reset.
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*/
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*/
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if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
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if (!(tp->tg3_flags2 & TG3_FLG2_IS_NIC)) {
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u32 gpio_mask;
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u32 gpio_mask;
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gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE2 |
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gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
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GRC_LCLCTRL_GPIO_OUTPUT0 | GRC_LCLCTRL_GPIO_OUTPUT2;
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GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
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GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
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if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
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if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
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gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
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gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
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@ -6418,8 +6419,9 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
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tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
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tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
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/* GPIO1 must be driven high for eeprom write protect */
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/* GPIO1 must be driven high for eeprom write protect */
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tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
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if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT)
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GRC_LCLCTRL_GPIO_OUTPUT1);
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tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
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GRC_LCLCTRL_GPIO_OUTPUT1);
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}
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}
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tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
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tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
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udelay(100);
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udelay(100);
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@ -9963,8 +9965,10 @@ static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
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tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
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tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
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if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
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if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
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if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM))
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if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
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tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
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tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
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tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
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}
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return;
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return;
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}
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}
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@ -10064,10 +10068,17 @@ static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
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tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
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tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
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tp->led_ctrl = LED_CTRL_MODE_PHY_2;
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tp->led_ctrl = LED_CTRL_MODE_PHY_2;
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if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP)
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if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
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tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
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tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
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else
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if ((tp->pdev->subsystem_vendor ==
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PCI_VENDOR_ID_ARIMA) &&
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(tp->pdev->subsystem_device == 0x205a ||
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tp->pdev->subsystem_device == 0x2063))
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tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
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} else {
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tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
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tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
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tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
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}
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if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
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if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
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tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
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tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
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@ -10693,7 +10704,7 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
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tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
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tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
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/* Get eeprom hw config before calling tg3_set_power_state().
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/* Get eeprom hw config before calling tg3_set_power_state().
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* In particular, the TG3_FLAG_EEPROM_WRITE_PROT flag must be
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* In particular, the TG3_FLG2_IS_NIC flag must be
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* determined before calling tg3_set_power_state() so that
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* determined before calling tg3_set_power_state() so that
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* we know whether or not to switch out of Vaux power.
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* we know whether or not to switch out of Vaux power.
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* When the flag is set, it means that GPIO1 is used for eeprom
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* When the flag is set, it means that GPIO1 is used for eeprom
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@ -2233,6 +2233,7 @@ struct tg3 {
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#define TG3_FLG2_PCI_EXPRESS 0x00000200
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#define TG3_FLG2_PCI_EXPRESS 0x00000200
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#define TG3_FLG2_ASF_NEW_HANDSHAKE 0x00000400
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#define TG3_FLG2_ASF_NEW_HANDSHAKE 0x00000400
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#define TG3_FLG2_HW_AUTONEG 0x00000800
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#define TG3_FLG2_HW_AUTONEG 0x00000800
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#define TG3_FLG2_IS_NIC 0x00001000
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#define TG3_FLG2_PHY_SERDES 0x00002000
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#define TG3_FLG2_PHY_SERDES 0x00002000
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#define TG3_FLG2_CAPACITIVE_COUPLING 0x00004000
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#define TG3_FLG2_CAPACITIVE_COUPLING 0x00004000
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#define TG3_FLG2_FLASH 0x00008000
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#define TG3_FLG2_FLASH 0x00008000
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@ -2003,6 +2003,8 @@
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#define PCI_DEVICE_ID_FARSITE_TE1 0x1610
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#define PCI_DEVICE_ID_FARSITE_TE1 0x1610
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#define PCI_DEVICE_ID_FARSITE_TE1C 0x1612
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#define PCI_DEVICE_ID_FARSITE_TE1C 0x1612
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#define PCI_VENDOR_ID_ARIMA 0x161f
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#define PCI_VENDOR_ID_SIBYTE 0x166d
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#define PCI_VENDOR_ID_SIBYTE 0x166d
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#define PCI_DEVICE_ID_BCM1250_PCI 0x0001
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#define PCI_DEVICE_ID_BCM1250_PCI 0x0001
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#define PCI_DEVICE_ID_BCM1250_HT 0x0002
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#define PCI_DEVICE_ID_BCM1250_HT 0x0002
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