i2o: Fix 32/64bit DMA locking
The I2O ioctls assume 32bits. In itself that is fine as they are old cards and nobody uses 64bit. However on LKML it was noted this assumption is also made for allocated memory and is unsafe on 64bit systems. Fixing this is a mess. It turns out there is tons of crap buried in a header file that does racy 32/64bit filtering on the masks. So we: - Verify all callers of the racy code can sleep (i2o_dma_[re]alloc) - Move the code into a new i2o/memory.c file - Remove the gfp_mask argument so nobody can try and misuse the function - Wrap a mutex around the problem area (a single mutex is easy to do and none of this is performance relevant) - Switch the remaining problem kmalloc holdout to use i2o_dma_alloc Cc: Markus Lidel <Markus.Lidel@shadowconnect.com> Cc: Vasily Averin <vvs@sw.ru> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
This commit is contained in:
Alan Cox
Linus Torvalds
Родитель
673c0c0038
Коммит
9d793b0bcb
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@ -5,7 +5,7 @@
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# In the future, some of these should be built conditionally.
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#
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i2o_core-y += iop.o driver.o device.o debug.o pci.o exec-osm.o
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i2o_core-y += iop.o driver.o device.o debug.o pci.o exec-osm.o memory.o
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i2o_bus-y += bus-osm.o
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i2o_config-y += config-osm.o
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obj-$(CONFIG_I2O) += i2o_core.o
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@ -467,7 +467,7 @@ int i2o_parm_issue(struct i2o_device *i2o_dev, int cmd, void *oplist,
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res.virt = NULL;
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if (i2o_dma_alloc(dev, &res, reslen, GFP_KERNEL))
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if (i2o_dma_alloc(dev, &res, reslen))
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return -ENOMEM;
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msg = i2o_msg_get_wait(c, I2O_TIMEOUT_MESSAGE_GET);
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@ -388,8 +388,8 @@ static int i2o_exec_lct_notify(struct i2o_controller *c, u32 change_ind)
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dev = &c->pdev->dev;
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if (i2o_dma_realloc
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(dev, &c->dlct, le32_to_cpu(sb->expected_lct_size), GFP_KERNEL))
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if (i2o_dma_realloc(dev, &c->dlct,
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le32_to_cpu(sb->expected_lct_size)))
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return -ENOMEM;
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msg = i2o_msg_get_wait(c, I2O_TIMEOUT_MESSAGE_GET);
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@ -260,7 +260,7 @@ static int i2o_cfg_swdl(unsigned long arg)
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if (IS_ERR(msg))
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return PTR_ERR(msg);
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if (i2o_dma_alloc(&c->pdev->dev, &buffer, fragsize, GFP_KERNEL)) {
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if (i2o_dma_alloc(&c->pdev->dev, &buffer, fragsize)) {
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i2o_msg_nop(c, msg);
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return -ENOMEM;
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}
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@ -339,7 +339,7 @@ static int i2o_cfg_swul(unsigned long arg)
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if (IS_ERR(msg))
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return PTR_ERR(msg);
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if (i2o_dma_alloc(&c->pdev->dev, &buffer, fragsize, GFP_KERNEL)) {
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if (i2o_dma_alloc(&c->pdev->dev, &buffer, fragsize)) {
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i2o_msg_nop(c, msg);
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return -ENOMEM;
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}
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@ -634,9 +634,7 @@ static int i2o_cfg_passthru32(struct file *file, unsigned cmnd,
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sg_size = sg[i].flag_count & 0xffffff;
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p = &(sg_list[sg_index]);
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/* Allocate memory for the transfer */
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if (i2o_dma_alloc
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(&c->pdev->dev, p, sg_size,
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PCI_DMA_BIDIRECTIONAL)) {
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if (i2o_dma_alloc(&c->pdev->dev, p, sg_size)) {
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printk(KERN_DEBUG
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"%s: Could not allocate SG buffer - size = %d buffer number %d of %d\n",
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c->name, sg_size, i, sg_count);
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@ -780,12 +778,11 @@ static int i2o_cfg_passthru(unsigned long arg)
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u32 size = 0;
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u32 reply_size = 0;
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u32 rcode = 0;
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void *sg_list[SG_TABLESIZE];
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struct i2o_dma sg_list[SG_TABLESIZE];
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u32 sg_offset = 0;
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u32 sg_count = 0;
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int sg_index = 0;
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u32 i = 0;
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void *p = NULL;
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i2o_status_block *sb;
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struct i2o_message *msg;
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unsigned int iop;
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@ -842,6 +839,7 @@ static int i2o_cfg_passthru(unsigned long arg)
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memset(sg_list, 0, sizeof(sg_list[0]) * SG_TABLESIZE);
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if (sg_offset) {
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struct sg_simple_element *sg;
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struct i2o_dma *p;
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if (sg_offset * 4 >= size) {
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rcode = -EFAULT;
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@ -871,22 +869,22 @@ static int i2o_cfg_passthru(unsigned long arg)
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goto sg_list_cleanup;
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}
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sg_size = sg[i].flag_count & 0xffffff;
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p = &(sg_list[sg_index]);
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if (i2o_dma_alloc(&c->pdev->dev, p, sg_size)) {
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/* Allocate memory for the transfer */
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p = kmalloc(sg_size, GFP_KERNEL);
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if (!p) {
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printk(KERN_DEBUG
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"%s: Could not allocate SG buffer - size = %d buffer number %d of %d\n",
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c->name, sg_size, i, sg_count);
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rcode = -ENOMEM;
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goto sg_list_cleanup;
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}
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sg_list[sg_index++] = p; // sglist indexed with input frame, not our internal frame.
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sg_index++;
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/* Copy in the user's SG buffer if necessary */
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if (sg[i].
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flag_count & 0x04000000 /*I2O_SGL_FLAGS_DIR */ ) {
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// TODO 64bit fix
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if (copy_from_user
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(p, (void __user *)sg[i].addr_bus,
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(p->virt, (void __user *)sg[i].addr_bus,
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sg_size)) {
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printk(KERN_DEBUG
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"%s: Could not copy SG buf %d FROM user\n",
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@ -895,8 +893,7 @@ static int i2o_cfg_passthru(unsigned long arg)
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goto sg_list_cleanup;
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}
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}
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//TODO 64bit fix
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sg[i].addr_bus = virt_to_bus(p);
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sg[i].addr_bus = p->phys;
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}
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}
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@ -908,7 +905,7 @@ static int i2o_cfg_passthru(unsigned long arg)
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}
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if (sg_offset) {
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u32 rmsg[128];
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u32 rmsg[I2O_OUTBOUND_MSG_FRAME_SIZE];
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/* Copy back the Scatter Gather buffers back to user space */
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u32 j;
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// TODO 64bit fix
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@ -942,11 +939,11 @@ static int i2o_cfg_passthru(unsigned long arg)
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sg_size = sg[j].flag_count & 0xffffff;
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// TODO 64bit fix
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if (copy_to_user
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((void __user *)sg[j].addr_bus, sg_list[j],
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((void __user *)sg[j].addr_bus, sg_list[j].virt,
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sg_size)) {
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printk(KERN_WARNING
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"%s: Could not copy %p TO user %x\n",
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c->name, sg_list[j],
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c->name, sg_list[j].virt,
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sg[j].addr_bus);
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rcode = -EFAULT;
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goto sg_list_cleanup;
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@ -973,7 +970,7 @@ sg_list_cleanup:
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}
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for (i = 0; i < sg_index; i++)
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kfree(sg_list[i]);
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i2o_dma_free(&c->pdev->dev, &sg_list[i]);
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cleanup:
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kfree(reply);
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@ -1004,7 +1004,7 @@ static int i2o_hrt_get(struct i2o_controller *c)
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size = hrt->num_entries * hrt->entry_len << 2;
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if (size > c->hrt.len) {
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if (i2o_dma_realloc(dev, &c->hrt, size, GFP_KERNEL))
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if (i2o_dma_realloc(dev, &c->hrt, size))
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return -ENOMEM;
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else
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hrt = c->hrt.virt;
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@ -0,0 +1,313 @@
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/*
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* Functions to handle I2O memory
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*
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* Pulled from the inlines in i2o headers and uninlined
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*
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#include <linux/module.h>
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#include <linux/i2o.h>
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#include <linux/delay.h>
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#include <linux/string.h>
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#include <linux/slab.h>
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#include "core.h"
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/* Protects our 32/64bit mask switching */
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static DEFINE_MUTEX(mem_lock);
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/**
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* i2o_sg_tablesize - Calculate the maximum number of elements in a SGL
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* @c: I2O controller for which the calculation should be done
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* @body_size: maximum body size used for message in 32-bit words.
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*
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* Return the maximum number of SG elements in a SG list.
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*/
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u16 i2o_sg_tablesize(struct i2o_controller *c, u16 body_size)
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{
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i2o_status_block *sb = c->status_block.virt;
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u16 sg_count =
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(sb->inbound_frame_size - sizeof(struct i2o_message) / 4) -
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body_size;
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if (c->pae_support) {
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/*
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* for 64-bit a SG attribute element must be added and each
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* SG element needs 12 bytes instead of 8.
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*/
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sg_count -= 2;
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sg_count /= 3;
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} else
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sg_count /= 2;
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if (c->short_req && (sg_count > 8))
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sg_count = 8;
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return sg_count;
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}
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EXPORT_SYMBOL_GPL(i2o_sg_tablesize);
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/**
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* i2o_dma_map_single - Map pointer to controller and fill in I2O message.
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* @c: I2O controller
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* @ptr: pointer to the data which should be mapped
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* @size: size of data in bytes
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* @direction: DMA_TO_DEVICE / DMA_FROM_DEVICE
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* @sg_ptr: pointer to the SG list inside the I2O message
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*
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* This function does all necessary DMA handling and also writes the I2O
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* SGL elements into the I2O message. For details on DMA handling see also
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* dma_map_single(). The pointer sg_ptr will only be set to the end of the
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* SG list if the allocation was successful.
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*
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* Returns DMA address which must be checked for failures using
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* dma_mapping_error().
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*/
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dma_addr_t i2o_dma_map_single(struct i2o_controller *c, void *ptr,
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size_t size,
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enum dma_data_direction direction,
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u32 ** sg_ptr)
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{
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u32 sg_flags;
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u32 *mptr = *sg_ptr;
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dma_addr_t dma_addr;
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switch (direction) {
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case DMA_TO_DEVICE:
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sg_flags = 0xd4000000;
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break;
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case DMA_FROM_DEVICE:
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sg_flags = 0xd0000000;
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break;
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default:
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return 0;
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}
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dma_addr = dma_map_single(&c->pdev->dev, ptr, size, direction);
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if (!dma_mapping_error(&c->pdev->dev, dma_addr)) {
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#ifdef CONFIG_I2O_EXT_ADAPTEC_DMA64
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if ((sizeof(dma_addr_t) > 4) && c->pae_support) {
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*mptr++ = cpu_to_le32(0x7C020002);
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*mptr++ = cpu_to_le32(PAGE_SIZE);
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}
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#endif
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*mptr++ = cpu_to_le32(sg_flags | size);
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*mptr++ = cpu_to_le32(i2o_dma_low(dma_addr));
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#ifdef CONFIG_I2O_EXT_ADAPTEC_DMA64
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if ((sizeof(dma_addr_t) > 4) && c->pae_support)
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*mptr++ = cpu_to_le32(i2o_dma_high(dma_addr));
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#endif
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*sg_ptr = mptr;
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}
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return dma_addr;
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}
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EXPORT_SYMBOL_GPL(i2o_dma_map_single);
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/**
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* i2o_dma_map_sg - Map a SG List to controller and fill in I2O message.
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* @c: I2O controller
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* @sg: SG list to be mapped
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* @sg_count: number of elements in the SG list
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* @direction: DMA_TO_DEVICE / DMA_FROM_DEVICE
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* @sg_ptr: pointer to the SG list inside the I2O message
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*
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* This function does all necessary DMA handling and also writes the I2O
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* SGL elements into the I2O message. For details on DMA handling see also
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* dma_map_sg(). The pointer sg_ptr will only be set to the end of the SG
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* list if the allocation was successful.
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*
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* Returns 0 on failure or 1 on success.
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*/
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int i2o_dma_map_sg(struct i2o_controller *c, struct scatterlist *sg,
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int sg_count, enum dma_data_direction direction, u32 ** sg_ptr)
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{
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u32 sg_flags;
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u32 *mptr = *sg_ptr;
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switch (direction) {
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case DMA_TO_DEVICE:
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sg_flags = 0x14000000;
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break;
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case DMA_FROM_DEVICE:
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sg_flags = 0x10000000;
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break;
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default:
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return 0;
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}
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sg_count = dma_map_sg(&c->pdev->dev, sg, sg_count, direction);
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if (!sg_count)
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return 0;
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#ifdef CONFIG_I2O_EXT_ADAPTEC_DMA64
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if ((sizeof(dma_addr_t) > 4) && c->pae_support) {
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*mptr++ = cpu_to_le32(0x7C020002);
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*mptr++ = cpu_to_le32(PAGE_SIZE);
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}
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#endif
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while (sg_count-- > 0) {
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if (!sg_count)
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sg_flags |= 0xC0000000;
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*mptr++ = cpu_to_le32(sg_flags | sg_dma_len(sg));
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*mptr++ = cpu_to_le32(i2o_dma_low(sg_dma_address(sg)));
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#ifdef CONFIG_I2O_EXT_ADAPTEC_DMA64
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if ((sizeof(dma_addr_t) > 4) && c->pae_support)
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*mptr++ = cpu_to_le32(i2o_dma_high(sg_dma_address(sg)));
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#endif
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sg = sg_next(sg);
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}
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*sg_ptr = mptr;
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return 1;
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}
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EXPORT_SYMBOL_GPL(i2o_dma_map_sg);
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/**
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* i2o_dma_alloc - Allocate DMA memory
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* @dev: struct device pointer to the PCI device of the I2O controller
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* @addr: i2o_dma struct which should get the DMA buffer
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* @len: length of the new DMA memory
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*
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* Allocate a coherent DMA memory and write the pointers into addr.
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*
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* Returns 0 on success or -ENOMEM on failure.
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*/
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int i2o_dma_alloc(struct device *dev, struct i2o_dma *addr, size_t len)
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{
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struct pci_dev *pdev = to_pci_dev(dev);
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int dma_64 = 0;
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mutex_lock(&mem_lock);
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if ((sizeof(dma_addr_t) > 4) && (pdev->dma_mask == DMA_64BIT_MASK)) {
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dma_64 = 1;
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if (pci_set_dma_mask(pdev, DMA_32BIT_MASK)) {
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mutex_unlock(&mem_lock);
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return -ENOMEM;
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}
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}
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addr->virt = dma_alloc_coherent(dev, len, &addr->phys, GFP_KERNEL);
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|
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if ((sizeof(dma_addr_t) > 4) && dma_64)
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if (pci_set_dma_mask(pdev, DMA_64BIT_MASK))
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printk(KERN_WARNING "i2o: unable to set 64-bit DMA");
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mutex_unlock(&mem_lock);
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|
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if (!addr->virt)
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return -ENOMEM;
|
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|
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memset(addr->virt, 0, len);
|
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addr->len = len;
|
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|
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return 0;
|
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}
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EXPORT_SYMBOL_GPL(i2o_dma_alloc);
|
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|
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|
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/**
|
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* i2o_dma_free - Free DMA memory
|
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* @dev: struct device pointer to the PCI device of the I2O controller
|
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* @addr: i2o_dma struct which contains the DMA buffer
|
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*
|
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* Free a coherent DMA memory and set virtual address of addr to NULL.
|
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*/
|
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void i2o_dma_free(struct device *dev, struct i2o_dma *addr)
|
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{
|
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if (addr->virt) {
|
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if (addr->phys)
|
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dma_free_coherent(dev, addr->len, addr->virt,
|
||||
addr->phys);
|
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else
|
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kfree(addr->virt);
|
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addr->virt = NULL;
|
||||
}
|
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}
|
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EXPORT_SYMBOL_GPL(i2o_dma_free);
|
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|
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|
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/**
|
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* i2o_dma_realloc - Realloc DMA memory
|
||||
* @dev: struct device pointer to the PCI device of the I2O controller
|
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* @addr: pointer to a i2o_dma struct DMA buffer
|
||||
* @len: new length of memory
|
||||
*
|
||||
* If there was something allocated in the addr, free it first. If len > 0
|
||||
* than try to allocate it and write the addresses back to the addr
|
||||
* structure. If len == 0 set the virtual address to NULL.
|
||||
*
|
||||
* Returns the 0 on success or negative error code on failure.
|
||||
*/
|
||||
int i2o_dma_realloc(struct device *dev, struct i2o_dma *addr, size_t len)
|
||||
{
|
||||
i2o_dma_free(dev, addr);
|
||||
|
||||
if (len)
|
||||
return i2o_dma_alloc(dev, addr, len);
|
||||
|
||||
return 0;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(i2o_dma_realloc);
|
||||
|
||||
/*
|
||||
* i2o_pool_alloc - Allocate an slab cache and mempool
|
||||
* @mempool: pointer to struct i2o_pool to write data into.
|
||||
* @name: name which is used to identify cache
|
||||
* @size: size of each object
|
||||
* @min_nr: minimum number of objects
|
||||
*
|
||||
* First allocates a slab cache with name and size. Then allocates a
|
||||
* mempool which uses the slab cache for allocation and freeing.
|
||||
*
|
||||
* Returns 0 on success or negative error code on failure.
|
||||
*/
|
||||
int i2o_pool_alloc(struct i2o_pool *pool, const char *name,
|
||||
size_t size, int min_nr)
|
||||
{
|
||||
pool->name = kmalloc(strlen(name) + 1, GFP_KERNEL);
|
||||
if (!pool->name)
|
||||
goto exit;
|
||||
strcpy(pool->name, name);
|
||||
|
||||
pool->slab =
|
||||
kmem_cache_create(pool->name, size, 0, SLAB_HWCACHE_ALIGN, NULL);
|
||||
if (!pool->slab)
|
||||
goto free_name;
|
||||
|
||||
pool->mempool = mempool_create_slab_pool(min_nr, pool->slab);
|
||||
if (!pool->mempool)
|
||||
goto free_slab;
|
||||
|
||||
return 0;
|
||||
|
||||
free_slab:
|
||||
kmem_cache_destroy(pool->slab);
|
||||
|
||||
free_name:
|
||||
kfree(pool->name);
|
||||
|
||||
exit:
|
||||
return -ENOMEM;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(i2o_pool_alloc);
|
||||
|
||||
/*
|
||||
* i2o_pool_free - Free slab cache and mempool again
|
||||
* @mempool: pointer to struct i2o_pool which should be freed
|
||||
*
|
||||
* Note that you have to return all objects to the mempool again before
|
||||
* calling i2o_pool_free().
|
||||
*/
|
||||
void i2o_pool_free(struct i2o_pool *pool)
|
||||
{
|
||||
mempool_destroy(pool->mempool);
|
||||
kmem_cache_destroy(pool->slab);
|
||||
kfree(pool->name);
|
||||
};
|
||||
EXPORT_SYMBOL_GPL(i2o_pool_free);
|
||||
|
|
@ -186,31 +186,29 @@ static int __devinit i2o_pci_alloc(struct i2o_controller *c)
|
|||
}
|
||||
}
|
||||
|
||||
if (i2o_dma_alloc(dev, &c->status, 8, GFP_KERNEL)) {
|
||||
if (i2o_dma_alloc(dev, &c->status, 8)) {
|
||||
i2o_pci_free(c);
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
if (i2o_dma_alloc(dev, &c->hrt, sizeof(i2o_hrt), GFP_KERNEL)) {
|
||||
if (i2o_dma_alloc(dev, &c->hrt, sizeof(i2o_hrt))) {
|
||||
i2o_pci_free(c);
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
if (i2o_dma_alloc(dev, &c->dlct, 8192, GFP_KERNEL)) {
|
||||
if (i2o_dma_alloc(dev, &c->dlct, 8192)) {
|
||||
i2o_pci_free(c);
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
if (i2o_dma_alloc(dev, &c->status_block, sizeof(i2o_status_block),
|
||||
GFP_KERNEL)) {
|
||||
if (i2o_dma_alloc(dev, &c->status_block, sizeof(i2o_status_block))) {
|
||||
i2o_pci_free(c);
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
if (i2o_dma_alloc
|
||||
(dev, &c->out_queue,
|
||||
I2O_MAX_OUTBOUND_MSG_FRAMES * I2O_OUTBOUND_MSG_FRAME_SIZE *
|
||||
sizeof(u32), GFP_KERNEL)) {
|
||||
if (i2o_dma_alloc(dev, &c->out_queue,
|
||||
I2O_MAX_OUTBOUND_MSG_FRAMES * I2O_OUTBOUND_MSG_FRAME_SIZE *
|
||||
sizeof(u32))) {
|
||||
i2o_pci_free(c);
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -570,7 +570,6 @@ struct i2o_controller {
|
|||
#endif
|
||||
spinlock_t lock; /* lock for controller
|
||||
configuration */
|
||||
|
||||
void *driver_data[I2O_MAX_DRIVERS]; /* storage for drivers */
|
||||
};
|
||||
|
||||
|
|
@ -691,289 +690,22 @@ static inline u32 i2o_dma_high(dma_addr_t dma_addr)
|
|||
};
|
||||
#endif
|
||||
|
||||
/**
|
||||
* i2o_sg_tablesize - Calculate the maximum number of elements in a SGL
|
||||
* @c: I2O controller for which the calculation should be done
|
||||
* @body_size: maximum body size used for message in 32-bit words.
|
||||
*
|
||||
* Return the maximum number of SG elements in a SG list.
|
||||
*/
|
||||
static inline u16 i2o_sg_tablesize(struct i2o_controller *c, u16 body_size)
|
||||
{
|
||||
i2o_status_block *sb = c->status_block.virt;
|
||||
u16 sg_count =
|
||||
(sb->inbound_frame_size - sizeof(struct i2o_message) / 4) -
|
||||
body_size;
|
||||
|
||||
if (c->pae_support) {
|
||||
/*
|
||||
* for 64-bit a SG attribute element must be added and each
|
||||
* SG element needs 12 bytes instead of 8.
|
||||
*/
|
||||
sg_count -= 2;
|
||||
sg_count /= 3;
|
||||
} else
|
||||
sg_count /= 2;
|
||||
|
||||
if (c->short_req && (sg_count > 8))
|
||||
sg_count = 8;
|
||||
|
||||
return sg_count;
|
||||
};
|
||||
|
||||
/**
|
||||
* i2o_dma_map_single - Map pointer to controller and fill in I2O message.
|
||||
* @c: I2O controller
|
||||
* @ptr: pointer to the data which should be mapped
|
||||
* @size: size of data in bytes
|
||||
* @direction: DMA_TO_DEVICE / DMA_FROM_DEVICE
|
||||
* @sg_ptr: pointer to the SG list inside the I2O message
|
||||
*
|
||||
* This function does all necessary DMA handling and also writes the I2O
|
||||
* SGL elements into the I2O message. For details on DMA handling see also
|
||||
* dma_map_single(). The pointer sg_ptr will only be set to the end of the
|
||||
* SG list if the allocation was successful.
|
||||
*
|
||||
* Returns DMA address which must be checked for failures using
|
||||
* dma_mapping_error().
|
||||
*/
|
||||
static inline dma_addr_t i2o_dma_map_single(struct i2o_controller *c, void *ptr,
|
||||
extern u16 i2o_sg_tablesize(struct i2o_controller *c, u16 body_size);
|
||||
extern dma_addr_t i2o_dma_map_single(struct i2o_controller *c, void *ptr,
|
||||
size_t size,
|
||||
enum dma_data_direction direction,
|
||||
u32 ** sg_ptr)
|
||||
{
|
||||
u32 sg_flags;
|
||||
u32 *mptr = *sg_ptr;
|
||||
dma_addr_t dma_addr;
|
||||
|
||||
switch (direction) {
|
||||
case DMA_TO_DEVICE:
|
||||
sg_flags = 0xd4000000;
|
||||
break;
|
||||
case DMA_FROM_DEVICE:
|
||||
sg_flags = 0xd0000000;
|
||||
break;
|
||||
default:
|
||||
return 0;
|
||||
}
|
||||
|
||||
dma_addr = dma_map_single(&c->pdev->dev, ptr, size, direction);
|
||||
if (!dma_mapping_error(&c->pdev->dev, dma_addr)) {
|
||||
#ifdef CONFIG_I2O_EXT_ADAPTEC_DMA64
|
||||
if ((sizeof(dma_addr_t) > 4) && c->pae_support) {
|
||||
*mptr++ = cpu_to_le32(0x7C020002);
|
||||
*mptr++ = cpu_to_le32(PAGE_SIZE);
|
||||
}
|
||||
#endif
|
||||
|
||||
*mptr++ = cpu_to_le32(sg_flags | size);
|
||||
*mptr++ = cpu_to_le32(i2o_dma_low(dma_addr));
|
||||
#ifdef CONFIG_I2O_EXT_ADAPTEC_DMA64
|
||||
if ((sizeof(dma_addr_t) > 4) && c->pae_support)
|
||||
*mptr++ = cpu_to_le32(i2o_dma_high(dma_addr));
|
||||
#endif
|
||||
*sg_ptr = mptr;
|
||||
}
|
||||
return dma_addr;
|
||||
};
|
||||
|
||||
/**
|
||||
* i2o_dma_map_sg - Map a SG List to controller and fill in I2O message.
|
||||
* @c: I2O controller
|
||||
* @sg: SG list to be mapped
|
||||
* @sg_count: number of elements in the SG list
|
||||
* @direction: DMA_TO_DEVICE / DMA_FROM_DEVICE
|
||||
* @sg_ptr: pointer to the SG list inside the I2O message
|
||||
*
|
||||
* This function does all necessary DMA handling and also writes the I2O
|
||||
* SGL elements into the I2O message. For details on DMA handling see also
|
||||
* dma_map_sg(). The pointer sg_ptr will only be set to the end of the SG
|
||||
* list if the allocation was successful.
|
||||
*
|
||||
* Returns 0 on failure or 1 on success.
|
||||
*/
|
||||
static inline int i2o_dma_map_sg(struct i2o_controller *c,
|
||||
u32 ** sg_ptr);
|
||||
extern int i2o_dma_map_sg(struct i2o_controller *c,
|
||||
struct scatterlist *sg, int sg_count,
|
||||
enum dma_data_direction direction,
|
||||
u32 ** sg_ptr)
|
||||
{
|
||||
u32 sg_flags;
|
||||
u32 *mptr = *sg_ptr;
|
||||
|
||||
switch (direction) {
|
||||
case DMA_TO_DEVICE:
|
||||
sg_flags = 0x14000000;
|
||||
break;
|
||||
case DMA_FROM_DEVICE:
|
||||
sg_flags = 0x10000000;
|
||||
break;
|
||||
default:
|
||||
return 0;
|
||||
}
|
||||
|
||||
sg_count = dma_map_sg(&c->pdev->dev, sg, sg_count, direction);
|
||||
if (!sg_count)
|
||||
return 0;
|
||||
|
||||
#ifdef CONFIG_I2O_EXT_ADAPTEC_DMA64
|
||||
if ((sizeof(dma_addr_t) > 4) && c->pae_support) {
|
||||
*mptr++ = cpu_to_le32(0x7C020002);
|
||||
*mptr++ = cpu_to_le32(PAGE_SIZE);
|
||||
}
|
||||
#endif
|
||||
|
||||
while (sg_count-- > 0) {
|
||||
if (!sg_count)
|
||||
sg_flags |= 0xC0000000;
|
||||
*mptr++ = cpu_to_le32(sg_flags | sg_dma_len(sg));
|
||||
*mptr++ = cpu_to_le32(i2o_dma_low(sg_dma_address(sg)));
|
||||
#ifdef CONFIG_I2O_EXT_ADAPTEC_DMA64
|
||||
if ((sizeof(dma_addr_t) > 4) && c->pae_support)
|
||||
*mptr++ = cpu_to_le32(i2o_dma_high(sg_dma_address(sg)));
|
||||
#endif
|
||||
sg = sg_next(sg);
|
||||
}
|
||||
*sg_ptr = mptr;
|
||||
|
||||
return 1;
|
||||
};
|
||||
|
||||
/**
|
||||
* i2o_dma_alloc - Allocate DMA memory
|
||||
* @dev: struct device pointer to the PCI device of the I2O controller
|
||||
* @addr: i2o_dma struct which should get the DMA buffer
|
||||
* @len: length of the new DMA memory
|
||||
* @gfp_mask: GFP mask
|
||||
*
|
||||
* Allocate a coherent DMA memory and write the pointers into addr.
|
||||
*
|
||||
* Returns 0 on success or -ENOMEM on failure.
|
||||
*/
|
||||
static inline int i2o_dma_alloc(struct device *dev, struct i2o_dma *addr,
|
||||
size_t len, gfp_t gfp_mask)
|
||||
{
|
||||
struct pci_dev *pdev = to_pci_dev(dev);
|
||||
int dma_64 = 0;
|
||||
|
||||
if ((sizeof(dma_addr_t) > 4) && (pdev->dma_mask == DMA_64BIT_MASK)) {
|
||||
dma_64 = 1;
|
||||
if (pci_set_dma_mask(pdev, DMA_32BIT_MASK))
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
addr->virt = dma_alloc_coherent(dev, len, &addr->phys, gfp_mask);
|
||||
|
||||
if ((sizeof(dma_addr_t) > 4) && dma_64)
|
||||
if (pci_set_dma_mask(pdev, DMA_64BIT_MASK))
|
||||
printk(KERN_WARNING "i2o: unable to set 64-bit DMA");
|
||||
|
||||
if (!addr->virt)
|
||||
return -ENOMEM;
|
||||
|
||||
memset(addr->virt, 0, len);
|
||||
addr->len = len;
|
||||
|
||||
return 0;
|
||||
};
|
||||
|
||||
/**
|
||||
* i2o_dma_free - Free DMA memory
|
||||
* @dev: struct device pointer to the PCI device of the I2O controller
|
||||
* @addr: i2o_dma struct which contains the DMA buffer
|
||||
*
|
||||
* Free a coherent DMA memory and set virtual address of addr to NULL.
|
||||
*/
|
||||
static inline void i2o_dma_free(struct device *dev, struct i2o_dma *addr)
|
||||
{
|
||||
if (addr->virt) {
|
||||
if (addr->phys)
|
||||
dma_free_coherent(dev, addr->len, addr->virt,
|
||||
addr->phys);
|
||||
else
|
||||
kfree(addr->virt);
|
||||
addr->virt = NULL;
|
||||
}
|
||||
};
|
||||
|
||||
/**
|
||||
* i2o_dma_realloc - Realloc DMA memory
|
||||
* @dev: struct device pointer to the PCI device of the I2O controller
|
||||
* @addr: pointer to a i2o_dma struct DMA buffer
|
||||
* @len: new length of memory
|
||||
* @gfp_mask: GFP mask
|
||||
*
|
||||
* If there was something allocated in the addr, free it first. If len > 0
|
||||
* than try to allocate it and write the addresses back to the addr
|
||||
* structure. If len == 0 set the virtual address to NULL.
|
||||
*
|
||||
* Returns the 0 on success or negative error code on failure.
|
||||
*/
|
||||
static inline int i2o_dma_realloc(struct device *dev, struct i2o_dma *addr,
|
||||
size_t len, gfp_t gfp_mask)
|
||||
{
|
||||
i2o_dma_free(dev, addr);
|
||||
|
||||
if (len)
|
||||
return i2o_dma_alloc(dev, addr, len, gfp_mask);
|
||||
|
||||
return 0;
|
||||
};
|
||||
|
||||
/*
|
||||
* i2o_pool_alloc - Allocate an slab cache and mempool
|
||||
* @mempool: pointer to struct i2o_pool to write data into.
|
||||
* @name: name which is used to identify cache
|
||||
* @size: size of each object
|
||||
* @min_nr: minimum number of objects
|
||||
*
|
||||
* First allocates a slab cache with name and size. Then allocates a
|
||||
* mempool which uses the slab cache for allocation and freeing.
|
||||
*
|
||||
* Returns 0 on success or negative error code on failure.
|
||||
*/
|
||||
static inline int i2o_pool_alloc(struct i2o_pool *pool, const char *name,
|
||||
size_t size, int min_nr)
|
||||
{
|
||||
pool->name = kmalloc(strlen(name) + 1, GFP_KERNEL);
|
||||
if (!pool->name)
|
||||
goto exit;
|
||||
strcpy(pool->name, name);
|
||||
|
||||
pool->slab =
|
||||
kmem_cache_create(pool->name, size, 0, SLAB_HWCACHE_ALIGN, NULL);
|
||||
if (!pool->slab)
|
||||
goto free_name;
|
||||
|
||||
pool->mempool = mempool_create_slab_pool(min_nr, pool->slab);
|
||||
if (!pool->mempool)
|
||||
goto free_slab;
|
||||
|
||||
return 0;
|
||||
|
||||
free_slab:
|
||||
kmem_cache_destroy(pool->slab);
|
||||
|
||||
free_name:
|
||||
kfree(pool->name);
|
||||
|
||||
exit:
|
||||
return -ENOMEM;
|
||||
};
|
||||
|
||||
/*
|
||||
* i2o_pool_free - Free slab cache and mempool again
|
||||
* @mempool: pointer to struct i2o_pool which should be freed
|
||||
*
|
||||
* Note that you have to return all objects to the mempool again before
|
||||
* calling i2o_pool_free().
|
||||
*/
|
||||
static inline void i2o_pool_free(struct i2o_pool *pool)
|
||||
{
|
||||
mempool_destroy(pool->mempool);
|
||||
kmem_cache_destroy(pool->slab);
|
||||
kfree(pool->name);
|
||||
};
|
||||
|
||||
u32 ** sg_ptr);
|
||||
extern int i2o_dma_alloc(struct device *dev, struct i2o_dma *addr, size_t len);
|
||||
extern void i2o_dma_free(struct device *dev, struct i2o_dma *addr);
|
||||
extern int i2o_dma_realloc(struct device *dev, struct i2o_dma *addr,
|
||||
size_t len);
|
||||
extern int i2o_pool_alloc(struct i2o_pool *pool, const char *name,
|
||||
size_t size, int min_nr);
|
||||
extern void i2o_pool_free(struct i2o_pool *pool);
|
||||
/* I2O driver (OSM) functions */
|
||||
extern int i2o_driver_register(struct i2o_driver *);
|
||||
extern void i2o_driver_unregister(struct i2o_driver *);
|
||||
|
|
|
|||
Загрузка…
Ссылка в новой задаче