ARM: KVM: VGIC virtual CPU interface management
Add VGIC virtual CPU interface code, picking pending interrupts from the distributor and stashing them in the VGIC control interface list registers. Reviewed-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Christoffer Dall <c.dall@virtualopensystems.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
This commit is contained in:
Marc Zyngier
Родитель
b47ef92af8
Коммит
9d949dce52
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@ -33,6 +33,7 @@
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#define VGIC_NR_PRIVATE_IRQS (VGIC_NR_SGIS + VGIC_NR_PPIS)
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#define VGIC_NR_SHARED_IRQS (VGIC_NR_IRQS - VGIC_NR_PRIVATE_IRQS)
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#define VGIC_MAX_CPUS KVM_MAX_VCPUS
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#define VGIC_MAX_LRS (1 << 6)
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/* Sanity checks... */
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#if (VGIC_MAX_CPUS > 8)
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@ -110,8 +111,33 @@ struct vgic_dist {
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};
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struct vgic_cpu {
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#ifdef CONFIG_KVM_ARM_VGIC
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/* per IRQ to LR mapping */
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u8 vgic_irq_lr_map[VGIC_NR_IRQS];
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/* Pending interrupts on this VCPU */
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DECLARE_BITMAP( pending_percpu, VGIC_NR_PRIVATE_IRQS);
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DECLARE_BITMAP( pending_shared, VGIC_NR_SHARED_IRQS);
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/* Bitmap of used/free list registers */
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DECLARE_BITMAP( lr_used, VGIC_MAX_LRS);
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/* Number of list registers on this CPU */
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int nr_lr;
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/* CPU vif control registers for world switch */
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u32 vgic_hcr;
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u32 vgic_vmcr;
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u32 vgic_misr; /* Saved only */
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u32 vgic_eisr[2]; /* Saved only */
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u32 vgic_elrsr[2]; /* Saved only */
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u32 vgic_apr;
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u32 vgic_lr[VGIC_MAX_LRS];
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#endif
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};
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#define LR_EMPTY 0xff
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struct kvm;
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struct kvm_vcpu;
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struct kvm_run;
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@ -119,9 +145,14 @@ struct kvm_exit_mmio;
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#ifdef CONFIG_KVM_ARM_VGIC
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int kvm_vgic_set_addr(struct kvm *kvm, unsigned long type, u64 addr);
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void kvm_vgic_flush_hwstate(struct kvm_vcpu *vcpu);
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void kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu);
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int kvm_vgic_vcpu_pending_irq(struct kvm_vcpu *vcpu);
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bool vgic_handle_mmio(struct kvm_vcpu *vcpu, struct kvm_run *run,
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struct kvm_exit_mmio *mmio);
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#define irqchip_in_kernel(k) (!!((k)->arch.vgic.vctrl_base))
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#else
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static inline int kvm_vgic_hyp_init(void)
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{
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@ -152,6 +152,34 @@ static int vgic_irq_is_enabled(struct kvm_vcpu *vcpu, int irq)
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return vgic_bitmap_get_irq_val(&dist->irq_enabled, vcpu->vcpu_id, irq);
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}
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static int vgic_irq_is_active(struct kvm_vcpu *vcpu, int irq)
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{
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struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
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return vgic_bitmap_get_irq_val(&dist->irq_active, vcpu->vcpu_id, irq);
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}
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static void vgic_irq_set_active(struct kvm_vcpu *vcpu, int irq)
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{
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struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
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vgic_bitmap_set_irq_val(&dist->irq_active, vcpu->vcpu_id, irq, 1);
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}
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static void vgic_irq_clear_active(struct kvm_vcpu *vcpu, int irq)
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{
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struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
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vgic_bitmap_set_irq_val(&dist->irq_active, vcpu->vcpu_id, irq, 0);
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}
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static int vgic_dist_irq_is_pending(struct kvm_vcpu *vcpu, int irq)
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{
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struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
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return vgic_bitmap_get_irq_val(&dist->irq_state, vcpu->vcpu_id, irq);
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}
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static void vgic_dist_irq_set(struct kvm_vcpu *vcpu, int irq)
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{
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struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
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@ -723,7 +751,30 @@ static void vgic_dispatch_sgi(struct kvm_vcpu *vcpu, u32 reg)
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static int compute_pending_for_cpu(struct kvm_vcpu *vcpu)
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{
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return 0;
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struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
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unsigned long *pending, *enabled, *pend_percpu, *pend_shared;
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unsigned long pending_private, pending_shared;
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int vcpu_id;
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vcpu_id = vcpu->vcpu_id;
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pend_percpu = vcpu->arch.vgic_cpu.pending_percpu;
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pend_shared = vcpu->arch.vgic_cpu.pending_shared;
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pending = vgic_bitmap_get_cpu_map(&dist->irq_state, vcpu_id);
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enabled = vgic_bitmap_get_cpu_map(&dist->irq_enabled, vcpu_id);
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bitmap_and(pend_percpu, pending, enabled, VGIC_NR_PRIVATE_IRQS);
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pending = vgic_bitmap_get_shared_map(&dist->irq_state);
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enabled = vgic_bitmap_get_shared_map(&dist->irq_enabled);
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bitmap_and(pend_shared, pending, enabled, VGIC_NR_SHARED_IRQS);
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bitmap_and(pend_shared, pend_shared,
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vgic_bitmap_get_shared_map(&dist->irq_spi_target[vcpu_id]),
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VGIC_NR_SHARED_IRQS);
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pending_private = find_first_bit(pend_percpu, VGIC_NR_PRIVATE_IRQS);
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pending_shared = find_first_bit(pend_shared, VGIC_NR_SHARED_IRQS);
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return (pending_private < VGIC_NR_PRIVATE_IRQS ||
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pending_shared < VGIC_NR_SHARED_IRQS);
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}
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/*
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@ -749,6 +800,280 @@ static void vgic_update_state(struct kvm *kvm)
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}
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}
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#define LR_CPUID(lr) \
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(((lr) & GICH_LR_PHYSID_CPUID) >> GICH_LR_PHYSID_CPUID_SHIFT)
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#define MK_LR_PEND(src, irq) \
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(GICH_LR_PENDING_BIT | ((src) << GICH_LR_PHYSID_CPUID_SHIFT) | (irq))
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/*
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* Queue an interrupt to a CPU virtual interface. Return true on success,
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* or false if it wasn't possible to queue it.
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*/
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static bool vgic_queue_irq(struct kvm_vcpu *vcpu, u8 sgi_source_id, int irq)
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{
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struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
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int lr;
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/* Sanitize the input... */
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BUG_ON(sgi_source_id & ~7);
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BUG_ON(sgi_source_id && irq >= VGIC_NR_SGIS);
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BUG_ON(irq >= VGIC_NR_IRQS);
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kvm_debug("Queue IRQ%d\n", irq);
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lr = vgic_cpu->vgic_irq_lr_map[irq];
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/* Do we have an active interrupt for the same CPUID? */
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if (lr != LR_EMPTY &&
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(LR_CPUID(vgic_cpu->vgic_lr[lr]) == sgi_source_id)) {
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kvm_debug("LR%d piggyback for IRQ%d %x\n",
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lr, irq, vgic_cpu->vgic_lr[lr]);
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BUG_ON(!test_bit(lr, vgic_cpu->lr_used));
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vgic_cpu->vgic_lr[lr] |= GICH_LR_PENDING_BIT;
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goto out;
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}
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/* Try to use another LR for this interrupt */
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lr = find_first_zero_bit((unsigned long *)vgic_cpu->lr_used,
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vgic_cpu->nr_lr);
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if (lr >= vgic_cpu->nr_lr)
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return false;
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kvm_debug("LR%d allocated for IRQ%d %x\n", lr, irq, sgi_source_id);
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vgic_cpu->vgic_lr[lr] = MK_LR_PEND(sgi_source_id, irq);
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vgic_cpu->vgic_irq_lr_map[irq] = lr;
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set_bit(lr, vgic_cpu->lr_used);
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out:
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if (!vgic_irq_is_edge(vcpu, irq))
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vgic_cpu->vgic_lr[lr] |= GICH_LR_EOI;
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return true;
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}
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static bool vgic_queue_sgi(struct kvm_vcpu *vcpu, int irq)
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{
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struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
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unsigned long sources;
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int vcpu_id = vcpu->vcpu_id;
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int c;
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sources = dist->irq_sgi_sources[vcpu_id][irq];
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for_each_set_bit(c, &sources, VGIC_MAX_CPUS) {
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if (vgic_queue_irq(vcpu, c, irq))
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clear_bit(c, &sources);
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}
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dist->irq_sgi_sources[vcpu_id][irq] = sources;
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/*
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* If the sources bitmap has been cleared it means that we
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* could queue all the SGIs onto link registers (see the
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* clear_bit above), and therefore we are done with them in
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* our emulated gic and can get rid of them.
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*/
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if (!sources) {
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vgic_dist_irq_clear(vcpu, irq);
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vgic_cpu_irq_clear(vcpu, irq);
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return true;
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}
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return false;
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}
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static bool vgic_queue_hwirq(struct kvm_vcpu *vcpu, int irq)
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{
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if (vgic_irq_is_active(vcpu, irq))
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return true; /* level interrupt, already queued */
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if (vgic_queue_irq(vcpu, 0, irq)) {
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if (vgic_irq_is_edge(vcpu, irq)) {
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vgic_dist_irq_clear(vcpu, irq);
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vgic_cpu_irq_clear(vcpu, irq);
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} else {
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vgic_irq_set_active(vcpu, irq);
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}
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return true;
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}
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return false;
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}
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/*
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* Fill the list registers with pending interrupts before running the
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* guest.
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*/
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static void __kvm_vgic_flush_hwstate(struct kvm_vcpu *vcpu)
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{
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struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
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struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
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int i, vcpu_id;
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int overflow = 0;
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vcpu_id = vcpu->vcpu_id;
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/*
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* We may not have any pending interrupt, or the interrupts
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* may have been serviced from another vcpu. In all cases,
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* move along.
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*/
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if (!kvm_vgic_vcpu_pending_irq(vcpu)) {
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pr_debug("CPU%d has no pending interrupt\n", vcpu_id);
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goto epilog;
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}
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/* SGIs */
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for_each_set_bit(i, vgic_cpu->pending_percpu, VGIC_NR_SGIS) {
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if (!vgic_queue_sgi(vcpu, i))
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overflow = 1;
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}
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/* PPIs */
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for_each_set_bit_from(i, vgic_cpu->pending_percpu, VGIC_NR_PRIVATE_IRQS) {
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if (!vgic_queue_hwirq(vcpu, i))
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overflow = 1;
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}
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/* SPIs */
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for_each_set_bit(i, vgic_cpu->pending_shared, VGIC_NR_SHARED_IRQS) {
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if (!vgic_queue_hwirq(vcpu, i + VGIC_NR_PRIVATE_IRQS))
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overflow = 1;
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}
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epilog:
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if (overflow) {
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vgic_cpu->vgic_hcr |= GICH_HCR_UIE;
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} else {
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vgic_cpu->vgic_hcr &= ~GICH_HCR_UIE;
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/*
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* We're about to run this VCPU, and we've consumed
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* everything the distributor had in store for
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* us. Claim we don't have anything pending. We'll
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* adjust that if needed while exiting.
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*/
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clear_bit(vcpu_id, &dist->irq_pending_on_cpu);
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}
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}
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static bool vgic_process_maintenance(struct kvm_vcpu *vcpu)
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{
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struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
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bool level_pending = false;
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kvm_debug("MISR = %08x\n", vgic_cpu->vgic_misr);
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/*
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* We do not need to take the distributor lock here, since the only
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* action we perform is clearing the irq_active_bit for an EOIed
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* level interrupt. There is a potential race with
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* the queuing of an interrupt in __kvm_vgic_flush_hwstate(), where we
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* check if the interrupt is already active. Two possibilities:
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*
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* - The queuing is occurring on the same vcpu: cannot happen,
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* as we're already in the context of this vcpu, and
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* executing the handler
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* - The interrupt has been migrated to another vcpu, and we
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* ignore this interrupt for this run. Big deal. It is still
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* pending though, and will get considered when this vcpu
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* exits.
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*/
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if (vgic_cpu->vgic_misr & GICH_MISR_EOI) {
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/*
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* Some level interrupts have been EOIed. Clear their
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* active bit.
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*/
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int lr, irq;
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for_each_set_bit(lr, (unsigned long *)vgic_cpu->vgic_eisr,
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vgic_cpu->nr_lr) {
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irq = vgic_cpu->vgic_lr[lr] & GICH_LR_VIRTUALID;
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vgic_irq_clear_active(vcpu, irq);
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vgic_cpu->vgic_lr[lr] &= ~GICH_LR_EOI;
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/* Any additional pending interrupt? */
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if (vgic_dist_irq_is_pending(vcpu, irq)) {
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vgic_cpu_irq_set(vcpu, irq);
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level_pending = true;
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} else {
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vgic_cpu_irq_clear(vcpu, irq);
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}
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}
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}
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if (vgic_cpu->vgic_misr & GICH_MISR_U)
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vgic_cpu->vgic_hcr &= ~GICH_HCR_UIE;
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return level_pending;
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}
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/*
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* Sync back the VGIC state after a guest run. We do not really touch
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* the distributor here (the irq_pending_on_cpu bit is safe to set),
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* so there is no need for taking its lock.
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*/
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static void __kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu)
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{
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struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
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struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
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int lr, pending;
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bool level_pending;
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level_pending = vgic_process_maintenance(vcpu);
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/* Clear mappings for empty LRs */
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for_each_set_bit(lr, (unsigned long *)vgic_cpu->vgic_elrsr,
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vgic_cpu->nr_lr) {
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int irq;
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if (!test_and_clear_bit(lr, vgic_cpu->lr_used))
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continue;
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irq = vgic_cpu->vgic_lr[lr] & GICH_LR_VIRTUALID;
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BUG_ON(irq >= VGIC_NR_IRQS);
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vgic_cpu->vgic_irq_lr_map[irq] = LR_EMPTY;
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}
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/* Check if we still have something up our sleeve... */
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pending = find_first_zero_bit((unsigned long *)vgic_cpu->vgic_elrsr,
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vgic_cpu->nr_lr);
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if (level_pending || pending < vgic_cpu->nr_lr)
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set_bit(vcpu->vcpu_id, &dist->irq_pending_on_cpu);
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}
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void kvm_vgic_flush_hwstate(struct kvm_vcpu *vcpu)
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{
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struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
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if (!irqchip_in_kernel(vcpu->kvm))
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return;
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spin_lock(&dist->lock);
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__kvm_vgic_flush_hwstate(vcpu);
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spin_unlock(&dist->lock);
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}
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void kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu)
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{
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if (!irqchip_in_kernel(vcpu->kvm))
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return;
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__kvm_vgic_sync_hwstate(vcpu);
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}
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int kvm_vgic_vcpu_pending_irq(struct kvm_vcpu *vcpu)
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{
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struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
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if (!irqchip_in_kernel(vcpu->kvm))
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return 0;
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return test_bit(vcpu->vcpu_id, &dist->irq_pending_on_cpu);
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}
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static bool vgic_ioaddr_overlap(struct kvm *kvm)
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{
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phys_addr_t dist = kvm->arch.vgic.vgic_dist_base;
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