arm/mx5: add device tree support for imx51 babbage
It adds device tree support for imx51 babbage board. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Acked-by: Grant Likely <grant.likely@secretlab.ca> Acked-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This commit is contained in:
Shawn Guo
Sascha Hauer
Родитель
73d2b4cdfc
Коммит
9daaf31a8c
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@ -1,3 +1,7 @@
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i.MX51 Babbage Board
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Required root node properties:
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- compatible = "fsl,imx51-babbage", "fsl,imx51";
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i.MX53 Automotive Reference Design Board
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Required root node properties:
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- compatible = "fsl,imx53-ard", "fsl,imx53";
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@ -0,0 +1,135 @@
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/*
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* Copyright 2011 Freescale Semiconductor, Inc.
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* Copyright 2011 Linaro Ltd.
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*
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* The code contained herein is licensed under the GNU General Public
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* License. You may obtain a copy of the GNU General Public License
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* Version 2 or later at the following locations:
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*
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* http://www.opensource.org/licenses/gpl-license.html
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* http://www.gnu.org/copyleft/gpl.html
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*/
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/dts-v1/;
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/include/ "imx51.dtsi"
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/ {
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model = "Freescale i.MX51 Babbage Board";
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compatible = "fsl,imx51-babbage", "fsl,imx51";
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chosen {
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bootargs = "console=ttymxc0,115200 root=/dev/mmcblk0p3 rootwait";
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};
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memory {
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reg = <0x90000000 0x20000000>;
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};
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soc {
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aips@70000000 { /* aips-1 */
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spba@70000000 {
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esdhc@70004000 { /* ESDHC1 */
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fsl,cd-internal;
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fsl,wp-internal;
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status = "okay";
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};
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esdhc@70008000 { /* ESDHC2 */
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cd-gpios = <&gpio0 6 0>; /* GPIO1_6 */
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wp-gpios = <&gpio0 5 0>; /* GPIO1_5 */
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status = "okay";
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};
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uart2: uart@7000c000 { /* UART3 */
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fsl,uart-has-rtscts;
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status = "okay";
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};
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ecspi@70010000 { /* ECSPI1 */
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fsl,spi-num-chipselects = <2>;
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cs-gpios = <&gpio3 24 0>, /* GPIO4_24 */
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<&gpio3 25 0>; /* GPIO4_25 */
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status = "okay";
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pmic: mc13892@0 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,mc13892";
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spi-max-frequency = <6000000>;
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reg = <0>;
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mc13xxx-irq-gpios = <&gpio0 8 0>; /* GPIO1_8 */
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fsl,mc13xxx-uses-regulator;
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};
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flash: at45db321d@1 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "atmel,at45db321d", "atmel,at45", "atmel,dataflash";
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spi-max-frequency = <25000000>;
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reg = <1>;
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partition@0 {
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label = "U-Boot";
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reg = <0x0 0x40000>;
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read-only;
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};
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partition@40000 {
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label = "Kernel";
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reg = <0x40000 0x3c0000>;
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};
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};
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};
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};
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wdog@73f98000 { /* WDOG1 */
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status = "okay";
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};
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iomuxc@73fa8000 {
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compatible = "fsl,imx51-iomuxc-babbage";
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reg = <0x73fa8000 0x4000>;
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};
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uart0: uart@73fbc000 {
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fsl,uart-has-rtscts;
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status = "okay";
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};
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uart1: uart@73fc0000 {
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status = "okay";
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};
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};
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aips@80000000 { /* aips-2 */
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sdma@83fb0000 {
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fsl,sdma-ram-script-name = "imx/sdma/sdma-imx51.bin";
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};
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i2c@83fc4000 { /* I2C2 */
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status = "okay";
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codec: sgtl5000@0a {
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compatible = "fsl,sgtl5000";
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reg = <0x0a>;
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};
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};
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fec@83fec000 {
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phy-mode = "mii";
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status = "okay";
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};
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};
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};
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gpio-keys {
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compatible = "gpio-keys";
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power {
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label = "Power Button";
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gpios = <&gpio1 21 0>;
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linux,code = <116>; /* KEY_POWER */
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gpio-key,wakeup;
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};
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};
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};
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@ -0,0 +1,246 @@
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/*
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* Copyright 2011 Freescale Semiconductor, Inc.
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* Copyright 2011 Linaro Ltd.
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*
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* The code contained herein is licensed under the GNU General Public
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* License. You may obtain a copy of the GNU General Public License
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* Version 2 or later at the following locations:
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*
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* http://www.opensource.org/licenses/gpl-license.html
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* http://www.gnu.org/copyleft/gpl.html
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*/
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/include/ "skeleton.dtsi"
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/ {
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aliases {
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serial0 = &uart0;
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serial1 = &uart1;
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serial2 = &uart2;
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};
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tzic: tz-interrupt-controller@e0000000 {
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compatible = "fsl,imx51-tzic", "fsl,tzic";
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interrupt-controller;
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#interrupt-cells = <1>;
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reg = <0xe0000000 0x4000>;
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};
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clocks {
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#address-cells = <1>;
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#size-cells = <0>;
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ckil {
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compatible = "fsl,imx-ckil", "fixed-clock";
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clock-frequency = <32768>;
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};
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ckih1 {
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compatible = "fsl,imx-ckih1", "fixed-clock";
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clock-frequency = <22579200>;
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};
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ckih2 {
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compatible = "fsl,imx-ckih2", "fixed-clock";
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clock-frequency = <0>;
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};
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osc {
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compatible = "fsl,imx-osc", "fixed-clock";
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clock-frequency = <24000000>;
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};
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};
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soc {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "simple-bus";
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interrupt-parent = <&tzic>;
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ranges;
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aips@70000000 { /* AIPS1 */
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compatible = "fsl,aips-bus", "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0x70000000 0x10000000>;
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ranges;
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spba@70000000 {
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compatible = "fsl,spba-bus", "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0x70000000 0x40000>;
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ranges;
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esdhc@70004000 { /* ESDHC1 */
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compatible = "fsl,imx51-esdhc";
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reg = <0x70004000 0x4000>;
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interrupts = <1>;
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status = "disabled";
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};
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esdhc@70008000 { /* ESDHC2 */
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compatible = "fsl,imx51-esdhc";
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reg = <0x70008000 0x4000>;
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interrupts = <2>;
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status = "disabled";
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};
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uart2: uart@7000c000 { /* UART3 */
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compatible = "fsl,imx51-uart", "fsl,imx21-uart";
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reg = <0x7000c000 0x4000>;
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interrupts = <33>;
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status = "disabled";
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};
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ecspi@70010000 { /* ECSPI1 */
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,imx51-ecspi";
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reg = <0x70010000 0x4000>;
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interrupts = <36>;
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status = "disabled";
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};
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esdhc@70020000 { /* ESDHC3 */
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compatible = "fsl,imx51-esdhc";
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reg = <0x70020000 0x4000>;
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interrupts = <3>;
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status = "disabled";
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};
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esdhc@70024000 { /* ESDHC4 */
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compatible = "fsl,imx51-esdhc";
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reg = <0x70024000 0x4000>;
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interrupts = <4>;
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status = "disabled";
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};
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};
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gpio0: gpio@73f84000 { /* GPIO1 */
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compatible = "fsl,imx51-gpio", "fsl,imx31-gpio";
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reg = <0x73f84000 0x4000>;
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interrupts = <50 51>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <1>;
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};
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gpio1: gpio@73f88000 { /* GPIO2 */
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compatible = "fsl,imx51-gpio", "fsl,imx31-gpio";
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reg = <0x73f88000 0x4000>;
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interrupts = <52 53>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <1>;
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};
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gpio2: gpio@73f8c000 { /* GPIO3 */
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compatible = "fsl,imx51-gpio", "fsl,imx31-gpio";
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reg = <0x73f8c000 0x4000>;
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interrupts = <54 55>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <1>;
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};
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gpio3: gpio@73f90000 { /* GPIO4 */
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compatible = "fsl,imx51-gpio", "fsl,imx31-gpio";
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reg = <0x73f90000 0x4000>;
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interrupts = <56 57>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <1>;
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};
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wdog@73f98000 { /* WDOG1 */
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compatible = "fsl,imx51-wdt", "fsl,imx21-wdt";
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reg = <0x73f98000 0x4000>;
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interrupts = <58>;
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status = "disabled";
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};
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wdog@73f9c000 { /* WDOG2 */
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compatible = "fsl,imx51-wdt", "fsl,imx21-wdt";
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reg = <0x73f9c000 0x4000>;
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interrupts = <59>;
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status = "disabled";
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};
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uart0: uart@73fbc000 {
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compatible = "fsl,imx51-uart", "fsl,imx21-uart";
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reg = <0x73fbc000 0x4000>;
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interrupts = <31>;
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status = "disabled";
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};
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uart1: uart@73fc0000 {
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compatible = "fsl,imx51-uart", "fsl,imx21-uart";
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reg = <0x73fc0000 0x4000>;
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interrupts = <32>;
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status = "disabled";
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};
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};
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aips@80000000 { /* AIPS2 */
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compatible = "fsl,aips-bus", "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0x80000000 0x10000000>;
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ranges;
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ecspi@83fac000 { /* ECSPI2 */
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,imx51-ecspi";
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reg = <0x83fac000 0x4000>;
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interrupts = <37>;
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status = "disabled";
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};
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sdma@83fb0000 {
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compatible = "fsl,imx51-sdma", "fsl,imx35-sdma";
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reg = <0x83fb0000 0x4000>;
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interrupts = <6>;
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};
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cspi@83fc0000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,imx51-cspi", "fsl,imx35-cspi";
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reg = <0x83fc0000 0x4000>;
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interrupts = <38>;
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status = "disabled";
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};
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i2c@83fc4000 { /* I2C2 */
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,imx51-i2c", "fsl,imx1-i2c";
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reg = <0x83fc4000 0x4000>;
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interrupts = <63>;
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status = "disabled";
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};
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i2c@83fc8000 { /* I2C1 */
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,imx51-i2c", "fsl,imx1-i2c";
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reg = <0x83fc8000 0x4000>;
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interrupts = <62>;
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status = "disabled";
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};
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fec@83fec000 {
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compatible = "fsl,imx51-fec", "fsl,imx27-fec";
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reg = <0x83fec000 0x4000>;
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interrupts = <87>;
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status = "disabled";
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};
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};
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};
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};
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@ -62,6 +62,15 @@ endif # ARCH_MX50_SUPPORTED
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if ARCH_MX51
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comment "i.MX51 machines:"
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config MACH_IMX51_DT
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bool "Support i.MX51 platforms from device tree"
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select SOC_IMX51
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select USE_OF
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select MACH_MX51_BABBAGE
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help
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Include support for Freescale i.MX51 based platforms
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using the device tree for discovery
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config MACH_MX51_BABBAGE
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bool "Support MX51 BABBAGE platforms"
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select SOC_IMX51
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@ -23,4 +23,5 @@ obj-$(CONFIG_MACH_MX51_EFIKAMX) += board-mx51_efikamx.o
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obj-$(CONFIG_MACH_MX51_EFIKASB) += board-mx51_efikasb.o
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obj-$(CONFIG_MACH_MX50_RDP) += board-mx50_rdp.o
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obj-$(CONFIG_MACH_IMX51_DT) += imx51-dt.o
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obj-$(CONFIG_MACH_IMX53_DT) += imx53-dt.o
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@ -351,6 +351,12 @@ static const struct esdhc_platform_data mx51_babbage_sd2_data __initconst = {
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.wp_type = ESDHC_WP_GPIO,
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};
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void __init imx51_babbage_common_init(void)
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{
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mxc_iomux_v3_setup_multiple_pads(mx51babbage_pads,
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ARRAY_SIZE(mx51babbage_pads));
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}
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/*
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* Board specific initialization.
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*/
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@ -365,8 +371,7 @@ static void __init mx51_babbage_init(void)
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#if defined(CONFIG_CPU_FREQ_IMX)
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get_cpu_op = mx51_get_cpu_op;
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#endif
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mxc_iomux_v3_setup_multiple_pads(mx51babbage_pads,
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ARRAY_SIZE(mx51babbage_pads));
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imx51_babbage_common_init();
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imx51_add_imx_uart(0, &uart_pdata);
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imx51_add_imx_uart(1, NULL);
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|
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@ -1633,6 +1633,14 @@ static void __init clk_get_freq_dt(unsigned long *ckil, unsigned long *osc,
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}
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}
|
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|
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int __init mx51_clocks_init_dt(void)
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{
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unsigned long ckil, osc, ckih1, ckih2;
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|
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clk_get_freq_dt(&ckil, &osc, &ckih1, &ckih2);
|
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return mx51_clocks_init(ckil, osc, ckih1, ckih2);
|
||||
}
|
||||
|
||||
int __init mx53_clocks_init_dt(void)
|
||||
{
|
||||
unsigned long ckil, osc, ckih1, ckih2;
|
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|
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|
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|
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@ -0,0 +1,116 @@
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/*
|
||||
* Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved.
|
||||
* Copyright 2011 Linaro Ltd.
|
||||
*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 or later at the following locations:
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
*/
|
||||
|
||||
#include <linux/irq.h>
|
||||
#include <linux/irqdomain.h>
|
||||
#include <linux/of_irq.h>
|
||||
#include <linux/of_platform.h>
|
||||
#include <asm/mach/arch.h>
|
||||
#include <asm/mach/time.h>
|
||||
#include <mach/common.h>
|
||||
#include <mach/mx51.h>
|
||||
|
||||
/*
|
||||
* Lookup table for attaching a specific name and platform_data pointer to
|
||||
* devices as they get created by of_platform_populate(). Ideally this table
|
||||
* would not exist, but the current clock implementation depends on some devices
|
||||
* having a specific name.
|
||||
*/
|
||||
static const struct of_dev_auxdata imx51_auxdata_lookup[] __initconst = {
|
||||
OF_DEV_AUXDATA("fsl,imx51-uart", MX51_UART1_BASE_ADDR, "imx21-uart.0", NULL),
|
||||
OF_DEV_AUXDATA("fsl,imx51-uart", MX51_UART2_BASE_ADDR, "imx21-uart.1", NULL),
|
||||
OF_DEV_AUXDATA("fsl,imx51-uart", MX51_UART3_BASE_ADDR, "imx21-uart.2", NULL),
|
||||
OF_DEV_AUXDATA("fsl,imx51-fec", MX51_FEC_BASE_ADDR, "imx27-fec.0", NULL),
|
||||
OF_DEV_AUXDATA("fsl,imx51-esdhc", MX51_ESDHC1_BASE_ADDR, "sdhci-esdhc-imx51.0", NULL),
|
||||
OF_DEV_AUXDATA("fsl,imx51-esdhc", MX51_ESDHC2_BASE_ADDR, "sdhci-esdhc-imx51.1", NULL),
|
||||
OF_DEV_AUXDATA("fsl,imx51-esdhc", MX51_ESDHC3_BASE_ADDR, "sdhci-esdhc-imx51.2", NULL),
|
||||
OF_DEV_AUXDATA("fsl,imx51-esdhc", MX51_ESDHC4_BASE_ADDR, "sdhci-esdhc-imx51.3", NULL),
|
||||
OF_DEV_AUXDATA("fsl,imx51-ecspi", MX51_ECSPI1_BASE_ADDR, "imx51-ecspi.0", NULL),
|
||||
OF_DEV_AUXDATA("fsl,imx51-ecspi", MX51_ECSPI2_BASE_ADDR, "imx51-ecspi.1", NULL),
|
||||
OF_DEV_AUXDATA("fsl,imx51-cspi", MX51_CSPI_BASE_ADDR, "imx35-cspi.0", NULL),
|
||||
OF_DEV_AUXDATA("fsl,imx51-i2c", MX51_I2C1_BASE_ADDR, "imx-i2c.0", NULL),
|
||||
OF_DEV_AUXDATA("fsl,imx51-i2c", MX51_I2C2_BASE_ADDR, "imx-i2c.1", NULL),
|
||||
OF_DEV_AUXDATA("fsl,imx51-sdma", MX51_SDMA_BASE_ADDR, "imx35-sdma", NULL),
|
||||
OF_DEV_AUXDATA("fsl,imx51-wdt", MX51_WDOG1_BASE_ADDR, "imx2-wdt.0", NULL),
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
|
||||
static void __init imx51_tzic_add_irq_domain(struct device_node *np,
|
||||
struct device_node *interrupt_parent)
|
||||
{
|
||||
irq_domain_add_simple(np, 0);
|
||||
}
|
||||
|
||||
static void __init imx51_gpio_add_irq_domain(struct device_node *np,
|
||||
struct device_node *interrupt_parent)
|
||||
{
|
||||
static int gpio_irq_base = MXC_GPIO_IRQ_START + ARCH_NR_GPIOS -
|
||||
32 * 4; /* imx51 gets 4 gpio ports */
|
||||
|
||||
irq_domain_add_simple(np, gpio_irq_base);
|
||||
gpio_irq_base += 32;
|
||||
}
|
||||
|
||||
static const struct of_device_id imx51_irq_match[] __initconst = {
|
||||
{ .compatible = "fsl,imx51-tzic", .data = imx51_tzic_add_irq_domain, },
|
||||
{ .compatible = "fsl,imx51-gpio", .data = imx51_gpio_add_irq_domain, },
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
|
||||
static const struct of_device_id imx51_iomuxc_of_match[] __initconst = {
|
||||
{ .compatible = "fsl,imx51-iomuxc-babbage", .data = imx51_babbage_common_init, },
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
|
||||
static void __init imx51_dt_init(void)
|
||||
{
|
||||
struct device_node *node;
|
||||
const struct of_device_id *of_id;
|
||||
void (*func)(void);
|
||||
|
||||
of_irq_init(imx51_irq_match);
|
||||
|
||||
node = of_find_matching_node(NULL, imx51_iomuxc_of_match);
|
||||
if (node) {
|
||||
of_id = of_match_node(imx51_iomuxc_of_match, node);
|
||||
func = of_id->data;
|
||||
func();
|
||||
of_node_put(node);
|
||||
}
|
||||
|
||||
of_platform_populate(NULL, of_default_bus_match_table,
|
||||
imx51_auxdata_lookup, NULL);
|
||||
}
|
||||
|
||||
static void __init imx51_timer_init(void)
|
||||
{
|
||||
mx51_clocks_init_dt();
|
||||
}
|
||||
|
||||
static struct sys_timer imx51_timer = {
|
||||
.init = imx51_timer_init,
|
||||
};
|
||||
|
||||
static const char *imx51_dt_board_compat[] __initdata = {
|
||||
"fsl,imx51-babbage",
|
||||
NULL
|
||||
};
|
||||
|
||||
DT_MACHINE_START(IMX51_DT, "Freescale i.MX51 (Device Tree Support)")
|
||||
.map_io = mx51_map_io,
|
||||
.init_early = imx51_init_early,
|
||||
.init_irq = mx51_init_irq,
|
||||
.handle_irq = imx51_handle_irq,
|
||||
.timer = &imx51_timer,
|
||||
.init_machine = imx51_dt_init,
|
||||
.dt_compat = imx51_dt_board_compat,
|
||||
MACHINE_END
|
||||
|
|
@ -64,6 +64,7 @@ extern int mx51_clocks_init(unsigned long ckil, unsigned long osc,
|
|||
unsigned long ckih1, unsigned long ckih2);
|
||||
extern int mx53_clocks_init(unsigned long ckil, unsigned long osc,
|
||||
unsigned long ckih1, unsigned long ckih2);
|
||||
extern int mx51_clocks_init_dt(void);
|
||||
extern int mx53_clocks_init_dt(void);
|
||||
extern struct platform_device *mxc_register_gpio(char *name, int id,
|
||||
resource_size_t iobase, resource_size_t iosize, int irq, int irq_high);
|
||||
|
|
@ -74,6 +75,7 @@ extern void mx51_efikamx_reset(void);
|
|||
extern int mx53_revision(void);
|
||||
extern int mx53_display_revision(void);
|
||||
|
||||
extern void imx51_babbage_common_init(void);
|
||||
extern void imx53_ard_common_init(void);
|
||||
extern void imx53_evk_common_init(void);
|
||||
extern void imx53_qsb_common_init(void);
|
||||
|
|
|
|||
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