Merge branch 'irqchip/mvebu' into irqchip/core
This commit is contained in:
Jason Cooper
Коммит
9df5126b69
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@ -38,6 +38,8 @@
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/* Interrupt Controller Registers Map */
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#define ARMADA_370_XP_INT_SET_MASK_OFFS (0x48)
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#define ARMADA_370_XP_INT_CLEAR_MASK_OFFS (0x4C)
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#define ARMADA_370_XP_INT_FABRIC_MASK_OFFS (0x54)
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#define ARMADA_370_XP_INT_CAUSE_PERF(cpu) (1 << cpu)
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#define ARMADA_370_XP_INT_CONTROL (0x00)
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#define ARMADA_370_XP_INT_SET_ENABLE_OFFS (0x30)
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@ -56,6 +58,7 @@
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#define ARMADA_370_XP_MAX_PER_CPU_IRQS (28)
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#define ARMADA_370_XP_TIMER0_PER_CPU_IRQ (5)
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#define ARMADA_370_XP_FABRIC_IRQ (3)
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#define IPI_DOORBELL_START (0)
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#define IPI_DOORBELL_END (8)
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@ -69,6 +72,7 @@ static void __iomem *per_cpu_int_base;
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static void __iomem *main_int_base;
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static struct irq_domain *armada_370_xp_mpic_domain;
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static u32 doorbell_mask_reg;
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static int parent_irq;
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#ifdef CONFIG_PCI_MSI
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static struct irq_domain *armada_370_xp_msi_domain;
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static DECLARE_BITMAP(msi_used, PCI_MSI_DOORBELL_NR);
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@ -76,6 +80,17 @@ static DEFINE_MUTEX(msi_used_lock);
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static phys_addr_t msi_doorbell_addr;
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#endif
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static inline bool is_percpu_irq(irq_hw_number_t irq)
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{
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switch (irq) {
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case ARMADA_370_XP_TIMER0_PER_CPU_IRQ:
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case ARMADA_370_XP_FABRIC_IRQ:
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return true;
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default:
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return false;
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}
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}
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/*
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* In SMP mode:
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* For shared global interrupts, mask/unmask global enable bit
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@ -85,7 +100,7 @@ static void armada_370_xp_irq_mask(struct irq_data *d)
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{
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irq_hw_number_t hwirq = irqd_to_hwirq(d);
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if (hwirq != ARMADA_370_XP_TIMER0_PER_CPU_IRQ)
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if (!is_percpu_irq(hwirq))
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writel(hwirq, main_int_base +
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ARMADA_370_XP_INT_CLEAR_ENABLE_OFFS);
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else
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@ -97,7 +112,7 @@ static void armada_370_xp_irq_unmask(struct irq_data *d)
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{
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irq_hw_number_t hwirq = irqd_to_hwirq(d);
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if (hwirq != ARMADA_370_XP_TIMER0_PER_CPU_IRQ)
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if (!is_percpu_irq(hwirq))
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writel(hwirq, main_int_base +
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ARMADA_370_XP_INT_SET_ENABLE_OFFS);
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else
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@ -286,14 +301,14 @@ static int armada_370_xp_mpic_irq_map(struct irq_domain *h,
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unsigned int virq, irq_hw_number_t hw)
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{
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armada_370_xp_irq_mask(irq_get_irq_data(virq));
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if (hw != ARMADA_370_XP_TIMER0_PER_CPU_IRQ)
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if (!is_percpu_irq(hw))
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writel(hw, per_cpu_int_base +
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ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
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else
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writel(hw, main_int_base + ARMADA_370_XP_INT_SET_ENABLE_OFFS);
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irq_set_status_flags(virq, IRQ_LEVEL);
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if (hw == ARMADA_370_XP_TIMER0_PER_CPU_IRQ) {
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if (is_percpu_irq(hw)) {
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irq_set_percpu_devid(virq);
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irq_set_chip_and_handler(virq, &armada_370_xp_irq_chip,
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handle_percpu_devid_irq);
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@ -307,28 +322,6 @@ static int armada_370_xp_mpic_irq_map(struct irq_domain *h,
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return 0;
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}
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#ifdef CONFIG_SMP
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static void armada_mpic_send_doorbell(const struct cpumask *mask,
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unsigned int irq)
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{
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int cpu;
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unsigned long map = 0;
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/* Convert our logical CPU mask into a physical one. */
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for_each_cpu(cpu, mask)
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map |= 1 << cpu_logical_map(cpu);
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/*
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* Ensure that stores to Normal memory are visible to the
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* other CPUs before issuing the IPI.
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*/
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dsb();
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/* submit softirq */
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writel((map << 8) | irq, main_int_base +
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ARMADA_370_XP_SW_TRIG_INT_OFFS);
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}
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static void armada_xp_mpic_smp_cpu_init(void)
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{
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u32 control;
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@ -351,11 +344,45 @@ static void armada_xp_mpic_smp_cpu_init(void)
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writel(0, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
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}
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static void armada_xp_mpic_perf_init(void)
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{
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unsigned long cpuid = cpu_logical_map(smp_processor_id());
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/* Enable Performance Counter Overflow interrupts */
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writel(ARMADA_370_XP_INT_CAUSE_PERF(cpuid),
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per_cpu_int_base + ARMADA_370_XP_INT_FABRIC_MASK_OFFS);
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}
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#ifdef CONFIG_SMP
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static void armada_mpic_send_doorbell(const struct cpumask *mask,
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unsigned int irq)
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{
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int cpu;
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unsigned long map = 0;
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/* Convert our logical CPU mask into a physical one. */
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for_each_cpu(cpu, mask)
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map |= 1 << cpu_logical_map(cpu);
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/*
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* Ensure that stores to Normal memory are visible to the
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* other CPUs before issuing the IPI.
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*/
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dsb();
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/* submit softirq */
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writel((map << 8) | irq, main_int_base +
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ARMADA_370_XP_SW_TRIG_INT_OFFS);
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}
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static int armada_xp_mpic_secondary_init(struct notifier_block *nfb,
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unsigned long action, void *hcpu)
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{
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if (action == CPU_STARTING || action == CPU_STARTING_FROZEN)
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if (action == CPU_STARTING || action == CPU_STARTING_FROZEN) {
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armada_xp_mpic_perf_init();
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armada_xp_mpic_smp_cpu_init();
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}
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return NOTIFY_OK;
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}
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@ -364,6 +391,21 @@ static struct notifier_block armada_370_xp_mpic_cpu_notifier = {
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.priority = 100,
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};
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static int mpic_cascaded_secondary_init(struct notifier_block *nfb,
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unsigned long action, void *hcpu)
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{
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if (action == CPU_STARTING || action == CPU_STARTING_FROZEN) {
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armada_xp_mpic_perf_init();
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enable_percpu_irq(parent_irq, IRQ_TYPE_NONE);
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}
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return NOTIFY_OK;
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}
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static struct notifier_block mpic_cascaded_cpu_notifier = {
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.notifier_call = mpic_cascaded_secondary_init,
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.priority = 100,
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};
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#endif /* CONFIG_SMP */
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static struct irq_domain_ops armada_370_xp_mpic_irq_ops = {
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@ -539,7 +581,7 @@ static int __init armada_370_xp_mpic_of_init(struct device_node *node,
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struct device_node *parent)
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{
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struct resource main_int_res, per_cpu_int_res;
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int parent_irq, nr_irqs, i;
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int nr_irqs, i;
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u32 control;
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BUG_ON(of_address_to_resource(node, 0, &main_int_res));
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@ -572,9 +614,9 @@ static int __init armada_370_xp_mpic_of_init(struct device_node *node,
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BUG_ON(!armada_370_xp_mpic_domain);
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#ifdef CONFIG_SMP
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/* Setup for the boot CPU */
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armada_xp_mpic_perf_init();
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armada_xp_mpic_smp_cpu_init();
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#endif
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armada_370_xp_msi_init(node, main_int_res.start);
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@ -587,6 +629,9 @@ static int __init armada_370_xp_mpic_of_init(struct device_node *node,
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register_cpu_notifier(&armada_370_xp_mpic_cpu_notifier);
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#endif
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} else {
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#ifdef CONFIG_SMP
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register_cpu_notifier(&mpic_cascaded_cpu_notifier);
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#endif
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irq_set_chained_handler(parent_irq,
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armada_370_xp_mpic_handle_cascade_irq);
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}
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