drm/radeon/cik: add hw cursor support (v2)
CIK (DCE8) hw cursors are programmed the same as evergreen (DCE4) with the following caveats: - cursors are now 128x128 pixels - new alpha blend enable bit v2: rebase Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -0,0 +1,65 @@
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/*
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* Copyright 2012 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Alex Deucher
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*/
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#ifndef __CIK_REG_H__
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#define __CIK_REG_H__
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#define CIK_DC_GPIO_HPD_MASK 0x65b0
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#define CIK_DC_GPIO_HPD_A 0x65b4
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#define CIK_DC_GPIO_HPD_EN 0x65b8
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#define CIK_DC_GPIO_HPD_Y 0x65bc
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/* CUR blocks at 0x6998, 0x7598, 0x10198, 0x10d98, 0x11998, 0x12598 */
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#define CIK_CUR_CONTROL 0x6998
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# define CIK_CURSOR_EN (1 << 0)
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# define CIK_CURSOR_MODE(x) (((x) & 0x3) << 8)
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# define CIK_CURSOR_MONO 0
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# define CIK_CURSOR_24_1 1
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# define CIK_CURSOR_24_8_PRE_MULT 2
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# define CIK_CURSOR_24_8_UNPRE_MULT 3
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# define CIK_CURSOR_2X_MAGNIFY (1 << 16)
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# define CIK_CURSOR_FORCE_MC_ON (1 << 20)
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# define CIK_CURSOR_URGENT_CONTROL(x) (((x) & 0x7) << 24)
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# define CIK_CURSOR_URGENT_ALWAYS 0
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# define CIK_CURSOR_URGENT_1_8 1
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# define CIK_CURSOR_URGENT_1_4 2
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# define CIK_CURSOR_URGENT_3_8 3
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# define CIK_CURSOR_URGENT_1_2 4
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#define CIK_CUR_SURFACE_ADDRESS 0x699c
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# define CIK_CUR_SURFACE_ADDRESS_MASK 0xfffff000
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#define CIK_CUR_SIZE 0x69a0
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#define CIK_CUR_SURFACE_ADDRESS_HIGH 0x69a4
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#define CIK_CUR_POSITION 0x69a8
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#define CIK_CUR_HOT_SPOT 0x69ac
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#define CIK_CUR_COLOR1 0x69b0
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#define CIK_CUR_COLOR2 0x69b4
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#define CIK_CUR_UPDATE 0x69b8
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# define CIK_CURSOR_UPDATE_PENDING (1 << 0)
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# define CIK_CURSOR_UPDATE_TAKEN (1 << 1)
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# define CIK_CURSOR_UPDATE_LOCK (1 << 16)
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# define CIK_CURSOR_DISABLE_MULTIPLE_UPDATE (1 << 24)
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#define CIK_ALPHA_CONTROL 0x6af0
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# define CIK_CURSOR_ALPHA_BLND_ENA (1 << 1)
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#endif
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@ -150,6 +150,13 @@ extern int radeon_fastfb;
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#define RADEON_RESET_MC (1 << 10)
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#define RADEON_RESET_DISPLAY (1 << 11)
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/* max cursor sizes (in pixels) */
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#define CURSOR_WIDTH 64
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#define CURSOR_HEIGHT 64
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#define CIK_CURSOR_WIDTH 128
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#define CIK_CURSOR_HEIGHT 128
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/*
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* Errata workarounds.
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*/
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@ -27,9 +27,6 @@
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#include <drm/radeon_drm.h>
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#include "radeon.h"
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#define CURSOR_WIDTH 64
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#define CURSOR_HEIGHT 64
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static void radeon_lock_cursor(struct drm_crtc *crtc, bool lock)
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{
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struct radeon_device *rdev = crtc->dev->dev_private;
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@ -167,7 +164,8 @@ int radeon_crtc_cursor_set(struct drm_crtc *crtc,
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goto unpin;
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}
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if ((width > CURSOR_WIDTH) || (height > CURSOR_HEIGHT)) {
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if ((width > radeon_crtc->max_cursor_width) ||
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(height > radeon_crtc->max_cursor_height)) {
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DRM_ERROR("bad cursor width or height %d x %d\n", width, height);
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return -EINVAL;
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}
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@ -233,11 +231,11 @@ int radeon_crtc_cursor_move(struct drm_crtc *crtc,
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DRM_DEBUG("x %d y %d c->x %d c->y %d\n", x, y, crtc->x, crtc->y);
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if (x < 0) {
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xorigin = min(-x, CURSOR_WIDTH - 1);
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xorigin = min(-x, radeon_crtc->max_cursor_width - 1);
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x = 0;
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}
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if (y < 0) {
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yorigin = min(-y, CURSOR_HEIGHT - 1);
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yorigin = min(-y, radeon_crtc->max_cursor_height - 1);
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y = 0;
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}
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@ -153,7 +153,13 @@ static void dce5_crtc_load_lut(struct drm_crtc *crtc)
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NI_OUTPUT_CSC_OVL_MODE(NI_OUTPUT_CSC_BYPASS)));
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/* XXX match this to the depth of the crtc fmt block, move to modeset? */
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WREG32(0x6940 + radeon_crtc->crtc_offset, 0);
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if (ASIC_IS_DCE8(rdev)) {
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/* XXX this only needs to be programmed once per crtc at startup,
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* not sure where the best place for it is
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*/
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WREG32(CIK_ALPHA_CONTROL + radeon_crtc->crtc_offset,
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CIK_CURSOR_ALPHA_BLND_ENA);
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}
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}
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static void legacy_crtc_load_lut(struct drm_crtc *crtc)
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@ -512,6 +518,14 @@ static void radeon_crtc_init(struct drm_device *dev, int index)
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radeon_crtc->crtc_id = index;
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rdev->mode_info.crtcs[index] = radeon_crtc;
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if (rdev->family >= CHIP_BONAIRE) {
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radeon_crtc->max_cursor_width = CIK_CURSOR_WIDTH;
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radeon_crtc->max_cursor_height = CIK_CURSOR_HEIGHT;
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} else {
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radeon_crtc->max_cursor_width = CURSOR_WIDTH;
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radeon_crtc->max_cursor_height = CURSOR_HEIGHT;
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}
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#if 0
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radeon_crtc->mode_set.crtc = &radeon_crtc->base;
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radeon_crtc->mode_set.connectors = (struct drm_connector **)(radeon_crtc + 1);
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@ -307,6 +307,8 @@ struct radeon_crtc {
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uint64_t cursor_addr;
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int cursor_width;
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int cursor_height;
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int max_cursor_width;
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int max_cursor_height;
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uint32_t legacy_display_base_addr;
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uint32_t legacy_cursor_offset;
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enum radeon_rmx_type rmx_type;
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@ -57,6 +57,7 @@
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#include "evergreen_reg.h"
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#include "ni_reg.h"
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#include "si_reg.h"
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#include "cik_reg.h"
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#define RADEON_MC_AGP_LOCATION 0x014c
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#define RADEON_MC_AGP_START_MASK 0x0000FFFF
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