carl9170: update fw/hw headers
This patch syncs up the header files with the project's main firmware carl9170fw.git. Signed-off-by: Christian Lamparter <chunkeey@googlemail.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
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436d0d9853
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9e09b5c96c
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@ -167,6 +167,7 @@ struct carl9170_rx_filter_cmd {
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#define CARL9170_RX_FILTER_CTL_BACKR 0x20
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#define CARL9170_RX_FILTER_MGMT 0x40
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#define CARL9170_RX_FILTER_DATA 0x80
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#define CARL9170_RX_FILTER_EVERYTHING (~0)
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struct carl9170_bcn_ctrl_cmd {
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__le32 vif_id;
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@ -69,6 +69,9 @@ enum carl9170fw_feature_list {
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/* Firmware RX filter | CARL9170_CMD_RX_FILTER */
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CARL9170FW_RX_FILTER,
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/* Wake up on WLAN */
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CARL9170FW_WOL,
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/* KEEP LAST */
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__CARL9170FW_FEATURE_NUM
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};
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@ -78,6 +81,7 @@ enum carl9170fw_feature_list {
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#define FIX_MAGIC "FIX\0"
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#define DBG_MAGIC "DBG\0"
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#define CHK_MAGIC "CHK\0"
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#define TXSQ_MAGIC "TXSQ"
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#define LAST_MAGIC "LAST"
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#define CARL9170FW_SET_DAY(d) (((d) - 1) % 31)
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@ -88,8 +92,10 @@ enum carl9170fw_feature_list {
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#define CARL9170FW_GET_MONTH(m) ((((m) / 31) % 12) + 1)
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#define CARL9170FW_GET_YEAR(y) ((y) / 372 + 10)
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#define CARL9170FW_MAGIC_SIZE 4
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struct carl9170fw_desc_head {
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u8 magic[4];
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u8 magic[CARL9170FW_MAGIC_SIZE];
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__le16 length;
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u8 min_ver;
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u8 cur_ver;
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@ -170,6 +176,16 @@ struct carl9170fw_chk_desc {
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#define CARL9170FW_CHK_DESC_SIZE \
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(sizeof(struct carl9170fw_chk_desc))
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#define CARL9170FW_TXSQ_DESC_MIN_VER 1
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#define CARL9170FW_TXSQ_DESC_CUR_VER 1
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struct carl9170fw_txsq_desc {
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struct carl9170fw_desc_head head;
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__le32 seq_table_addr;
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} __packed;
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#define CARL9170FW_TXSQ_DESC_SIZE \
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(sizeof(struct carl9170fw_txsq_desc))
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#define CARL9170FW_LAST_DESC_MIN_VER 1
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#define CARL9170FW_LAST_DESC_CUR_VER 2
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struct carl9170fw_last_desc {
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@ -189,8 +205,8 @@ struct carl9170fw_last_desc {
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}
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static inline void carl9170fw_fill_desc(struct carl9170fw_desc_head *head,
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u8 magic[4], __le16 length,
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u8 min_ver, u8 cur_ver)
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u8 magic[CARL9170FW_MAGIC_SIZE],
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__le16 length, u8 min_ver, u8 cur_ver)
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{
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head->magic[0] = magic[0];
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head->magic[1] = magic[1];
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@ -204,7 +220,7 @@ static inline void carl9170fw_fill_desc(struct carl9170fw_desc_head *head,
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#define carl9170fw_for_each_hdr(desc, fw_desc) \
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for (desc = fw_desc; \
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memcmp(desc->magic, LAST_MAGIC, 4) && \
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memcmp(desc->magic, LAST_MAGIC, CARL9170FW_MAGIC_SIZE) && \
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le16_to_cpu(desc->length) >= CARL9170FW_DESC_HEAD_SIZE && \
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le16_to_cpu(desc->length) < CARL9170FW_DESC_MAX_LENGTH; \
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desc = (void *)((unsigned long)desc + le16_to_cpu(desc->length)))
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@ -218,8 +234,8 @@ static inline bool carl9170fw_supports(__le32 list, u8 feature)
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}
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static inline bool carl9170fw_desc_cmp(const struct carl9170fw_desc_head *head,
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const u8 descid[4], u16 min_len,
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u8 compatible_revision)
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const u8 descid[CARL9170FW_MAGIC_SIZE],
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u16 min_len, u8 compatible_revision)
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{
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if (descid[0] == head->magic[0] && descid[1] == head->magic[1] &&
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descid[2] == head->magic[2] && descid[3] == head->magic[3] &&
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@ -463,6 +463,8 @@
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#define AR9170_PWR_REG_CHIP_REVISION (AR9170_PWR_REG_BASE + 0x010)
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#define AR9170_PWR_REG_PLL_ADDAC (AR9170_PWR_REG_BASE + 0x014)
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#define AR9170_PWR_PLL_ADDAC_DIV_S 2
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#define AR9170_PWR_PLL_ADDAC_DIV 0xffc
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#define AR9170_PWR_REG_WATCH_DOG_MAGIC (AR9170_PWR_REG_BASE + 0x020)
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/* Faraday USB Controller */
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@ -471,6 +473,9 @@
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#define AR9170_USB_REG_MAIN_CTRL (AR9170_USB_REG_BASE + 0x000)
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#define AR9170_USB_MAIN_CTRL_REMOTE_WAKEUP BIT(0)
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#define AR9170_USB_MAIN_CTRL_ENABLE_GLOBAL_INT BIT(2)
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#define AR9170_USB_MAIN_CTRL_GO_TO_SUSPEND BIT(3)
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#define AR9170_USB_MAIN_CTRL_RESET BIT(4)
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#define AR9170_USB_MAIN_CTRL_CHIP_ENABLE BIT(5)
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#define AR9170_USB_MAIN_CTRL_HIGHSPEED BIT(6)
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#define AR9170_USB_REG_DEVICE_ADDRESS (AR9170_USB_REG_BASE + 0x001)
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@ -499,6 +504,13 @@
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#define AR9170_USB_REG_INTR_GROUP (AR9170_USB_REG_BASE + 0x020)
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#define AR9170_USB_REG_INTR_SOURCE_0 (AR9170_USB_REG_BASE + 0x021)
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#define AR9170_USB_INTR_SRC0_SETUP BIT(0)
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#define AR9170_USB_INTR_SRC0_IN BIT(1)
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#define AR9170_USB_INTR_SRC0_OUT BIT(2)
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#define AR9170_USB_INTR_SRC0_FAIL BIT(3) /* ??? */
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#define AR9170_USB_INTR_SRC0_END BIT(4) /* ??? */
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#define AR9170_USB_INTR_SRC0_ABORT BIT(7)
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#define AR9170_USB_REG_INTR_SOURCE_1 (AR9170_USB_REG_BASE + 0x022)
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#define AR9170_USB_REG_INTR_SOURCE_2 (AR9170_USB_REG_BASE + 0x023)
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#define AR9170_USB_REG_INTR_SOURCE_3 (AR9170_USB_REG_BASE + 0x024)
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@ -506,6 +518,15 @@
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#define AR9170_USB_REG_INTR_SOURCE_5 (AR9170_USB_REG_BASE + 0x026)
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#define AR9170_USB_REG_INTR_SOURCE_6 (AR9170_USB_REG_BASE + 0x027)
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#define AR9170_USB_REG_INTR_SOURCE_7 (AR9170_USB_REG_BASE + 0x028)
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#define AR9170_USB_INTR_SRC7_USB_RESET BIT(1)
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#define AR9170_USB_INTR_SRC7_USB_SUSPEND BIT(2)
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#define AR9170_USB_INTR_SRC7_USB_RESUME BIT(3)
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#define AR9170_USB_INTR_SRC7_ISO_SEQ_ERR BIT(4)
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#define AR9170_USB_INTR_SRC7_ISO_SEQ_ABORT BIT(5)
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#define AR9170_USB_INTR_SRC7_TX0BYTE BIT(6)
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#define AR9170_USB_INTR_SRC7_RX0BYTE BIT(7)
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#define AR9170_USB_REG_IDLE_COUNT (AR9170_USB_REG_BASE + 0x02f)
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#define AR9170_USB_REG_EP_MAP (AR9170_USB_REG_BASE + 0x030)
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#define AR9170_USB_REG_EP1_MAP (AR9170_USB_REG_BASE + 0x030)
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@ -581,6 +602,10 @@
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#define AR9170_USB_REG_MAX_AGG_UPLOAD (AR9170_USB_REG_BASE + 0x110)
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#define AR9170_USB_REG_UPLOAD_TIME_CTL (AR9170_USB_REG_BASE + 0x114)
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#define AR9170_USB_REG_WAKE_UP (AR9170_USB_REG_BASE + 0x120)
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#define AR9170_USB_WAKE_UP_WAKE BIT(0)
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#define AR9170_USB_REG_CBUS_CTRL (AR9170_USB_REG_BASE + 0x1f0)
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#define AR9170_USB_CBUS_CTRL_BUFFER_END (BIT(1))
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@ -1,7 +1,7 @@
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#ifndef __CARL9170_SHARED_VERSION_H
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#define __CARL9170_SHARED_VERSION_H
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#define CARL9170FW_VERSION_YEAR 10
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#define CARL9170FW_VERSION_MONTH 10
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#define CARL9170FW_VERSION_DAY 29
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#define CARL9170FW_VERSION_GIT "1.9.0"
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#define CARL9170FW_VERSION_YEAR 11
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#define CARL9170FW_VERSION_MONTH 1
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#define CARL9170FW_VERSION_DAY 22
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#define CARL9170FW_VERSION_GIT "1.9.2"
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#endif /* __CARL9170_SHARED_VERSION_H */
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@ -251,7 +251,7 @@ struct carl9170_tx_superdesc {
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u8 ampdu_commit_factor:1;
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u8 ampdu_unused_bit:1;
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u8 queue:2;
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u8 reserved:1;
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u8 assign_seq:1;
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u8 vif_id:3;
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u8 fill_in_tsf:1;
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u8 cab:1;
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@ -299,6 +299,7 @@ struct _ar9170_tx_hwdesc {
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#define CARL9170_TX_SUPER_MISC_QUEUE 0x3
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#define CARL9170_TX_SUPER_MISC_QUEUE_S 0
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#define CARL9170_TX_SUPER_MISC_ASSIGN_SEQ 0x4
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#define CARL9170_TX_SUPER_MISC_VIF_ID 0x38
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#define CARL9170_TX_SUPER_MISC_VIF_ID_S 3
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#define CARL9170_TX_SUPER_MISC_FILL_IN_TSF 0x40
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@ -413,6 +414,23 @@ enum ar9170_txq {
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__AR9170_NUM_TXQ,
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};
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/*
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* This is an workaround for several undocumented bugs.
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* Don't mess with the QoS/AC <-> HW Queue map, if you don't
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* know what you are doing.
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*
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* Known problems [hardware]:
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* * The MAC does not aggregate frames on anything other
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* than the first HW queue.
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* * when an AMPDU is placed [in the first hw queue] and
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* additional frames are already queued on a different
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* hw queue, the MAC will ALWAYS freeze.
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*
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* In a nutshell: The hardware can either do QoS or
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* Aggregation but not both at the same time. As a
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* result, this makes the device pretty much useless
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* for any serious 802.11n setup.
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*/
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static const u8 ar9170_qmap[__AR9170_NUM_TXQ] = { 2, 1, 0, 3 };
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#define AR9170_TXQ_DEPTH 32
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