dmaengine: Add support for multiple descriptors for imx-dma.
dmaengine specifies the possibility that several descriptors can be queued for transfer. It also indicates that tasklets must be used for DMA callbacks. Acked-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Javier Martin <javier.martin@vista-silicon.com> Signed-off-by: Vinod Koul <vinod.koul@linux.intel.com>
This commit is contained in:
Javier Martin
Vinod Koul
Родитель
6c05f09155
Коммит
9e15db7ce9
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@ -5,6 +5,7 @@
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* found on i.MX1/21/27
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*
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* Copyright 2010 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
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* Copyright 2012 Javier Martin, Vista Silicon <javier.martin@vista-silicon.com>
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*
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* The code contained herein is licensed under the GNU General Public
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* License. You may obtain a copy of the GNU General Public License
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@ -13,6 +14,7 @@
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* http://www.opensource.org/licenses/gpl-license.html
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* http://www.gnu.org/copyleft/gpl.html
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*/
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/types.h>
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@ -29,19 +31,52 @@
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#include <mach/dma-v1.h>
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#include <mach/hardware.h>
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#define IMXDMA_MAX_CHAN_DESCRIPTORS 16
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enum imxdma_prep_type {
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IMXDMA_DESC_MEMCPY,
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IMXDMA_DESC_INTERLEAVED,
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IMXDMA_DESC_SLAVE_SG,
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IMXDMA_DESC_CYCLIC,
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};
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struct imxdma_desc {
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struct list_head node;
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struct dma_async_tx_descriptor desc;
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enum dma_status status;
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dma_addr_t src;
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dma_addr_t dest;
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size_t len;
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unsigned int dmamode;
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enum imxdma_prep_type type;
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/* For memcpy and interleaved */
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unsigned int config_port;
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unsigned int config_mem;
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/* For interleaved transfers */
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unsigned int x;
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unsigned int y;
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unsigned int w;
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/* For slave sg and cyclic */
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struct scatterlist *sg;
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unsigned int sgcount;
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};
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struct imxdma_channel {
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struct imxdma_engine *imxdma;
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unsigned int channel;
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unsigned int imxdma_channel;
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struct tasklet_struct dma_tasklet;
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struct list_head ld_free;
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struct list_head ld_queue;
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struct list_head ld_active;
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int descs_allocated;
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enum dma_slave_buswidth word_size;
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dma_addr_t per_address;
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u32 watermark_level;
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struct dma_chan chan;
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spinlock_t lock;
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struct dma_async_tx_descriptor desc;
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dma_cookie_t last_completed;
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enum dma_status status;
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int dma_request;
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struct scatterlist *sg_list;
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};
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@ -60,27 +95,31 @@ static struct imxdma_channel *to_imxdma_chan(struct dma_chan *chan)
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return container_of(chan, struct imxdma_channel, chan);
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}
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static void imxdma_handle(struct imxdma_channel *imxdmac)
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static inline bool imxdma_chan_is_doing_cyclic(struct imxdma_channel *imxdmac)
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{
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if (imxdmac->desc.callback)
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imxdmac->desc.callback(imxdmac->desc.callback_param);
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imxdmac->last_completed = imxdmac->desc.cookie;
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struct imxdma_desc *desc;
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if (!list_empty(&imxdmac->ld_active)) {
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desc = list_first_entry(&imxdmac->ld_active, struct imxdma_desc,
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node);
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if (desc->type == IMXDMA_DESC_CYCLIC)
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return true;
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}
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return false;
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}
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static void imxdma_irq_handler(int channel, void *data)
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{
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struct imxdma_channel *imxdmac = data;
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imxdmac->status = DMA_SUCCESS;
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imxdma_handle(imxdmac);
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tasklet_schedule(&imxdmac->dma_tasklet);
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}
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static void imxdma_err_handler(int channel, void *data, int error)
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{
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struct imxdma_channel *imxdmac = data;
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imxdmac->status = DMA_ERROR;
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imxdma_handle(imxdmac);
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tasklet_schedule(&imxdmac->dma_tasklet);
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}
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static void imxdma_progression(int channel, void *data,
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@ -88,8 +127,88 @@ static void imxdma_progression(int channel, void *data,
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{
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struct imxdma_channel *imxdmac = data;
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imxdmac->status = DMA_SUCCESS;
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imxdma_handle(imxdmac);
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tasklet_schedule(&imxdmac->dma_tasklet);
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}
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static int imxdma_xfer_desc(struct imxdma_desc *d)
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{
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struct imxdma_channel *imxdmac = to_imxdma_chan(d->desc.chan);
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int ret;
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/* Configure and enable */
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switch (d->type) {
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case IMXDMA_DESC_MEMCPY:
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ret = imx_dma_config_channel(imxdmac->imxdma_channel,
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d->config_port, d->config_mem, 0, 0);
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if (ret < 0)
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return ret;
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ret = imx_dma_setup_single(imxdmac->imxdma_channel, d->src,
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d->len, d->dest, d->dmamode);
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if (ret < 0)
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return ret;
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break;
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case IMXDMA_DESC_CYCLIC:
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ret = imx_dma_setup_progression_handler(imxdmac->imxdma_channel,
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imxdma_progression);
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if (ret < 0)
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return ret;
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/*
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* We fall through here since cyclic transfer is the same as
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* slave_sg adding a progression handler and a specific sg
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* configuration which is done in 'imxdma_prep_dma_cyclic'.
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*/
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case IMXDMA_DESC_SLAVE_SG:
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if (d->dmamode == DMA_MODE_READ)
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ret = imx_dma_setup_sg(imxdmac->imxdma_channel, d->sg,
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d->sgcount, d->len, d->src, d->dmamode);
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else
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ret = imx_dma_setup_sg(imxdmac->imxdma_channel, d->sg,
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d->sgcount, d->len, d->dest, d->dmamode);
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if (ret < 0)
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return ret;
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break;
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default:
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return -EINVAL;
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}
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imx_dma_enable(imxdmac->imxdma_channel);
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return 0;
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}
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static void imxdma_tasklet(unsigned long data)
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{
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struct imxdma_channel *imxdmac = (void *)data;
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struct imxdma_engine *imxdma = imxdmac->imxdma;
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struct imxdma_desc *desc;
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spin_lock(&imxdmac->lock);
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if (list_empty(&imxdmac->ld_active)) {
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/* Someone might have called terminate all */
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goto out;
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}
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desc = list_first_entry(&imxdmac->ld_active, struct imxdma_desc, node);
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if (desc->desc.callback)
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desc->desc.callback(desc->desc.callback_param);
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imxdmac->last_completed = desc->desc.cookie;
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/* If we are dealing with a cyclic descriptor keep it on ld_active */
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if (imxdma_chan_is_doing_cyclic(imxdmac))
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goto out;
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list_move_tail(imxdmac->ld_active.next, &imxdmac->ld_free);
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if (!list_empty(&imxdmac->ld_queue)) {
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desc = list_first_entry(&imxdmac->ld_queue, struct imxdma_desc,
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node);
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list_move_tail(imxdmac->ld_queue.next, &imxdmac->ld_active);
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if (imxdma_xfer_desc(desc) < 0)
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dev_warn(imxdma->dev, "%s: channel: %d couldn't xfer desc\n",
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__func__, imxdmac->channel);
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}
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out:
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spin_unlock(&imxdmac->lock);
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}
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static int imxdma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
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@ -98,12 +217,17 @@ static int imxdma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
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struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
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struct dma_slave_config *dmaengine_cfg = (void *)arg;
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int ret;
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unsigned long flags;
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unsigned int mode = 0;
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switch (cmd) {
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case DMA_TERMINATE_ALL:
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imxdmac->status = DMA_ERROR;
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imx_dma_disable(imxdmac->imxdma_channel);
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spin_lock_irqsave(&imxdmac->lock, flags);
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list_splice_tail_init(&imxdmac->ld_active, &imxdmac->ld_free);
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list_splice_tail_init(&imxdmac->ld_queue, &imxdmac->ld_free);
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spin_unlock_irqrestore(&imxdmac->lock, flags);
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return 0;
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case DMA_SLAVE_CONFIG:
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if (dmaengine_cfg->direction == DMA_DEV_TO_MEM) {
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@ -154,11 +278,14 @@ static enum dma_status imxdma_tx_status(struct dma_chan *chan,
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struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
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dma_cookie_t last_used;
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enum dma_status ret;
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unsigned long flags;
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spin_lock_irqsave(&imxdmac->lock, flags);
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last_used = chan->cookie;
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ret = dma_async_is_complete(cookie, imxdmac->last_completed, last_used);
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dma_set_tx_state(txstate, imxdmac->last_completed, last_used, 0);
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spin_unlock_irqrestore(&imxdmac->lock, flags);
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return ret;
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}
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@ -171,7 +298,6 @@ static dma_cookie_t imxdma_assign_cookie(struct imxdma_channel *imxdma)
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cookie = 1;
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imxdma->chan.cookie = cookie;
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imxdma->desc.cookie = cookie;
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return cookie;
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}
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@ -180,12 +306,15 @@ static dma_cookie_t imxdma_tx_submit(struct dma_async_tx_descriptor *tx)
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{
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struct imxdma_channel *imxdmac = to_imxdma_chan(tx->chan);
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dma_cookie_t cookie;
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unsigned long flags;
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spin_lock_irq(&imxdmac->lock);
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spin_lock_irqsave(&imxdmac->lock, flags);
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list_move_tail(imxdmac->ld_free.next, &imxdmac->ld_queue);
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cookie = imxdma_assign_cookie(imxdmac);
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tx->cookie = cookie;
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spin_unlock_irq(&imxdmac->lock);
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spin_unlock_irqrestore(&imxdmac->lock, flags);
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return cookie;
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}
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@ -198,21 +327,48 @@ static int imxdma_alloc_chan_resources(struct dma_chan *chan)
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if (data != NULL)
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imxdmac->dma_request = data->dma_request;
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dma_async_tx_descriptor_init(&imxdmac->desc, chan);
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imxdmac->desc.tx_submit = imxdma_tx_submit;
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/* txd.flags will be overwritten in prep funcs */
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imxdmac->desc.flags = DMA_CTRL_ACK;
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while (imxdmac->descs_allocated < IMXDMA_MAX_CHAN_DESCRIPTORS) {
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struct imxdma_desc *desc;
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imxdmac->status = DMA_SUCCESS;
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desc = kzalloc(sizeof(*desc), GFP_KERNEL);
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if (!desc)
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break;
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__memzero(&desc->desc, sizeof(struct dma_async_tx_descriptor));
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dma_async_tx_descriptor_init(&desc->desc, chan);
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desc->desc.tx_submit = imxdma_tx_submit;
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/* txd.flags will be overwritten in prep funcs */
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desc->desc.flags = DMA_CTRL_ACK;
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desc->status = DMA_SUCCESS;
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return 0;
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list_add_tail(&desc->node, &imxdmac->ld_free);
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imxdmac->descs_allocated++;
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}
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if (!imxdmac->descs_allocated)
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return -ENOMEM;
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return imxdmac->descs_allocated;
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}
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static void imxdma_free_chan_resources(struct dma_chan *chan)
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{
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struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
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struct imxdma_desc *desc, *_desc;
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unsigned long flags;
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spin_lock_irqsave(&imxdmac->lock, flags);
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imx_dma_disable(imxdmac->imxdma_channel);
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list_splice_tail_init(&imxdmac->ld_active, &imxdmac->ld_free);
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list_splice_tail_init(&imxdmac->ld_queue, &imxdmac->ld_free);
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spin_unlock_irqrestore(&imxdmac->lock, flags);
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list_for_each_entry_safe(desc, _desc, &imxdmac->ld_free, node) {
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kfree(desc);
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imxdmac->descs_allocated--;
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}
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INIT_LIST_HEAD(&imxdmac->ld_free);
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if (imxdmac->sg_list) {
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kfree(imxdmac->sg_list);
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@ -227,23 +383,19 @@ static struct dma_async_tx_descriptor *imxdma_prep_slave_sg(
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{
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struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
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struct scatterlist *sg;
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int i, ret, dma_length = 0;
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unsigned int dmamode;
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int i, dma_length = 0;
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struct imxdma_desc *desc;
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if (imxdmac->status == DMA_IN_PROGRESS)
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if (list_empty(&imxdmac->ld_free) ||
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imxdma_chan_is_doing_cyclic(imxdmac))
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return NULL;
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imxdmac->status = DMA_IN_PROGRESS;
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desc = list_first_entry(&imxdmac->ld_free, struct imxdma_desc, node);
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for_each_sg(sgl, sg, sg_len, i) {
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dma_length += sg->length;
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}
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if (direction == DMA_DEV_TO_MEM)
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dmamode = DMA_MODE_READ;
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else
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dmamode = DMA_MODE_WRITE;
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switch (imxdmac->word_size) {
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case DMA_SLAVE_BUSWIDTH_4_BYTES:
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if (sgl->length & 3 || sgl->dma_address & 3)
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@ -259,12 +411,21 @@ static struct dma_async_tx_descriptor *imxdma_prep_slave_sg(
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return NULL;
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}
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ret = imx_dma_setup_sg(imxdmac->imxdma_channel, sgl, sg_len,
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dma_length, imxdmac->per_address, dmamode);
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if (ret)
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return NULL;
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desc->type = IMXDMA_DESC_SLAVE_SG;
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desc->sg = sgl;
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desc->sgcount = sg_len;
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desc->len = dma_length;
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if (direction == DMA_DEV_TO_MEM) {
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desc->dmamode = DMA_MODE_READ;
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desc->src = imxdmac->per_address;
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} else {
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desc->dmamode = DMA_MODE_WRITE;
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desc->dest = imxdmac->per_address;
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}
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desc->desc.callback = NULL;
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desc->desc.callback_param = NULL;
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return &imxdmac->desc;
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return &desc->desc;
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}
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static struct dma_async_tx_descriptor *imxdma_prep_dma_cyclic(
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@ -273,23 +434,18 @@ static struct dma_async_tx_descriptor *imxdma_prep_dma_cyclic(
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{
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struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
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struct imxdma_engine *imxdma = imxdmac->imxdma;
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int i, ret;
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struct imxdma_desc *desc;
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int i;
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unsigned int periods = buf_len / period_len;
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unsigned int dmamode;
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dev_dbg(imxdma->dev, "%s channel: %d buf_len=%d period_len=%d\n",
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__func__, imxdmac->channel, buf_len, period_len);
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if (imxdmac->status == DMA_IN_PROGRESS)
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if (list_empty(&imxdmac->ld_free) ||
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imxdma_chan_is_doing_cyclic(imxdmac))
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return NULL;
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imxdmac->status = DMA_IN_PROGRESS;
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ret = imx_dma_setup_progression_handler(imxdmac->imxdma_channel,
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imxdma_progression);
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if (ret) {
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dev_err(imxdma->dev, "Failed to setup the DMA handler\n");
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return NULL;
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}
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desc = list_first_entry(&imxdmac->ld_free, struct imxdma_desc, node);
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if (imxdmac->sg_list)
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kfree(imxdmac->sg_list);
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|
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@ -315,17 +471,21 @@ static struct dma_async_tx_descriptor *imxdma_prep_dma_cyclic(
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imxdmac->sg_list[periods].page_link =
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((unsigned long)imxdmac->sg_list | 0x01) & ~0x02;
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if (direction == DMA_DEV_TO_MEM)
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dmamode = DMA_MODE_READ;
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else
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dmamode = DMA_MODE_WRITE;
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desc->type = IMXDMA_DESC_CYCLIC;
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desc->sg = imxdmac->sg_list;
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desc->sgcount = periods;
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desc->len = IMX_DMA_LENGTH_LOOP;
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if (direction == DMA_DEV_TO_MEM) {
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desc->dmamode = DMA_MODE_READ;
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desc->src = imxdmac->per_address;
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} else {
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desc->dmamode = DMA_MODE_WRITE;
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desc->dest = imxdmac->per_address;
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}
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desc->desc.callback = NULL;
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desc->desc.callback_param = NULL;
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|
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ret = imx_dma_setup_sg(imxdmac->imxdma_channel, imxdmac->sg_list, periods,
|
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IMX_DMA_LENGTH_LOOP, imxdmac->per_address, dmamode);
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if (ret)
|
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return NULL;
|
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|
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return &imxdmac->desc;
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return &desc->desc;
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}
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|
||||
static struct dma_async_tx_descriptor *imxdma_prep_dma_memcpy(
|
||||
|
|
@ -334,36 +494,53 @@ static struct dma_async_tx_descriptor *imxdma_prep_dma_memcpy(
|
|||
{
|
||||
struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
|
||||
struct imxdma_engine *imxdma = imxdmac->imxdma;
|
||||
int ret;
|
||||
struct imxdma_desc *desc;
|
||||
|
||||
dev_dbg(imxdma->dev, "%s channel: %d src=0x%x dst=0x%x len=%d\n",
|
||||
__func__, imxdmac->channel, src, dest, len);
|
||||
|
||||
if (imxdmac->status == DMA_IN_PROGRESS)
|
||||
return NULL;
|
||||
imxdmac->status = DMA_IN_PROGRESS;
|
||||
|
||||
ret = imx_dma_config_channel(imxdmac->imxdma_channel,
|
||||
IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR,
|
||||
IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR,
|
||||
0, 0);
|
||||
if (ret)
|
||||
if (list_empty(&imxdmac->ld_free) ||
|
||||
imxdma_chan_is_doing_cyclic(imxdmac))
|
||||
return NULL;
|
||||
|
||||
ret = imx_dma_setup_single(imxdmac->imxdma_channel, src, len,
|
||||
dest, DMA_MODE_WRITE);
|
||||
if (ret)
|
||||
return NULL;
|
||||
desc = list_first_entry(&imxdmac->ld_free, struct imxdma_desc, node);
|
||||
|
||||
return &imxdmac->desc;
|
||||
desc->type = IMXDMA_DESC_MEMCPY;
|
||||
desc->src = src;
|
||||
desc->dest = dest;
|
||||
desc->len = len;
|
||||
desc->dmamode = DMA_MODE_WRITE;
|
||||
desc->config_port = IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR;
|
||||
desc->config_mem = IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR;
|
||||
desc->desc.callback = NULL;
|
||||
desc->desc.callback_param = NULL;
|
||||
|
||||
return &desc->desc;
|
||||
}
|
||||
|
||||
static void imxdma_issue_pending(struct dma_chan *chan)
|
||||
{
|
||||
struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
|
||||
struct imxdma_engine *imxdma = imxdmac->imxdma;
|
||||
struct imxdma_desc *desc;
|
||||
unsigned long flags;
|
||||
|
||||
if (imxdmac->status == DMA_IN_PROGRESS)
|
||||
imx_dma_enable(imxdmac->imxdma_channel);
|
||||
spin_lock_irqsave(&imxdmac->lock, flags);
|
||||
if (list_empty(&imxdmac->ld_active) &&
|
||||
!list_empty(&imxdmac->ld_queue)) {
|
||||
desc = list_first_entry(&imxdmac->ld_queue,
|
||||
struct imxdma_desc, node);
|
||||
|
||||
if (imxdma_xfer_desc(desc) < 0) {
|
||||
dev_warn(imxdma->dev,
|
||||
"%s: channel: %d couldn't issue DMA xfer\n",
|
||||
__func__, imxdmac->channel);
|
||||
} else {
|
||||
list_move_tail(imxdmac->ld_queue.next,
|
||||
&imxdmac->ld_active);
|
||||
}
|
||||
}
|
||||
spin_unlock_irqrestore(&imxdmac->lock, flags);
|
||||
}
|
||||
|
||||
static int __init imxdma_probe(struct platform_device *pdev)
|
||||
|
|
@ -398,11 +575,18 @@ static int __init imxdma_probe(struct platform_device *pdev)
|
|||
imxdmac->imxdma = imxdma;
|
||||
spin_lock_init(&imxdmac->lock);
|
||||
|
||||
INIT_LIST_HEAD(&imxdmac->ld_queue);
|
||||
INIT_LIST_HEAD(&imxdmac->ld_free);
|
||||
INIT_LIST_HEAD(&imxdmac->ld_active);
|
||||
|
||||
tasklet_init(&imxdmac->dma_tasklet, imxdma_tasklet,
|
||||
(unsigned long)imxdmac);
|
||||
imxdmac->chan.device = &imxdma->dma_device;
|
||||
imxdmac->channel = i;
|
||||
|
||||
/* Add the channel to the DMAC list */
|
||||
list_add_tail(&imxdmac->chan.device_node, &imxdma->dma_device.channels);
|
||||
list_add_tail(&imxdmac->chan.device_node,
|
||||
&imxdma->dma_device.channels);
|
||||
}
|
||||
|
||||
imxdma->dev = &pdev->dev;
|
||||
|
|
|
|||
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