ibm_newemac: Add support for GPCS, SGMII and M88E1112 PHY
Add support for the phy types found on the Arches and other PowerPC 460 based boards. Signed-off-by: Victor Gallardo <vgallardo@amcc.com> Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Acked-by: Jeff Garzik <jeff@garzik.org> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
This commit is contained in:
Victor Gallardo
Josh Boyer
Родитель
5a013fc7bb
Коммит
9e3cb29497
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@ -75,6 +75,10 @@
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#define ICINTSTAT_ICTX1 0x20000000
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#define ICINTSTAT_ICTX 0x60000000
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/* SDRs (460EX/460GT) */
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#define SDR0_ETH_CFG 0x4103
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#define SDR0_ETH_CFG_ECS 0x00000100 /* EMAC int clk source */
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/*
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* All those DCR register addresses are offsets from the base address
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* for the SRAM0 controller (e.g. 0x20 on 440GX). The base address is
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@ -130,6 +130,7 @@ static inline void emac_report_timeout_error(struct emac_instance *dev,
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const char *error)
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{
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if (emac_has_feature(dev, EMAC_FTR_440GX_PHY_CLK_FIX |
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EMAC_FTR_460EX_PHY_CLK_FIX |
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EMAC_FTR_440EP_PHY_CLK_FIX))
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DBG(dev, "%s" NL, error);
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else if (net_ratelimit())
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@ -201,13 +202,15 @@ static inline int emac_phy_supports_gige(int phy_mode)
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{
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return phy_mode == PHY_MODE_GMII ||
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phy_mode == PHY_MODE_RGMII ||
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phy_mode == PHY_MODE_SGMII ||
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phy_mode == PHY_MODE_TBI ||
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phy_mode == PHY_MODE_RTBI;
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}
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static inline int emac_phy_gpcs(int phy_mode)
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{
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return phy_mode == PHY_MODE_TBI ||
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return phy_mode == PHY_MODE_SGMII ||
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phy_mode == PHY_MODE_TBI ||
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phy_mode == PHY_MODE_RTBI;
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}
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@ -351,10 +354,24 @@ static int emac_reset(struct emac_instance *dev)
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emac_tx_disable(dev);
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}
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#ifdef CONFIG_PPC_DCR_NATIVE
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/* Enable internal clock source */
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if (emac_has_feature(dev, EMAC_FTR_460EX_PHY_CLK_FIX))
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dcri_clrset(SDR0, SDR0_ETH_CFG,
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0, SDR0_ETH_CFG_ECS << dev->cell_index);
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#endif
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out_be32(&p->mr0, EMAC_MR0_SRST);
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while ((in_be32(&p->mr0) & EMAC_MR0_SRST) && n)
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--n;
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#ifdef CONFIG_PPC_DCR_NATIVE
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/* Enable external clock source */
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if (emac_has_feature(dev, EMAC_FTR_460EX_PHY_CLK_FIX))
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dcri_clrset(SDR0, SDR0_ETH_CFG,
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SDR0_ETH_CFG_ECS << dev->cell_index, 0);
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#endif
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if (n) {
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dev->reset_failed = 0;
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return 0;
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@ -547,8 +564,9 @@ static int emac_configure(struct emac_instance *dev)
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switch (dev->phy.speed) {
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case SPEED_1000:
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if (emac_phy_gpcs(dev->phy.mode)) {
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mr1 |= EMAC_MR1_MF_1000GPCS |
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EMAC_MR1_MF_IPPA(dev->phy.address);
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mr1 |= EMAC_MR1_MF_1000GPCS | EMAC_MR1_MF_IPPA(
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(dev->phy.gpcs_address != 0xffffffff) ?
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dev->phy.gpcs_address : dev->phy.address);
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/* Put some arbitrary OUI, Manuf & Rev IDs so we can
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* identify this GPCS PHY later.
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@ -660,8 +678,12 @@ static int emac_configure(struct emac_instance *dev)
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out_be32(&p->iser, r);
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/* We need to take GPCS PHY out of isolate mode after EMAC reset */
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if (emac_phy_gpcs(dev->phy.mode))
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emac_mii_reset_phy(&dev->phy);
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if (emac_phy_gpcs(dev->phy.mode)) {
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if (dev->phy.gpcs_address != 0xffffffff)
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emac_mii_reset_gpcs(&dev->phy);
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else
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emac_mii_reset_phy(&dev->phy);
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}
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return 0;
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}
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@ -866,7 +888,9 @@ static int emac_mdio_read(struct net_device *ndev, int id, int reg)
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struct emac_instance *dev = netdev_priv(ndev);
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int res;
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res = __emac_mdio_read(dev->mdio_instance ? dev->mdio_instance : dev,
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res = __emac_mdio_read((dev->mdio_instance &&
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dev->phy.gpcs_address != id) ?
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dev->mdio_instance : dev,
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(u8) id, (u8) reg);
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return res;
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}
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@ -875,7 +899,9 @@ static void emac_mdio_write(struct net_device *ndev, int id, int reg, int val)
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{
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struct emac_instance *dev = netdev_priv(ndev);
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__emac_mdio_write(dev->mdio_instance ? dev->mdio_instance : dev,
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__emac_mdio_write((dev->mdio_instance &&
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dev->phy.gpcs_address != id) ?
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dev->mdio_instance : dev,
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(u8) id, (u8) reg, (u16) val);
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}
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@ -2367,7 +2393,11 @@ static int __devinit emac_init_phy(struct emac_instance *dev)
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* XXX I probably should move these settings to the dev tree
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*/
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dev->phy.address = -1;
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dev->phy.features = SUPPORTED_100baseT_Full | SUPPORTED_MII;
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dev->phy.features = SUPPORTED_MII;
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if (emac_phy_supports_gige(dev->phy_mode))
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dev->phy.features |= SUPPORTED_1000baseT_Full;
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else
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dev->phy.features |= SUPPORTED_100baseT_Full;
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dev->phy.pause = 1;
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return 0;
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@ -2406,7 +2436,9 @@ static int __devinit emac_init_phy(struct emac_instance *dev)
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* Note that the busy_phy_map is currently global
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* while it should probably be per-ASIC...
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*/
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dev->phy.address = dev->cell_index;
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dev->phy.gpcs_address = dev->gpcs_address;
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if (dev->phy.gpcs_address == 0xffffffff)
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dev->phy.address = dev->cell_index;
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}
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emac_configure(dev);
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@ -2516,6 +2548,8 @@ static int __devinit emac_init_config(struct emac_instance *dev)
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dev->phy_address = 0xffffffff;
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if (emac_read_uint_prop(np, "phy-map", &dev->phy_map, 0))
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dev->phy_map = 0xffffffff;
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if (emac_read_uint_prop(np, "gpcs-address", &dev->gpcs_address, 0))
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dev->gpcs_address = 0xffffffff;
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if (emac_read_uint_prop(np->parent, "clock-frequency", &dev->opb_bus_freq, 1))
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return -ENXIO;
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if (emac_read_uint_prop(np, "tah-device", &dev->tah_ph, 0))
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@ -2559,6 +2593,9 @@ static int __devinit emac_init_config(struct emac_instance *dev)
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/* Check EMAC version */
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if (of_device_is_compatible(np, "ibm,emac4sync")) {
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dev->features |= (EMAC_FTR_EMAC4 | EMAC_FTR_EMAC4SYNC);
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if (of_device_is_compatible(np, "ibm,emac-460ex") ||
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of_device_is_compatible(np, "ibm,emac-460gt"))
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dev->features |= EMAC_FTR_460EX_PHY_CLK_FIX;
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} else if (of_device_is_compatible(np, "ibm,emac4")) {
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dev->features |= EMAC_FTR_EMAC4;
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if (of_device_is_compatible(np, "ibm,emac-440gx"))
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@ -2826,6 +2863,9 @@ static int __devinit emac_probe(struct of_device *ofdev,
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ndev->dev_addr[0], ndev->dev_addr[1], ndev->dev_addr[2],
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ndev->dev_addr[3], ndev->dev_addr[4], ndev->dev_addr[5]);
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if (dev->phy_mode == PHY_MODE_SGMII)
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printk(KERN_NOTICE "%s: in SGMII mode\n", ndev->name);
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if (dev->phy.address >= 0)
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printk("%s: found %s PHY (0x%02x)\n", ndev->name,
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dev->phy.def->name, dev->phy.address);
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@ -190,6 +190,9 @@ struct emac_instance {
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struct delayed_work link_work;
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int link_polling;
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/* GPCS PHY infos */
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u32 gpcs_address;
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/* Shared MDIO if any */
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u32 mdio_ph;
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struct of_device *mdio_dev;
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@ -317,6 +320,10 @@ struct emac_instance {
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* The 405EX and 460EX contain the EMAC4SYNC core
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*/
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#define EMAC_FTR_EMAC4SYNC 0x00000200
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/*
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* Set if we need phy clock workaround for 460ex or 460gt
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*/
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#define EMAC_FTR_460EX_PHY_CLK_FIX 0x00000400
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/* Right now, we don't quite handle the always/possible masks on the
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@ -344,6 +351,7 @@ enum {
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#ifdef CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL
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EMAC_FTR_NO_FLOW_CONTROL_40x |
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#endif
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EMAC_FTR_460EX_PHY_CLK_FIX |
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EMAC_FTR_440EP_PHY_CLK_FIX,
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};
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@ -38,6 +38,16 @@ static inline void phy_write(struct mii_phy *phy, int reg, int val)
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phy->mdio_write(phy->dev, phy->address, reg, val);
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}
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static inline int gpcs_phy_read(struct mii_phy *phy, int reg)
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{
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return phy->mdio_read(phy->dev, phy->gpcs_address, reg);
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}
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static inline void gpcs_phy_write(struct mii_phy *phy, int reg, int val)
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{
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phy->mdio_write(phy->dev, phy->gpcs_address, reg, val);
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}
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int emac_mii_reset_phy(struct mii_phy *phy)
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{
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int val;
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@ -62,6 +72,37 @@ int emac_mii_reset_phy(struct mii_phy *phy)
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return limit <= 0;
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}
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int emac_mii_reset_gpcs(struct mii_phy *phy)
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{
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int val;
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int limit = 10000;
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val = gpcs_phy_read(phy, MII_BMCR);
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val &= ~(BMCR_ISOLATE | BMCR_ANENABLE);
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val |= BMCR_RESET;
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gpcs_phy_write(phy, MII_BMCR, val);
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udelay(300);
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while (limit--) {
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val = gpcs_phy_read(phy, MII_BMCR);
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if (val >= 0 && (val & BMCR_RESET) == 0)
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break;
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udelay(10);
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}
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if ((val & BMCR_ISOLATE) && limit > 0)
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gpcs_phy_write(phy, MII_BMCR, val & ~BMCR_ISOLATE);
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if (limit > 0 && phy->mode == PHY_MODE_SGMII) {
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/* Configure GPCS interface to recommended setting for SGMII */
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gpcs_phy_write(phy, 0x04, 0x8120); /* AsymPause, FDX */
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gpcs_phy_write(phy, 0x07, 0x2801); /* msg_pg, toggle */
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gpcs_phy_write(phy, 0x00, 0x0140); /* 1Gbps, FDX */
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}
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return limit <= 0;
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}
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static int genmii_setup_aneg(struct mii_phy *phy, u32 advertise)
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{
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int ctl, adv;
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@ -332,6 +373,33 @@ static int m88e1111_init(struct mii_phy *phy)
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return 0;
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}
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static int m88e1112_init(struct mii_phy *phy)
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{
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/*
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* Marvell 88E1112 PHY needs to have the SGMII MAC
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* interace (page 2) properly configured to
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* communicate with the 460EX/GT GPCS interface.
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*/
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u16 reg_short;
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pr_debug("%s: Marvell 88E1112 Ethernet\n", __func__);
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/* Set access to Page 2 */
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phy_write(phy, 0x16, 0x0002);
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phy_write(phy, 0x00, 0x0040); /* 1Gbps */
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reg_short = (u16)(phy_read(phy, 0x1a));
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reg_short |= 0x8000; /* bypass Auto-Negotiation */
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phy_write(phy, 0x1a, reg_short);
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emac_mii_reset_phy(phy); /* reset MAC interface */
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/* Reset access to Page 0 */
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phy_write(phy, 0x16, 0x0000);
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return 0;
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}
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static int et1011c_init(struct mii_phy *phy)
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{
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u16 reg_short;
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@ -384,11 +452,27 @@ static struct mii_phy_def m88e1111_phy_def = {
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.ops = &m88e1111_phy_ops,
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};
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static struct mii_phy_ops m88e1112_phy_ops = {
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.init = m88e1112_init,
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.setup_aneg = genmii_setup_aneg,
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.setup_forced = genmii_setup_forced,
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.poll_link = genmii_poll_link,
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.read_link = genmii_read_link
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};
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static struct mii_phy_def m88e1112_phy_def = {
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.phy_id = 0x01410C90,
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.phy_id_mask = 0x0ffffff0,
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.name = "Marvell 88E1112 Ethernet",
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.ops = &m88e1112_phy_ops,
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};
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static struct mii_phy_def *mii_phy_table[] = {
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&et1011c_phy_def,
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&cis8201_phy_def,
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&bcm5248_phy_def,
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&m88e1111_phy_def,
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&m88e1112_phy_def,
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&genmii_phy_def,
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NULL
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};
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@ -57,6 +57,7 @@ struct mii_phy {
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or determined automaticaly */
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int address; /* PHY address */
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int mode; /* PHY mode */
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int gpcs_address; /* GPCS PHY address */
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/* 1: autoneg enabled, 0: disabled */
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int autoneg;
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@ -81,5 +82,6 @@ struct mii_phy {
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*/
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int emac_mii_phy_probe(struct mii_phy *phy, int address);
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int emac_mii_reset_phy(struct mii_phy *phy);
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int emac_mii_reset_gpcs(struct mii_phy *phy);
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#endif /* __IBM_NEWEMAC_PHY_H */
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