ARC updates for 5.8-rc5
- User build systems to pass -mcpu - Fix potential EFA clobber in syscall handler - Fix ARCompact 2 levels of interrupts build - Detect newer HS CPU releases - miscll other fixes -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEOXpuCuR6hedrdLCJadfx3eKKwl4FAl8EEywACgkQadfx3eKK wl4bBxAApoG3kYeJcKkLR3zlSoP+ScbFjMd6UOZBt0lwwA8RJsU9Hyj8aq1u46yl Yknqhbe9el79fUtRbS584L947rA0d8aWYAGpFgelAxMKqb4XbfNMHl/W5lAgY84T EDeCotis9FBf21PRULbGkXEKxJAJqwYp5vCDnoTI+ckfKvhjVRsriqylsb62qGLa 4KOSWChSgSFkFv0pGCfLA7X7CgkwVDNYWbG02OBR3uRg/hBnVpAm7WgJtSFGbRCk TGTHE7Czf4m2DXM5t1N0kLWA7PQ4oJ/RNa3o8auuGbM5TdZaaewe5uRAIpuG2638 lCqU8boSEUR2yO4jHtSZaXLszhU/k6BC4gdCYUGcp9+8wCHsBubJaLUg4YGIZGZM yitzlmME8r5jS1itxO39F7k2cyE7jYvXjuvb7n/gCiYPL496pu8ZxD7nEHSmQKtx k3hl12SjX53jmQ9G2ECLVns4+yFj+thivr2CGiKq2MN6ogUbuTCFx6hZyRCuW5tq B3mV7Zzg+A3l9OBwlHMGC9ZggBnwOKdYQNKLXQl4r/XCtH01t4Y+Rcn1g4VS9BJy oHiNRs9mLO57owijwABL55eMCRoArDm5a6QUT8qByNTG0s2kNv/9TK6lKH/qnQWj 4DBSaeikKIHoxW44K9EfwhCvds0x2H/1tj2V2ImUFqOpPCygLCk= =OIAG -----END PGP SIGNATURE----- Merge tag 'arc-5.8-rc5' of git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc Pull ARC fixes from Vineet Gupta: - User build systems to pass -mcpu - Fix potential EFA clobber in syscall handler - Fix ARCompact 2 levels of interrupts build - Detect newer HS CPU releases - misc other fixes * tag 'arc-5.8-rc5' of git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc: ARCv2: support loop buffer (LPB) disabling ARC: build: remove deprecated toggle for arc700 builds ARC: build: allow users to specify -mcpu ARCv2: boot log: detect newer/upconing HS3x/HS4x releases ARC: elf: use right ELF_ARCH ARC: [arcompact] fix bitrot with 2 levels of interrupt ARC: entry: fix potential EFA clobber when TIF_SYSCALL_TRACE
This commit is contained in:
Linus Torvalds
Коммит
9e4d769621
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@ -170,6 +170,15 @@ config ARC_CPU_HS
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endchoice
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config ARC_TUNE_MCPU
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string "Override default -mcpu compiler flag"
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default ""
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help
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Override default -mcpu=xxx compiler flag (which is set depending on
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the ISA version) with the specified value.
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NOTE: If specified flag isn't supported by current compiler the
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ISA default value will be used as a fallback.
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config CPU_BIG_ENDIAN
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bool "Enable Big Endian Mode"
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help
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@ -465,6 +474,12 @@ config ARC_IRQ_NO_AUTOSAVE
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This is programmable and can be optionally disabled in which case
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software INTERRUPT_PROLOGUE/EPILGUE do the needed work
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config ARC_LPB_DISABLE
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bool "Disable loop buffer (LPB)"
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help
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On HS cores, loop buffer (LPB) is programmable in runtime and can
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be optionally disabled.
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endif # ISA_ARCV2
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endmenu # "ARC CPU Configuration"
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@ -10,8 +10,25 @@ CROSS_COMPILE := $(call cc-cross-prefix, arc-linux- arceb-linux-)
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endif
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cflags-y += -fno-common -pipe -fno-builtin -mmedium-calls -D__linux__
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cflags-$(CONFIG_ISA_ARCOMPACT) += -mA7
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cflags-$(CONFIG_ISA_ARCV2) += -mcpu=hs38
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tune-mcpu-def-$(CONFIG_ISA_ARCOMPACT) := -mcpu=arc700
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tune-mcpu-def-$(CONFIG_ISA_ARCV2) := -mcpu=hs38
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ifeq ($(CONFIG_ARC_TUNE_MCPU),"")
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cflags-y += $(tune-mcpu-def-y)
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else
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tune-mcpu := $(shell echo $(CONFIG_ARC_TUNE_MCPU))
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tune-mcpu-ok := $(call cc-option-yn, $(tune-mcpu))
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ifeq ($(tune-mcpu-ok),y)
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cflags-y += $(tune-mcpu)
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else
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# The flag provided by 'CONFIG_ARC_TUNE_MCPU' option isn't known by this compiler
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# (probably the compiler is too old). Use ISA default mcpu flag instead as a safe option.
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$(warning ** WARNING ** CONFIG_ARC_TUNE_MCPU flag '$(tune-mcpu)' is unknown, fallback to '$(tune-mcpu-def-y)')
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cflags-y += $(tune-mcpu-def-y)
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endif
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endif
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ifdef CONFIG_ARC_CURR_IN_REG
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# For a global register defintion, make sure it gets passed to every file
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@ -19,7 +19,7 @@
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#define R_ARC_32_PCREL 0x31
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/*to set parameters in the core dumps */
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#define ELF_ARCH EM_ARCOMPACT
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#define ELF_ARCH EM_ARC_INUSE
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#define ELF_CLASS ELFCLASS32
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#ifdef CONFIG_CPU_BIG_ENDIAN
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@ -90,6 +90,9 @@ static inline void arch_local_irq_restore(unsigned long flags)
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/*
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* Unconditionally Enable IRQs
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*/
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#ifdef CONFIG_ARC_COMPACT_IRQ_LEVELS
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extern void arch_local_irq_enable(void);
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#else
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static inline void arch_local_irq_enable(void)
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{
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unsigned long temp;
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@ -102,7 +105,7 @@ static inline void arch_local_irq_enable(void)
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: "n"((STATUS_E1_MASK | STATUS_E2_MASK))
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: "cc", "memory");
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}
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#endif
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/*
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* Unconditionally Disable IRQs
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@ -165,7 +165,6 @@ END(EV_Extension)
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tracesys:
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; save EFA in case tracer wants the PC of traced task
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; using ERET won't work since next-PC has already committed
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lr r12, [efa]
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GET_CURR_TASK_FIELD_PTR TASK_THREAD, r11
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st r12, [r11, THREAD_FAULT_ADDR] ; thread.fault_address
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@ -208,15 +207,9 @@ tracesys_exit:
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; Breakpoint TRAP
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; ---------------------------------------------
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trap_with_param:
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; stop_pc info by gdb needs this info
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lr r0, [efa]
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mov r0, r12 ; EFA in case ptracer/gdb wants stop_pc
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mov r1, sp
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; Now that we have read EFA, it is safe to do "fake" rtie
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; and get out of CPU exception mode
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FAKE_RET_FROM_EXCPN
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; Save callee regs in case gdb wants to have a look
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; SP will grow up by size of CALLEE Reg-File
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; NOTE: clobbers r12
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@ -243,6 +236,10 @@ ENTRY(EV_Trap)
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EXCEPTION_PROLOGUE
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lr r12, [efa]
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FAKE_RET_FROM_EXCPN
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;============ TRAP 1 :breakpoints
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; Check ECR for trap with arg (PROLOGUE ensures r10 has ECR)
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bmsk.f 0, r10, 7
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@ -250,9 +247,6 @@ ENTRY(EV_Trap)
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;============ TRAP (no param): syscall top level
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; First return from Exception to pure K mode (Exception/IRQs renabled)
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FAKE_RET_FROM_EXCPN
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; If syscall tracing ongoing, invoke pre-post-hooks
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GET_CURR_THR_INFO_FLAGS r10
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btst r10, TIF_SYSCALL_TRACE
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@ -59,6 +59,14 @@
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bclr r5, r5, STATUS_AD_BIT
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#endif
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kflag r5
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#ifdef CONFIG_ARC_LPB_DISABLE
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lr r5, [ARC_REG_LPB_BUILD]
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breq r5, 0, 1f ; LPB doesn't exist
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mov r5, 1
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sr r5, [ARC_REG_LPB_CTRL]
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1:
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#endif /* CONFIG_ARC_LPB_DISABLE */
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#endif
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; Config DSP_CTRL properly, so kernel may use integer multiply,
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; multiply-accumulate, and divide operations
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@ -58,10 +58,12 @@ static const struct id_to_str arc_legacy_rel[] = {
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{ 0x00, NULL }
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};
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static const struct id_to_str arc_cpu_rel[] = {
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static const struct id_to_str arc_hs_ver54_rel[] = {
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/* UARCH.MAJOR, Release */
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{ 0, "R3.10a"},
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{ 1, "R3.50a"},
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{ 2, "R3.60a"},
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{ 3, "R4.00a"},
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{ 0xFF, NULL }
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};
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@ -117,12 +119,6 @@ static void decode_arc_core(struct cpuinfo_arc *cpu)
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struct bcr_uarch_build_arcv2 uarch;
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const struct id_to_str *tbl;
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/*
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* Up until (including) the first core4 release (0x54) things were
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* simple: AUX IDENTITY.ARCVER was sufficient to identify arc family
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* and release: 0x50 to 0x53 was HS38, 0x54 was HS48 (dual issue)
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*/
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if (cpu->core.family < 0x54) { /* includes arc700 */
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for (tbl = &arc_legacy_rel[0]; tbl->id != 0; tbl++) {
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@ -143,11 +139,10 @@ static void decode_arc_core(struct cpuinfo_arc *cpu)
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}
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/*
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* However the subsequent HS release (same 0x54) allow HS38 or HS48
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* configurations and encode this info in a different BCR.
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* The BCR was introduced in 0x54 so can't be read unconditionally.
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* Initial HS cores bumped AUX IDENTITY.ARCVER for each release until
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* ARCVER 0x54 which introduced AUX MICRO_ARCH_BUILD and subsequent
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* releases only update it.
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*/
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READ_BCR(ARC_REG_MICRO_ARCH_BCR, uarch);
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if (uarch.prod == 4) {
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@ -158,7 +153,7 @@ static void decode_arc_core(struct cpuinfo_arc *cpu)
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cpu->name = "HS38";
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}
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for (tbl = &arc_cpu_rel[0]; tbl->id != 0xFF; tbl++) {
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for (tbl = &arc_hs_ver54_rel[0]; tbl->id != 0xFF; tbl++) {
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if (uarch.maj == tbl->id) {
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cpu->release = tbl->str;
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break;
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