arm64: dts: freescale: Add i.MX8MP EVK board support
Add basic i.MM8MP EVK board support. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
This commit is contained in:
Anson Huang
Shawn Guo
Родитель
6d9b8d2043
Коммит
9e847693c6
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@ -30,6 +30,7 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-rdb.dtb
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dtb-$(CONFIG_ARCH_MXC) += imx8mm-evk.dtb
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dtb-$(CONFIG_ARCH_MXC) += imx8mn-evk.dtb
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dtb-$(CONFIG_ARCH_MXC) += imx8mn-ddr4-evk.dtb
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dtb-$(CONFIG_ARCH_MXC) += imx8mp-evk.dtb
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dtb-$(CONFIG_ARCH_MXC) += imx8mq-evk.dtb
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dtb-$(CONFIG_ARCH_MXC) += imx8mq-hummingboard-pulse.dtb
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dtb-$(CONFIG_ARCH_MXC) += imx8mq-librem5-devkit.dtb
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@ -0,0 +1,231 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright 2019 NXP
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*/
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/dts-v1/;
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#include "imx8mp.dtsi"
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/ {
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model = "NXP i.MX8MPlus EVK board";
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compatible = "fsl,imx8mp-evk", "fsl,imx8mp";
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chosen {
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stdout-path = &uart2;
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};
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memory@40000000 {
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device_type = "memory";
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reg = <0x0 0x40000000 0 0xc0000000>,
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<0x1 0x00000000 0 0xc0000000>;
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};
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reg_usdhc2_vmmc: regulator-usdhc2 {
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compatible = "regulator-fixed";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
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regulator-name = "VSD_3V3";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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};
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};
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&fec {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_fec>;
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phy-mode = "rgmii-id";
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phy-handle = <ðphy1>;
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fsl,magic-packet;
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status = "okay";
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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ethphy1: ethernet-phy@1 {
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <1>;
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eee-broken-1000t;
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reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>;
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};
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};
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};
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&snvs_pwrkey {
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status = "okay";
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};
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&uart2 {
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/* console */
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart2>;
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status = "okay";
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};
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&usdhc2 {
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assigned-clocks = <&clk IMX8MP_CLK_USDHC2>;
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assigned-clock-rates = <400000000>;
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pinctrl-names = "default", "state_100mhz", "state_200mhz";
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pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
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pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
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pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
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cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
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vmmc-supply = <®_usdhc2_vmmc>;
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bus-width = <4>;
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status = "okay";
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};
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&usdhc3 {
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assigned-clocks = <&clk IMX8MP_CLK_USDHC3>;
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assigned-clock-rates = <400000000>;
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pinctrl-names = "default", "state_100mhz", "state_200mhz";
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pinctrl-0 = <&pinctrl_usdhc3>;
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pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
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pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
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bus-width = <8>;
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non-removable;
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status = "okay";
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};
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&wdog1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_wdog>;
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fsl,ext-reset-output;
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status = "okay";
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};
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&iomuxc {
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pinctrl-names = "default";
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pinctrl_fec: fecgrp {
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fsl,pins = <
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MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x3
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MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x3
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MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x91
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MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x91
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MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x91
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MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x91
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MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x91
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MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x91
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MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x1f
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MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x1f
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MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x1f
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MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x1f
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MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x1f
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MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x1f
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MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02 0x19
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>;
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};
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pinctrl_reg_usdhc2_vmmc: regusdhc2vmmc {
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fsl,pins = <
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MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x41
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>;
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};
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pinctrl_uart2: uart2grp {
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fsl,pins = <
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MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x49
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MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x49
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>;
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};
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pinctrl_usdhc2: usdhc2grp {
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fsl,pins = <
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MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190
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MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0
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MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0
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MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0
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MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0
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MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0
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MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
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>;
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};
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pinctrl_usdhc2_100mhz: usdhc2grp-100mhz {
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fsl,pins = <
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MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194
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MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4
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MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4
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MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4
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MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4
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MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4
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MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
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>;
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};
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pinctrl_usdhc2_200mhz: usdhc2grp-200mhz {
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fsl,pins = <
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MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196
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MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6
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MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6
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MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6
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MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6
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MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6
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MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
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>;
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};
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pinctrl_usdhc2_gpio: usdhc2grp-gpio {
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fsl,pins = <
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MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4
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>;
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};
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pinctrl_usdhc3: usdhc3grp {
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fsl,pins = <
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MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190
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MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0
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MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0
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MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0
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MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0
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MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0
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MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0
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MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0
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MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0
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MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0
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MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190
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>;
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};
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pinctrl_usdhc3_100mhz: usdhc3grp-100mhz {
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fsl,pins = <
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MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194
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MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4
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MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4
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MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4
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MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4
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MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4
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MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4
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MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4
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MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4
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MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4
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MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194
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>;
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};
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pinctrl_usdhc3_200mhz: usdhc3grp-200mhz {
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fsl,pins = <
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MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196
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MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6
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MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6
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MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6
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MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6
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MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6
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MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6
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MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6
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MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6
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MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6
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MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196
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>;
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};
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pinctrl_wdog: wdoggrp {
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fsl,pins = <
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MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0xc6
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>;
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};
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};
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