arch/x86/kernel/cpu/mcheck/p4.c: cleanups
SMP, the machine check exception dispatches all logical processors within a physical package to the machine-check exception handler, so the printk within each handler outputs concurrently and makes the output unreadable. Refer to Intel system programming guide Part 1 Section 7.8.5 http://developer.intel.com/design/processor/manuals/253668.pdf Signed-off-by: Min Zhang <mzhang@mvista.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
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Родитель
8b2cb7a8f5
Коммит
9e8b6d90ac
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@ -33,21 +33,24 @@ static void k7_machine_check(struct pt_regs * regs, long error_code)
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for (i=1; i<nr_mce_banks; i++) {
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rdmsr (MSR_IA32_MC0_STATUS+i*4,low, high);
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if (high&(1<<31)) {
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char misc[20];
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char addr[24];
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misc[0] = addr[0] = '\0';
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if (high & (1<<29))
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recover |= 1;
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if (high & (1<<25))
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recover |= 2;
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printk (KERN_EMERG "Bank %d: %08x%08x", i, high, low);
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high &= ~(1<<31);
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if (high & (1<<27)) {
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rdmsr (MSR_IA32_MC0_MISC+i*4, alow, ahigh);
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printk ("[%08x%08x]", ahigh, alow);
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snprintf (misc, 20, "[%08x%08x]", ahigh, alow);
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}
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if (high & (1<<26)) {
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rdmsr (MSR_IA32_MC0_ADDR+i*4, alow, ahigh);
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printk (" at %08x%08x", ahigh, alow);
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snprintf (addr, 24, " at %08x%08x", ahigh, alow);
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}
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printk ("\n");
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printk (KERN_EMERG "CPU %d: Bank %d: %08x%08x%s%s\n",
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smp_processor_id(), i, high, low, misc, addr);
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/* Clear it */
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wrmsr (MSR_IA32_MC0_STATUS+i*4, 0UL, 0UL);
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/* Serialize */
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@ -158,32 +158,35 @@ static void intel_machine_check(struct pt_regs * regs, long error_code)
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if (mce_num_extended_msrs > 0) {
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struct intel_mce_extended_msrs dbg;
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intel_get_extended_msrs(&dbg);
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printk (KERN_DEBUG "CPU %d: EIP: %08x EFLAGS: %08x\n",
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smp_processor_id(), dbg.eip, dbg.eflags);
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printk (KERN_DEBUG "\teax: %08x ebx: %08x ecx: %08x edx: %08x\n",
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dbg.eax, dbg.ebx, dbg.ecx, dbg.edx);
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printk (KERN_DEBUG "\tesi: %08x edi: %08x ebp: %08x esp: %08x\n",
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printk (KERN_DEBUG "CPU %d: EIP: %08x EFLAGS: %08x\n"
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"\teax: %08x ebx: %08x ecx: %08x edx: %08x\n"
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"\tesi: %08x edi: %08x ebp: %08x esp: %08x\n",
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smp_processor_id(), dbg.eip, dbg.eflags,
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dbg.eax, dbg.ebx, dbg.ecx, dbg.edx,
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dbg.esi, dbg.edi, dbg.ebp, dbg.esp);
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}
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for (i=0; i<nr_mce_banks; i++) {
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rdmsr (MSR_IA32_MC0_STATUS+i*4,low, high);
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if (high & (1<<31)) {
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char misc[20];
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char addr[24];
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misc[0] = addr[0] = '\0';
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if (high & (1<<29))
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recover |= 1;
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if (high & (1<<25))
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recover |= 2;
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printk (KERN_EMERG "Bank %d: %08x%08x", i, high, low);
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high &= ~(1<<31);
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if (high & (1<<27)) {
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rdmsr (MSR_IA32_MC0_MISC+i*4, alow, ahigh);
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printk ("[%08x%08x]", ahigh, alow);
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snprintf (misc, 20, "[%08x%08x]", ahigh, alow);
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}
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if (high & (1<<26)) {
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rdmsr (MSR_IA32_MC0_ADDR+i*4, alow, ahigh);
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printk (" at %08x%08x", ahigh, alow);
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snprintf (addr, 24, " at %08x%08x", ahigh, alow);
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}
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printk ("\n");
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printk (KERN_EMERG "CPU %d: Bank %d: %08x%08x%s%s\n",
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smp_processor_id(), i, high, low, misc, addr);
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}
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}
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@ -33,21 +33,24 @@ static void intel_machine_check(struct pt_regs * regs, long error_code)
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for (i=0; i<nr_mce_banks; i++) {
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rdmsr (MSR_IA32_MC0_STATUS+i*4,low, high);
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if (high & (1<<31)) {
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char misc[20];
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char addr[24];
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misc[0] = addr[0] = '\0';
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if (high & (1<<29))
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recover |= 1;
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if (high & (1<<25))
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recover |= 2;
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printk (KERN_EMERG "Bank %d: %08x%08x", i, high, low);
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high &= ~(1<<31);
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if (high & (1<<27)) {
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rdmsr (MSR_IA32_MC0_MISC+i*4, alow, ahigh);
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printk ("[%08x%08x]", ahigh, alow);
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snprintf (misc, 20, "[%08x%08x]", ahigh, alow);
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}
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if (high & (1<<26)) {
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rdmsr (MSR_IA32_MC0_ADDR+i*4, alow, ahigh);
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printk (" at %08x%08x", ahigh, alow);
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snprintf (addr, 24, " at %08x%08x", ahigh, alow);
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}
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printk ("\n");
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printk (KERN_EMERG "CPU %d: Bank %d: %08x%08x%s%s\n",
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smp_processor_id(), i, high, low, misc, addr);
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}
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}
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