[POWERPC] 86xx/85xx: Unify Freescale PCI Express memory map registers structure
Unify PCI Express memory map registers structure define to arch/pwoerpc/sysdev/fsl_pcie.h for Freescale 85xx/86xx processor family. Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This commit is contained in:
Zang Roy-r61911
Kumar Gala
Родитель
3e4e97f42e
Коммит
9eb90a0c3b
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@ -22,9 +22,9 @@
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#include <asm/atomic.h>
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#include <asm/io.h>
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#include <asm/prom.h>
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#include <asm/immap_86xx.h>
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#include <asm/pci-bridge.h>
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#include <sysdev/fsl_soc.h>
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#include <sysdev/fsl_pcie.h>
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#include "mpc86xx.h"
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@ -0,0 +1,94 @@
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/*
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* MPC85xx/86xx PCI Express structure define
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*
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* Copyright 2007 Freescale Semiconductor, Inc
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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*/
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#ifdef __KERNEL__
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#ifndef __POWERPC_FSL_PCIE_H
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#define __POWERPC_FSL_PCIE_H
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/* PCIE Express IO block registers in 85xx/86xx */
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struct ccsr_pex {
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__be32 __iomem pex_config_addr; /* 0x.000 - PCI Express Configuration Address Register */
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__be32 __iomem pex_config_data; /* 0x.004 - PCI Express Configuration Data Register */
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u8 __iomem res1[4];
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__be32 __iomem pex_otb_cpl_tor; /* 0x.00c - PCI Express Outbound completion timeout register */
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__be32 __iomem pex_conf_tor; /* 0x.010 - PCI Express configuration timeout register */
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u8 __iomem res2[12];
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__be32 __iomem pex_pme_mes_dr; /* 0x.020 - PCI Express PME and message detect register */
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__be32 __iomem pex_pme_mes_disr; /* 0x.024 - PCI Express PME and message disable register */
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__be32 __iomem pex_pme_mes_ier; /* 0x.028 - PCI Express PME and message interrupt enable register */
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__be32 __iomem pex_pmcr; /* 0x.02c - PCI Express power management command register */
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u8 __iomem res3[3024];
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__be32 __iomem pexotar0; /* 0x.c00 - PCI Express outbound translation address register 0 */
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__be32 __iomem pexotear0; /* 0x.c04 - PCI Express outbound translation extended address register 0*/
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u8 __iomem res4[8];
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__be32 __iomem pexowar0; /* 0x.c10 - PCI Express outbound window attributes register 0*/
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u8 __iomem res5[12];
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__be32 __iomem pexotar1; /* 0x.c20 - PCI Express outbound translation address register 1 */
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__be32 __iomem pexotear1; /* 0x.c24 - PCI Express outbound translation extended address register 1*/
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__be32 __iomem pexowbar1; /* 0x.c28 - PCI Express outbound window base address register 1*/
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u8 __iomem res6[4];
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__be32 __iomem pexowar1; /* 0x.c30 - PCI Express outbound window attributes register 1*/
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u8 __iomem res7[12];
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__be32 __iomem pexotar2; /* 0x.c40 - PCI Express outbound translation address register 2 */
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__be32 __iomem pexotear2; /* 0x.c44 - PCI Express outbound translation extended address register 2*/
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__be32 __iomem pexowbar2; /* 0x.c48 - PCI Express outbound window base address register 2*/
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u8 __iomem res8[4];
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__be32 __iomem pexowar2; /* 0x.c50 - PCI Express outbound window attributes register 2*/
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u8 __iomem res9[12];
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__be32 __iomem pexotar3; /* 0x.c60 - PCI Express outbound translation address register 3 */
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__be32 __iomem pexotear3; /* 0x.c64 - PCI Express outbound translation extended address register 3*/
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__be32 __iomem pexowbar3; /* 0x.c68 - PCI Express outbound window base address register 3*/
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u8 __iomem res10[4];
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__be32 __iomem pexowar3; /* 0x.c70 - PCI Express outbound window attributes register 3*/
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u8 __iomem res11[12];
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__be32 __iomem pexotar4; /* 0x.c80 - PCI Express outbound translation address register 4 */
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__be32 __iomem pexotear4; /* 0x.c84 - PCI Express outbound translation extended address register 4*/
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__be32 __iomem pexowbar4; /* 0x.c88 - PCI Express outbound window base address register 4*/
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u8 __iomem res12[4];
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__be32 __iomem pexowar4; /* 0x.c90 - PCI Express outbound window attributes register 4*/
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u8 __iomem res13[12];
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u8 __iomem res14[256];
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__be32 __iomem pexitar3; /* 0x.da0 - PCI Express inbound translation address register 3 */
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u8 __iomem res15[4];
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__be32 __iomem pexiwbar3; /* 0x.da8 - PCI Express inbound window base address register 3 */
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__be32 __iomem pexiwbear3; /* 0x.dac - PCI Express inbound window base extended address register 3 */
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__be32 __iomem pexiwar3; /* 0x.db0 - PCI Express inbound window attributes register 3 */
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u8 __iomem res16[12];
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__be32 __iomem pexitar2; /* 0x.dc0 - PCI Express inbound translation address register 2 */
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u8 __iomem res17[4];
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__be32 __iomem pexiwbar2; /* 0x.dc8 - PCI Express inbound window base address register 2 */
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__be32 __iomem pexiwbear2; /* 0x.dcc - PCI Express inbound window base extended address register 2 */
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__be32 __iomem pexiwar2; /* 0x.dd0 - PCI Express inbound window attributes register 2 */
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u8 __iomem res18[12];
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__be32 __iomem pexitar1; /* 0x.de0 - PCI Express inbound translation address register 2 */
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u8 __iomem res19[4];
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__be32 __iomem pexiwbar1; /* 0x.de8 - PCI Express inbound window base address register 2 */
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__be32 __iomem pexiwbear1; /* 0x.dec - PCI Express inbound window base extended address register 2 */
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__be32 __iomem pexiwar1; /* 0x.df0 - PCI Express inbound window attributes register 2 */
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u8 __iomem res20[12];
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__be32 __iomem pex_err_dr; /* 0x.e00 - PCI Express error detect register */
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u8 __iomem res21[4];
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__be32 __iomem pex_err_en; /* 0x.e08 - PCI Express error interrupt enable register */
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u8 __iomem res22[4];
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__be32 __iomem pex_err_disr; /* 0x.e10 - PCI Express error disable register */
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u8 __iomem res23[12];
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__be32 __iomem pex_err_cap_stat; /* 0x.e20 - PCI Express error capture status register */
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u8 __iomem res24[4];
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__be32 __iomem pex_err_cap_r0; /* 0x.e28 - PCI Express error capture register 0 */
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__be32 __iomem pex_err_cap_r1; /* 0x.e2c - PCI Express error capture register 0 */
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__be32 __iomem pex_err_cap_r2; /* 0x.e30 - PCI Express error capture register 0 */
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__be32 __iomem pex_err_cap_r3; /* 0x.e34 - PCI Express error capture register 0 */
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};
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#endif /* __POWERPC_FSL_PCIE_H */
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#endif /* __KERNEL__ */
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@ -85,81 +85,6 @@ typedef struct ccsr_pci {
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char res19[472];
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} ccsr_pci_t;
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/* PCI Express Registers */
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typedef struct ccsr_pex {
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uint pex_config_addr; /* 0x.000 - PCI Express Configuration Address Register */
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uint pex_config_data; /* 0x.004 - PCI Express Configuration Data Register */
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char res1[4];
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uint pex_otb_cpl_tor; /* 0x.00c - PCI Express Outbound completion timeout register */
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uint pex_conf_tor; /* 0x.010 - PCI Express configuration timeout register */
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char res2[12];
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uint pex_pme_mes_dr; /* 0x.020 - PCI Express PME and message detect register */
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uint pex_pme_mes_disr; /* 0x.024 - PCI Express PME and message disable register */
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uint pex_pme_mes_ier; /* 0x.028 - PCI Express PME and message interrupt enable register */
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uint pex_pmcr; /* 0x.02c - PCI Express power management command register */
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char res3[3024];
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uint pexotar0; /* 0x.c00 - PCI Express outbound translation address register 0 */
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uint pexotear0; /* 0x.c04 - PCI Express outbound translation extended address register 0*/
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char res4[8];
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uint pexowar0; /* 0x.c10 - PCI Express outbound window attributes register 0*/
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char res5[12];
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uint pexotar1; /* 0x.c20 - PCI Express outbound translation address register 1 */
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uint pexotear1; /* 0x.c24 - PCI Express outbound translation extended address register 1*/
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uint pexowbar1; /* 0x.c28 - PCI Express outbound window base address register 1*/
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char res6[4];
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uint pexowar1; /* 0x.c30 - PCI Express outbound window attributes register 1*/
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char res7[12];
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uint pexotar2; /* 0x.c40 - PCI Express outbound translation address register 2 */
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uint pexotear2; /* 0x.c44 - PCI Express outbound translation extended address register 2*/
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uint pexowbar2; /* 0x.c48 - PCI Express outbound window base address register 2*/
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char res8[4];
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uint pexowar2; /* 0x.c50 - PCI Express outbound window attributes register 2*/
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char res9[12];
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uint pexotar3; /* 0x.c60 - PCI Express outbound translation address register 3 */
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uint pexotear3; /* 0x.c64 - PCI Express outbound translation extended address register 3*/
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uint pexowbar3; /* 0x.c68 - PCI Express outbound window base address register 3*/
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char res10[4];
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uint pexowar3; /* 0x.c70 - PCI Express outbound window attributes register 3*/
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char res11[12];
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uint pexotar4; /* 0x.c80 - PCI Express outbound translation address register 4 */
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uint pexotear4; /* 0x.c84 - PCI Express outbound translation extended address register 4*/
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uint pexowbar4; /* 0x.c88 - PCI Express outbound window base address register 4*/
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char res12[4];
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uint pexowar4; /* 0x.c90 - PCI Express outbound window attributes register 4*/
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char res13[12];
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char res14[256];
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uint pexitar3; /* 0x.da0 - PCI Express inbound translation address register 3 */
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char res15[4];
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uint pexiwbar3; /* 0x.da8 - PCI Express inbound window base address register 3 */
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uint pexiwbear3; /* 0x.dac - PCI Express inbound window base extended address register 3 */
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uint pexiwar3; /* 0x.db0 - PCI Express inbound window attributes register 3 */
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char res16[12];
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uint pexitar2; /* 0x.dc0 - PCI Express inbound translation address register 2 */
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char res17[4];
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uint pexiwbar2; /* 0x.dc8 - PCI Express inbound window base address register 2 */
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uint pexiwbear2; /* 0x.dcc - PCI Express inbound window base extended address register 2 */
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uint pexiwar2; /* 0x.dd0 - PCI Express inbound window attributes register 2 */
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char res18[12];
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uint pexitar1; /* 0x.de0 - PCI Express inbound translation address register 2 */
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char res19[4];
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uint pexiwbar1; /* 0x.de8 - PCI Express inbound window base address register 2 */
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uint pexiwbear1; /* 0x.dec - PCI Express inbound window base extended address register 2 */
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uint pexiwar1; /* 0x.df0 - PCI Express inbound window attributes register 2 */
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char res20[12];
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uint pex_err_dr; /* 0x.e00 - PCI Express error detect register */
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char res21[4];
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uint pex_err_en; /* 0x.e08 - PCI Express error interrupt enable register */
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char res22[4];
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uint pex_err_disr; /* 0x.e10 - PCI Express error disable register */
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char res23[12];
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uint pex_err_cap_stat; /* 0x.e20 - PCI Express error capture status register */
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char res24[4];
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uint pex_err_cap_r0; /* 0x.e28 - PCI Express error capture register 0 */
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uint pex_err_cap_r1; /* 0x.e2c - PCI Express error capture register 0 */
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uint pex_err_cap_r2; /* 0x.e30 - PCI Express error capture register 0 */
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uint pex_err_cap_r3; /* 0x.e34 - PCI Express error capture register 0 */
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} ccsr_pex_t;
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/* Global Utility Registers */
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typedef struct ccsr_guts {
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uint porpllsr; /* 0x.0000 - POR PLL Ratio Status Register */
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