ARM: dts: socfpga: Add unit name to clock nodes
Most clock nodes in Arria5, Cyclone5 and Arria10 have a reg property but does not have a unit name. This will trigger several warnings like this one (when compiled with W=1): Node /soc/clkmgr@ffd04000/clocks/periph_pll has a reg or ranges property, but no unit name Add the corresponding unit name to each node. Signed-off-by: Florian Vaussard <florian.vaussard@heig-vd.ch> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
This commit is contained in:
Florian Vaussard
Dinh Nguyen
Родитель
c1ae3cfa0e
Коммит
9f24e81659
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@ -145,7 +145,7 @@
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compatible = "fixed-clock";
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};
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main_pll: main_pll {
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main_pll: main_pll@40 {
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#address-cells = <1>;
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#size-cells = <0>;
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#clock-cells = <0>;
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@ -153,7 +153,7 @@
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clocks = <&osc1>;
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reg = <0x40>;
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mpuclk: mpuclk {
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mpuclk: mpuclk@48 {
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#clock-cells = <0>;
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compatible = "altr,socfpga-perip-clk";
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clocks = <&main_pll>;
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@ -161,7 +161,7 @@
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reg = <0x48>;
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};
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mainclk: mainclk {
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mainclk: mainclk@4c {
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#clock-cells = <0>;
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compatible = "altr,socfpga-perip-clk";
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clocks = <&main_pll>;
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@ -169,7 +169,7 @@
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reg = <0x4C>;
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};
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dbg_base_clk: dbg_base_clk {
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dbg_base_clk: dbg_base_clk@50 {
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#clock-cells = <0>;
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compatible = "altr,socfpga-perip-clk";
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clocks = <&main_pll>, <&osc1>;
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@ -177,21 +177,21 @@
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reg = <0x50>;
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};
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main_qspi_clk: main_qspi_clk {
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main_qspi_clk: main_qspi_clk@54 {
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#clock-cells = <0>;
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compatible = "altr,socfpga-perip-clk";
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clocks = <&main_pll>;
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reg = <0x54>;
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};
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main_nand_sdmmc_clk: main_nand_sdmmc_clk {
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main_nand_sdmmc_clk: main_nand_sdmmc_clk@58 {
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#clock-cells = <0>;
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compatible = "altr,socfpga-perip-clk";
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clocks = <&main_pll>;
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reg = <0x58>;
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};
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cfg_h2f_usr0_clk: cfg_h2f_usr0_clk {
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cfg_h2f_usr0_clk: cfg_h2f_usr0_clk@5c {
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#clock-cells = <0>;
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compatible = "altr,socfpga-perip-clk";
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clocks = <&main_pll>;
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@ -199,7 +199,7 @@
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};
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};
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periph_pll: periph_pll {
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periph_pll: periph_pll@80 {
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#address-cells = <1>;
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#size-cells = <0>;
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#clock-cells = <0>;
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@ -207,42 +207,42 @@
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clocks = <&osc1>, <&osc2>, <&f2s_periph_ref_clk>;
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reg = <0x80>;
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emac0_clk: emac0_clk {
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emac0_clk: emac0_clk@88 {
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#clock-cells = <0>;
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compatible = "altr,socfpga-perip-clk";
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clocks = <&periph_pll>;
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reg = <0x88>;
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};
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emac1_clk: emac1_clk {
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emac1_clk: emac1_clk@8c {
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#clock-cells = <0>;
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compatible = "altr,socfpga-perip-clk";
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clocks = <&periph_pll>;
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reg = <0x8C>;
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};
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per_qspi_clk: per_qsi_clk {
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per_qspi_clk: per_qsi_clk@90 {
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#clock-cells = <0>;
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compatible = "altr,socfpga-perip-clk";
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clocks = <&periph_pll>;
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reg = <0x90>;
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};
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per_nand_mmc_clk: per_nand_mmc_clk {
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per_nand_mmc_clk: per_nand_mmc_clk@94 {
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#clock-cells = <0>;
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compatible = "altr,socfpga-perip-clk";
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clocks = <&periph_pll>;
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reg = <0x94>;
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};
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per_base_clk: per_base_clk {
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per_base_clk: per_base_clk@98 {
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#clock-cells = <0>;
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compatible = "altr,socfpga-perip-clk";
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clocks = <&periph_pll>;
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reg = <0x98>;
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};
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h2f_usr1_clk: h2f_usr1_clk {
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h2f_usr1_clk: h2f_usr1_clk@9c {
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#clock-cells = <0>;
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compatible = "altr,socfpga-perip-clk";
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clocks = <&periph_pll>;
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@ -250,7 +250,7 @@
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};
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};
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sdram_pll: sdram_pll {
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sdram_pll: sdram_pll@c0 {
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#address-cells = <1>;
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#size-cells = <0>;
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#clock-cells = <0>;
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@ -258,28 +258,28 @@
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clocks = <&osc1>, <&osc2>, <&f2s_sdram_ref_clk>;
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reg = <0xC0>;
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ddr_dqs_clk: ddr_dqs_clk {
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ddr_dqs_clk: ddr_dqs_clk@c8 {
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#clock-cells = <0>;
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compatible = "altr,socfpga-perip-clk";
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clocks = <&sdram_pll>;
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reg = <0xC8>;
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};
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ddr_2x_dqs_clk: ddr_2x_dqs_clk {
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ddr_2x_dqs_clk: ddr_2x_dqs_clk@cc {
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#clock-cells = <0>;
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compatible = "altr,socfpga-perip-clk";
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clocks = <&sdram_pll>;
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reg = <0xCC>;
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};
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ddr_dq_clk: ddr_dq_clk {
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ddr_dq_clk: ddr_dq_clk@d0 {
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#clock-cells = <0>;
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compatible = "altr,socfpga-perip-clk";
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clocks = <&sdram_pll>;
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reg = <0xD0>;
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};
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h2f_usr2_clk: h2f_usr2_clk {
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h2f_usr2_clk: h2f_usr2_clk@d4 {
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#clock-cells = <0>;
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compatible = "altr,socfpga-perip-clk";
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clocks = <&sdram_pll>;
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@ -119,7 +119,7 @@
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compatible = "fixed-clock";
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};
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main_pll: main_pll {
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main_pll: main_pll@40 {
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#address-cells = <1>;
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#size-cells = <0>;
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#clock-cells = <0>;
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@ -142,35 +142,35 @@
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div-reg = <0x144 0 11>;
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};
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main_emaca_clk: main_emaca_clk {
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main_emaca_clk: main_emaca_clk@68 {
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#clock-cells = <0>;
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compatible = "altr,socfpga-a10-perip-clk";
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clocks = <&main_pll>;
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reg = <0x68>;
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};
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main_emacb_clk: main_emacb_clk {
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main_emacb_clk: main_emacb_clk@6c {
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#clock-cells = <0>;
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compatible = "altr,socfpga-a10-perip-clk";
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clocks = <&main_pll>;
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reg = <0x6C>;
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};
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main_emac_ptp_clk: main_emac_ptp_clk {
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main_emac_ptp_clk: main_emac_ptp_clk@70 {
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#clock-cells = <0>;
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compatible = "altr,socfpga-a10-perip-clk";
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clocks = <&main_pll>;
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reg = <0x70>;
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};
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main_gpio_db_clk: main_gpio_db_clk {
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main_gpio_db_clk: main_gpio_db_clk@74 {
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#clock-cells = <0>;
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compatible = "altr,socfpga-a10-perip-clk";
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clocks = <&main_pll>;
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reg = <0x74>;
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};
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main_sdmmc_clk: main_sdmmc_clk {
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main_sdmmc_clk: main_sdmmc_clk@78 {
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#clock-cells = <0>;
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compatible = "altr,socfpga-a10-perip-clk"
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;
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@ -178,28 +178,28 @@
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reg = <0x78>;
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};
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main_s2f_usr0_clk: main_s2f_usr0_clk {
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main_s2f_usr0_clk: main_s2f_usr0_clk@7c {
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#clock-cells = <0>;
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compatible = "altr,socfpga-a10-perip-clk";
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clocks = <&main_pll>;
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reg = <0x7C>;
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};
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main_s2f_usr1_clk: main_s2f_usr1_clk {
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main_s2f_usr1_clk: main_s2f_usr1_clk@80 {
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#clock-cells = <0>;
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compatible = "altr,socfpga-a10-perip-clk";
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clocks = <&main_pll>;
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reg = <0x80>;
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};
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main_hmc_pll_ref_clk: main_hmc_pll_ref_clk {
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main_hmc_pll_ref_clk: main_hmc_pll_ref_clk@84 {
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#clock-cells = <0>;
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compatible = "altr,socfpga-a10-perip-clk";
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clocks = <&main_pll>;
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reg = <0x84>;
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};
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main_periph_ref_clk: main_periph_ref_clk {
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main_periph_ref_clk: main_periph_ref_clk@9c {
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#clock-cells = <0>;
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compatible = "altr,socfpga-a10-perip-clk";
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clocks = <&main_pll>;
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@ -207,7 +207,7 @@
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};
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};
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periph_pll: periph_pll {
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periph_pll: periph_pll@c0 {
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#address-cells = <1>;
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#size-cells = <0>;
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#clock-cells = <0>;
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@ -230,56 +230,56 @@
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div-reg = <0x144 16 11>;
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};
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peri_emaca_clk: peri_emaca_clk {
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peri_emaca_clk: peri_emaca_clk@e8 {
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#clock-cells = <0>;
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compatible = "altr,socfpga-a10-perip-clk";
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clocks = <&periph_pll>;
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reg = <0xE8>;
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};
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peri_emacb_clk: peri_emacb_clk {
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peri_emacb_clk: peri_emacb_clk@ec {
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#clock-cells = <0>;
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compatible = "altr,socfpga-a10-perip-clk";
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clocks = <&periph_pll>;
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reg = <0xEC>;
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};
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peri_emac_ptp_clk: peri_emac_ptp_clk {
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peri_emac_ptp_clk: peri_emac_ptp_clk@f0 {
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#clock-cells = <0>;
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compatible = "altr,socfpga-a10-perip-clk";
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clocks = <&periph_pll>;
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reg = <0xF0>;
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};
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peri_gpio_db_clk: peri_gpio_db_clk {
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peri_gpio_db_clk: peri_gpio_db_clk@f4 {
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#clock-cells = <0>;
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compatible = "altr,socfpga-a10-perip-clk";
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clocks = <&periph_pll>;
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reg = <0xF4>;
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};
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peri_sdmmc_clk: peri_sdmmc_clk {
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peri_sdmmc_clk: peri_sdmmc_clk@f8 {
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#clock-cells = <0>;
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compatible = "altr,socfpga-a10-perip-clk";
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clocks = <&periph_pll>;
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reg = <0xF8>;
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};
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peri_s2f_usr0_clk: peri_s2f_usr0_clk {
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peri_s2f_usr0_clk: peri_s2f_usr0_clk@fc {
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#clock-cells = <0>;
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compatible = "altr,socfpga-a10-perip-clk";
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clocks = <&periph_pll>;
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reg = <0xFC>;
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};
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peri_s2f_usr1_clk: peri_s2f_usr1_clk {
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peri_s2f_usr1_clk: peri_s2f_usr1_clk@100 {
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#clock-cells = <0>;
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compatible = "altr,socfpga-a10-perip-clk";
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clocks = <&periph_pll>;
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reg = <0x100>;
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};
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peri_hmc_pll_ref_clk: peri_hmc_pll_ref_clk {
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peri_hmc_pll_ref_clk: peri_hmc_pll_ref_clk@104 {
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#clock-cells = <0>;
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compatible = "altr,socfpga-a10-perip-clk";
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clocks = <&periph_pll>;
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@ -287,7 +287,7 @@
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};
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};
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mpu_free_clk: mpu_free_clk {
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mpu_free_clk: mpu_free_clk@60 {
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#clock-cells = <0>;
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compatible = "altr,socfpga-a10-perip-clk";
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clocks = <&main_mpu_base_clk>, <&peri_mpu_base_clk>,
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@ -296,7 +296,7 @@
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reg = <0x60>;
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};
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noc_free_clk: noc_free_clk {
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noc_free_clk: noc_free_clk@64 {
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#clock-cells = <0>;
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compatible = "altr,socfpga-a10-perip-clk";
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clocks = <&main_noc_base_clk>, <&peri_noc_base_clk>,
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@ -305,7 +305,7 @@
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reg = <0x64>;
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};
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s2f_user1_free_clk: s2f_user1_free_clk {
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s2f_user1_free_clk: s2f_user1_free_clk@104 {
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#clock-cells = <0>;
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compatible = "altr,socfpga-a10-perip-clk";
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clocks = <&main_s2f_usr1_clk>, <&peri_s2f_usr1_clk>,
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@ -314,7 +314,7 @@
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reg = <0x104>;
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};
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sdmmc_free_clk: sdmmc_free_clk {
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sdmmc_free_clk: sdmmc_free_clk@f8 {
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#clock-cells = <0>;
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compatible = "altr,socfpga-a10-perip-clk";
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clocks = <&main_sdmmc_clk>, <&peri_sdmmc_clk>,
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