net/fsl: introduce Freescale 10G MDIO driver
Similar to fsl_pq_mdio.c, this driver is for the 10G MDIO controller on Freescale Frame Manager Ethernet controllers. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Timur Tabi
David S. Miller
Родитель
3afa6d00fb
Коммит
9f35a7342c
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@ -62,6 +62,13 @@ config FSL_PQ_MDIO
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---help---
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This driver supports the MDIO bus used by the gianfar and UCC drivers.
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config FSL_XGMAC_MDIO
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tristate "Freescale XGMAC MDIO"
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depends on FSL_SOC
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select PHYLIB
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---help---
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This driver supports the MDIO bus on the Fman 10G Ethernet MACs.
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config UCC_GETH
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tristate "Freescale QE Gigabit Ethernet"
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depends on QUICC_ENGINE
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@ -9,6 +9,7 @@ ifeq ($(CONFIG_FEC_MPC52xx_MDIO),y)
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endif
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obj-$(CONFIG_FS_ENET) += fs_enet/
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obj-$(CONFIG_FSL_PQ_MDIO) += fsl_pq_mdio.o
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obj-$(CONFIG_FSL_XGMAC_MDIO) += xgmac_mdio.o
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obj-$(CONFIG_GIANFAR) += gianfar_driver.o
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obj-$(CONFIG_PTP_1588_CLOCK_GIANFAR) += gianfar_ptp.o
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gianfar_driver-objs := gianfar.o \
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@ -0,0 +1,274 @@
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/*
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* QorIQ 10G MDIO Controller
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*
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* Copyright 2012 Freescale Semiconductor, Inc.
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*
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* Authors: Andy Fleming <afleming@freescale.com>
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* Timur Tabi <timur@freescale.com>
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*
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* This file is licensed under the terms of the GNU General Public License
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* version 2. This program is licensed "as is" without any warranty of any
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* kind, whether express or implied.
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*/
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#include <linux/kernel.h>
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#include <linux/slab.h>
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#include <linux/interrupt.h>
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#include <linux/module.h>
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#include <linux/phy.h>
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#include <linux/mdio.h>
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#include <linux/of_platform.h>
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#include <linux/of_mdio.h>
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/* Number of microseconds to wait for a register to respond */
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#define TIMEOUT 1000
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struct tgec_mdio_controller {
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__be32 reserved[12];
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__be32 mdio_stat; /* MDIO configuration and status */
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__be32 mdio_ctl; /* MDIO control */
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__be32 mdio_data; /* MDIO data */
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__be32 mdio_addr; /* MDIO address */
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} __packed;
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#define MDIO_STAT_CLKDIV(x) (((x>>1) & 0xff) << 8)
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#define MDIO_STAT_BSY (1 << 0)
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#define MDIO_STAT_RD_ER (1 << 1)
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#define MDIO_CTL_DEV_ADDR(x) (x & 0x1f)
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#define MDIO_CTL_PORT_ADDR(x) ((x & 0x1f) << 5)
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#define MDIO_CTL_PRE_DIS (1 << 10)
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#define MDIO_CTL_SCAN_EN (1 << 11)
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#define MDIO_CTL_POST_INC (1 << 14)
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#define MDIO_CTL_READ (1 << 15)
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#define MDIO_DATA(x) (x & 0xffff)
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#define MDIO_DATA_BSY (1 << 31)
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/*
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* Wait untill the MDIO bus is free
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*/
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static int xgmac_wait_until_free(struct device *dev,
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struct tgec_mdio_controller __iomem *regs)
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{
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uint32_t status;
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/* Wait till the bus is free */
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status = spin_event_timeout(
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!((in_be32(®s->mdio_stat)) & MDIO_STAT_BSY), TIMEOUT, 0);
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if (!status) {
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dev_err(dev, "timeout waiting for bus to be free\n");
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return -ETIMEDOUT;
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}
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return 0;
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}
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/*
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* Wait till the MDIO read or write operation is complete
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*/
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static int xgmac_wait_until_done(struct device *dev,
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struct tgec_mdio_controller __iomem *regs)
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{
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uint32_t status;
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/* Wait till the MDIO write is complete */
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status = spin_event_timeout(
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!((in_be32(®s->mdio_data)) & MDIO_DATA_BSY), TIMEOUT, 0);
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if (!status) {
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dev_err(dev, "timeout waiting for operation to complete\n");
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return -ETIMEDOUT;
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}
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return 0;
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}
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/*
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* Write value to the PHY for this device to the register at regnum,waiting
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* until the write is done before it returns. All PHY configuration has to be
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* done through the TSEC1 MIIM regs.
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*/
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static int xgmac_mdio_write(struct mii_bus *bus, int phy_id, int regnum, u16 value)
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{
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struct tgec_mdio_controller __iomem *regs = bus->priv;
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uint16_t dev_addr = regnum >> 16;
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int ret;
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/* Setup the MII Mgmt clock speed */
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out_be32(®s->mdio_stat, MDIO_STAT_CLKDIV(100));
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ret = xgmac_wait_until_free(&bus->dev, regs);
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if (ret)
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return ret;
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/* Set the port and dev addr */
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out_be32(®s->mdio_ctl,
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MDIO_CTL_PORT_ADDR(phy_id) | MDIO_CTL_DEV_ADDR(dev_addr));
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/* Set the register address */
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out_be32(®s->mdio_addr, regnum & 0xffff);
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ret = xgmac_wait_until_free(&bus->dev, regs);
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if (ret)
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return ret;
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/* Write the value to the register */
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out_be32(®s->mdio_data, MDIO_DATA(value));
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ret = xgmac_wait_until_done(&bus->dev, regs);
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if (ret)
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return ret;
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return 0;
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}
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/*
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* Reads from register regnum in the PHY for device dev, returning the value.
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* Clears miimcom first. All PHY configuration has to be done through the
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* TSEC1 MIIM regs.
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*/
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static int xgmac_mdio_read(struct mii_bus *bus, int phy_id, int regnum)
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{
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struct tgec_mdio_controller __iomem *regs = bus->priv;
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uint16_t dev_addr = regnum >> 16;
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uint32_t mdio_ctl;
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uint16_t value;
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int ret;
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/* Setup the MII Mgmt clock speed */
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out_be32(®s->mdio_stat, MDIO_STAT_CLKDIV(100));
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ret = xgmac_wait_until_free(&bus->dev, regs);
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if (ret)
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return ret;
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/* Set the Port and Device Addrs */
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mdio_ctl = MDIO_CTL_PORT_ADDR(phy_id) | MDIO_CTL_DEV_ADDR(dev_addr);
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out_be32(®s->mdio_ctl, mdio_ctl);
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/* Set the register address */
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out_be32(®s->mdio_addr, regnum & 0xffff);
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ret = xgmac_wait_until_free(&bus->dev, regs);
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if (ret)
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return ret;
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/* Initiate the read */
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out_be32(®s->mdio_ctl, mdio_ctl | MDIO_CTL_READ);
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ret = xgmac_wait_until_done(&bus->dev, regs);
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if (ret)
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return ret;
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/* Return all Fs if nothing was there */
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if (in_be32(®s->mdio_stat) & MDIO_STAT_RD_ER) {
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dev_err(&bus->dev, "MDIO read error\n");
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return 0xffff;
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}
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value = in_be32(®s->mdio_data) & 0xffff;
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dev_dbg(&bus->dev, "read %04x\n", value);
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return value;
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}
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/* Reset the MIIM registers, and wait for the bus to free */
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static int xgmac_mdio_reset(struct mii_bus *bus)
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{
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struct tgec_mdio_controller __iomem *regs = bus->priv;
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int ret;
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mutex_lock(&bus->mdio_lock);
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/* Setup the MII Mgmt clock speed */
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out_be32(®s->mdio_stat, MDIO_STAT_CLKDIV(100));
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ret = xgmac_wait_until_free(&bus->dev, regs);
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mutex_unlock(&bus->mdio_lock);
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return ret;
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}
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static int __devinit xgmac_mdio_probe(struct platform_device *pdev)
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{
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struct device_node *np = pdev->dev.of_node;
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struct mii_bus *bus;
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struct resource res;
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int ret;
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ret = of_address_to_resource(np, 0, &res);
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if (ret) {
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dev_err(&pdev->dev, "could not obtain address\n");
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return ret;
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}
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bus = mdiobus_alloc_size(PHY_MAX_ADDR * sizeof(int));
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if (!bus)
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return -ENOMEM;
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bus->name = "Freescale XGMAC MDIO Bus";
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bus->read = xgmac_mdio_read;
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bus->write = xgmac_mdio_write;
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bus->reset = xgmac_mdio_reset;
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bus->irq = bus->priv;
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bus->parent = &pdev->dev;
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snprintf(bus->id, MII_BUS_ID_SIZE, "%llx", (unsigned long long)res.start);
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/* Set the PHY base address */
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bus->priv = of_iomap(np, 0);
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if (!bus->priv) {
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ret = -ENOMEM;
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goto err_ioremap;
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}
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ret = of_mdiobus_register(bus, np);
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if (ret) {
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dev_err(&pdev->dev, "cannot register MDIO bus\n");
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goto err_registration;
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}
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dev_set_drvdata(&pdev->dev, bus);
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return 0;
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err_registration:
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iounmap(bus->priv);
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err_ioremap:
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mdiobus_free(bus);
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return ret;
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}
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static int __devexit xgmac_mdio_remove(struct platform_device *pdev)
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{
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struct mii_bus *bus = dev_get_drvdata(&pdev->dev);
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mdiobus_unregister(bus);
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iounmap(bus->priv);
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mdiobus_free(bus);
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return 0;
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}
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static struct of_device_id xgmac_mdio_match[] = {
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{
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.compatible = "fsl,fman-xmdio",
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},
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{},
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};
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MODULE_DEVICE_TABLE(of, xgmac_mdio_match);
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static struct platform_driver xgmac_mdio_driver = {
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.driver = {
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.name = "fsl-fman_xmdio",
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.of_match_table = xgmac_mdio_match,
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},
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.probe = xgmac_mdio_probe,
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.remove = xgmac_mdio_remove,
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};
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module_platform_driver(xgmac_mdio_driver);
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MODULE_DESCRIPTION("Freescale QorIQ 10G MDIO Controller");
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MODULE_LICENSE("GPL v2");
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