Merge branch 'master' of master.kernel.org:/pub/scm/linux/kernel/git/davem/sparc-2.6
This commit is contained in:
Коммит
9fafbd8061
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@ -5,4 +5,17 @@
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#else
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#include <asm/io_32.h>
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#endif
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/*
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* Defines used for both SPARC32 and SPARC64
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*/
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/* Big endian versions of memory read/write routines */
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#define readb_be(__addr) __raw_readb(__addr)
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#define readw_be(__addr) __raw_readw(__addr)
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#define readl_be(__addr) __raw_readl(__addr)
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#define writeb_be(__b, __addr) __raw_writeb(__b, __addr)
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#define writel_be(__w, __addr) __raw_writel(__w, __addr)
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#define writew_be(__l, __addr) __raw_writew(__l, __addr)
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#endif
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@ -165,7 +165,7 @@ static int __devinit apc_probe(struct platform_device *op)
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return 0;
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}
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static struct of_device_id __initdata apc_match[] = {
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static struct of_device_id apc_match[] = {
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{
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.name = APC_OBPNAME,
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},
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@ -69,7 +69,7 @@ static int __devinit pmc_probe(struct platform_device *op)
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return 0;
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}
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static struct of_device_id __initdata pmc_match[] = {
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static struct of_device_id pmc_match[] = {
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{
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.name = PMC_OBPNAME,
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},
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@ -51,6 +51,7 @@ cpumask_t smp_commenced_mask = CPU_MASK_NONE;
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void __cpuinit smp_store_cpu_info(int id)
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{
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int cpu_node;
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int mid;
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cpu_data(id).udelay_val = loops_per_jiffy;
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@ -58,10 +59,13 @@ void __cpuinit smp_store_cpu_info(int id)
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cpu_data(id).clock_tick = prom_getintdefault(cpu_node,
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"clock-frequency", 0);
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cpu_data(id).prom_node = cpu_node;
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cpu_data(id).mid = cpu_get_hwmid(cpu_node);
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mid = cpu_get_hwmid(cpu_node);
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if (cpu_data(id).mid < 0)
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panic("No MID found for CPU%d at node 0x%08d", id, cpu_node);
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if (mid < 0) {
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printk(KERN_NOTICE "No MID found for CPU%d at node 0x%08d", id, cpu_node);
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mid = 0;
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}
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cpu_data(id).mid = mid;
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}
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void __init smp_cpus_done(unsigned int max_cpus)
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@ -168,7 +168,7 @@ static int __devinit clock_probe(struct platform_device *op)
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return 0;
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}
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static struct of_device_id __initdata clock_match[] = {
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static struct of_device_id clock_match[] = {
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{
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.name = "eeprom",
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},
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@ -289,10 +289,16 @@ cc_end_cruft:
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/* Also, handle the alignment code out of band. */
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cc_dword_align:
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cmp %g1, 6
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bl,a ccte
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cmp %g1, 16
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bge 1f
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srl %g1, 1, %o3
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2: cmp %o3, 0
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be,a ccte
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andcc %g1, 0xf, %o3
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andcc %o0, 0x1, %g0
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andcc %o3, %o0, %g0 ! Check %o0 only (%o1 has the same last 2 bits)
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be,a 2b
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srl %o3, 1, %o3
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1: andcc %o0, 0x1, %g0
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bne ccslow
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andcc %o0, 0x2, %g0
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be 1f
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