ASoC: fsl_sai: Cleanups and 1:1 bclk:mclk ratio support
Merge series from Sascha Hauer <s.hauer@pengutronix.de>: This series has some updates for the fsl_sai driver: Some general cleanup patches, a bugfix in the ip revision checking and finally the mclk setting is made more accurate and support for 1:1 bclk:mclk setting is added.
This commit is contained in:
Mark Brown
Коммит
9fce18ab0b
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@ -62,7 +62,7 @@ static irqreturn_t fsl_sai_isr(int irq, void *devid)
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unsigned int ofs = sai->soc_data->reg_offset;
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struct device *dev = &sai->pdev->dev;
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u32 flags, xcsr, mask;
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bool irq_none = true;
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irqreturn_t iret = IRQ_NONE;
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/*
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* Both IRQ status bits and IRQ mask bits are in the xCSR but
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@ -76,7 +76,7 @@ static irqreturn_t fsl_sai_isr(int irq, void *devid)
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flags = xcsr & mask;
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if (flags)
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irq_none = false;
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iret = IRQ_HANDLED;
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else
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goto irq_rx;
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@ -110,7 +110,7 @@ irq_rx:
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flags = xcsr & mask;
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if (flags)
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irq_none = false;
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iret = IRQ_HANDLED;
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else
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goto out;
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@ -139,10 +139,7 @@ irq_rx:
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regmap_write(sai->regmap, FSL_SAI_RCSR(ofs), flags | xcsr);
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out:
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if (irq_none)
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return IRQ_NONE;
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else
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return IRQ_HANDLED;
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return iret;
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}
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static int fsl_sai_set_dai_tdm_slot(struct snd_soc_dai *cpu_dai, u32 tx_mask,
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@ -167,11 +164,10 @@ static int fsl_sai_set_dai_bclk_ratio(struct snd_soc_dai *dai,
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}
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static int fsl_sai_set_dai_sysclk_tr(struct snd_soc_dai *cpu_dai,
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int clk_id, unsigned int freq, int fsl_dir)
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int clk_id, unsigned int freq, bool tx)
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{
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struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
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unsigned int ofs = sai->soc_data->reg_offset;
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bool tx = fsl_dir == FSL_FMT_TRANSMITTER;
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u32 val_cr2 = 0;
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switch (clk_id) {
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@ -205,15 +201,13 @@ static int fsl_sai_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
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if (dir == SND_SOC_CLOCK_IN)
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return 0;
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ret = fsl_sai_set_dai_sysclk_tr(cpu_dai, clk_id, freq,
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FSL_FMT_TRANSMITTER);
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ret = fsl_sai_set_dai_sysclk_tr(cpu_dai, clk_id, freq, true);
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if (ret) {
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dev_err(cpu_dai->dev, "Cannot set tx sysclk: %d\n", ret);
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return ret;
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}
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ret = fsl_sai_set_dai_sysclk_tr(cpu_dai, clk_id, freq,
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FSL_FMT_RECEIVER);
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ret = fsl_sai_set_dai_sysclk_tr(cpu_dai, clk_id, freq, false);
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if (ret)
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dev_err(cpu_dai->dev, "Cannot set rx sysclk: %d\n", ret);
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@ -221,11 +215,10 @@ static int fsl_sai_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
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}
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static int fsl_sai_set_dai_fmt_tr(struct snd_soc_dai *cpu_dai,
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unsigned int fmt, int fsl_dir)
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unsigned int fmt, bool tx)
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{
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struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
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unsigned int ofs = sai->soc_data->reg_offset;
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bool tx = fsl_dir == FSL_FMT_TRANSMITTER;
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u32 val_cr2 = 0, val_cr4 = 0;
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if (!sai->is_lsb_first)
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@ -332,13 +325,13 @@ static int fsl_sai_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt)
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{
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int ret;
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ret = fsl_sai_set_dai_fmt_tr(cpu_dai, fmt, FSL_FMT_TRANSMITTER);
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ret = fsl_sai_set_dai_fmt_tr(cpu_dai, fmt, true);
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if (ret) {
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dev_err(cpu_dai->dev, "Cannot set tx format: %d\n", ret);
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return ret;
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}
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ret = fsl_sai_set_dai_fmt_tr(cpu_dai, fmt, FSL_FMT_RECEIVER);
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ret = fsl_sai_set_dai_fmt_tr(cpu_dai, fmt, false);
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if (ret)
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dev_err(cpu_dai->dev, "Cannot set rx format: %d\n", ret);
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@ -348,13 +341,13 @@ static int fsl_sai_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt)
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static int fsl_sai_set_bclk(struct snd_soc_dai *dai, bool tx, u32 freq)
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{
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struct fsl_sai *sai = snd_soc_dai_get_drvdata(dai);
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unsigned int ofs = sai->soc_data->reg_offset;
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unsigned int reg, ofs = sai->soc_data->reg_offset;
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unsigned long clk_rate;
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u32 savediv = 0, ratio, savesub = freq;
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u32 savediv = 0, ratio, bestdiff = freq;
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int adir = tx ? RX : TX;
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int dir = tx ? TX : RX;
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u32 id;
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int ret = 0;
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bool support_1_1_ratio = sai->verid.version >= 0x0301;
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/* Don't apply to consumer mode */
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if (sai->is_consumer_mode)
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@ -368,37 +361,41 @@ static int fsl_sai_set_bclk(struct snd_soc_dai *dai, bool tx, u32 freq)
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id = sai->soc_data->mclk0_is_mclk1 ? 1 : 0;
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for (; id < FSL_SAI_MCLK_MAX; id++) {
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int diff;
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clk_rate = clk_get_rate(sai->mclk_clk[id]);
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if (!clk_rate)
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continue;
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ratio = clk_rate / freq;
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ratio = DIV_ROUND_CLOSEST(clk_rate, freq);
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if (!ratio || ratio > 512)
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continue;
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if (ratio == 1 && !support_1_1_ratio)
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continue;
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else if (ratio & 1)
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continue;
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ret = clk_rate - ratio * freq;
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diff = abs((long)clk_rate - ratio * freq);
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/*
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* Drop the source that can not be
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* divided into the required rate.
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*/
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if (ret != 0 && clk_rate / ret < 1000)
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if (diff != 0 && clk_rate / diff < 1000)
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continue;
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dev_dbg(dai->dev,
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"ratio %d for freq %dHz based on clock %ldHz\n",
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ratio, freq, clk_rate);
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if (ratio % 2 == 0 && ratio >= 2 && ratio <= 512)
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ratio /= 2;
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else
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continue;
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if (ret < savesub) {
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if (diff < bestdiff) {
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savediv = ratio;
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sai->mclk_id[tx] = id;
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savesub = ret;
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bestdiff = diff;
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}
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if (ret == 0)
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if (diff == 0)
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break;
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}
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@ -408,6 +405,9 @@ static int fsl_sai_set_bclk(struct snd_soc_dai *dai, bool tx, u32 freq)
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return -EINVAL;
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}
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dev_dbg(dai->dev, "best fit: clock id=%d, div=%d, deviation =%d\n",
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sai->mclk_id[tx], savediv, bestdiff);
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/*
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* 1) For Asynchronous mode, we must set RCR2 register for capture, and
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* set TCR2 register for playback.
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@ -418,22 +418,24 @@ static int fsl_sai_set_bclk(struct snd_soc_dai *dai, bool tx, u32 freq)
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* 4) For Tx and Rx are both Synchronous with another SAI, we just
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* ignore it.
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*/
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if (fsl_sai_dir_is_synced(sai, adir)) {
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regmap_update_bits(sai->regmap, FSL_SAI_xCR2(!tx, ofs),
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FSL_SAI_CR2_MSEL_MASK,
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FSL_SAI_CR2_MSEL(sai->mclk_id[tx]));
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regmap_update_bits(sai->regmap, FSL_SAI_xCR2(!tx, ofs),
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FSL_SAI_CR2_DIV_MASK, savediv - 1);
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} else if (!sai->synchronous[dir]) {
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regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx, ofs),
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FSL_SAI_CR2_MSEL_MASK,
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FSL_SAI_CR2_MSEL(sai->mclk_id[tx]));
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regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx, ofs),
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FSL_SAI_CR2_DIV_MASK, savediv - 1);
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}
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if (fsl_sai_dir_is_synced(sai, adir))
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reg = FSL_SAI_xCR2(!tx, ofs);
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else if (!sai->synchronous[dir])
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reg = FSL_SAI_xCR2(tx, ofs);
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else
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return 0;
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dev_dbg(dai->dev, "best fit: clock id=%d, div=%d, deviation =%d\n",
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sai->mclk_id[tx], savediv, savesub);
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regmap_update_bits(sai->regmap, reg, FSL_SAI_CR2_MSEL_MASK,
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FSL_SAI_CR2_MSEL(sai->mclk_id[tx]));
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if (savediv == 1)
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regmap_update_bits(sai->regmap, reg,
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FSL_SAI_CR2_DIV_MASK | FSL_SAI_CR2_BYP,
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FSL_SAI_CR2_BYP);
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else
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regmap_update_bits(sai->regmap, reg,
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FSL_SAI_CR2_DIV_MASK | FSL_SAI_CR2_BYP,
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savediv / 2 - 1);
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return 0;
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}
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@ -972,10 +974,8 @@ static int fsl_sai_check_version(struct device *dev)
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dev_dbg(dev, "VERID: 0x%016X\n", val);
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sai->verid.major = (val & FSL_SAI_VERID_MAJOR_MASK) >>
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FSL_SAI_VERID_MAJOR_SHIFT;
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sai->verid.minor = (val & FSL_SAI_VERID_MINOR_MASK) >>
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FSL_SAI_VERID_MINOR_SHIFT;
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sai->verid.version = val &
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(FSL_SAI_VERID_MAJOR_MASK | FSL_SAI_VERID_MINOR_MASK);
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sai->verid.feature = val & FSL_SAI_VERID_FEATURE_MASK;
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ret = regmap_read(sai->regmap, FSL_SAI_PARAM, &val);
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@ -1147,7 +1147,7 @@ static int fsl_sai_probe(struct platform_device *pdev)
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/* Select MCLK direction */
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if (of_find_property(np, "fsl,sai-mclk-direction-output", NULL) &&
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sai->verid.major >= 3 && sai->verid.minor >= 1) {
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sai->verid.version >= 0x0301) {
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regmap_update_bits(sai->regmap, FSL_SAI_MCTL,
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FSL_SAI_MCTL_MCLK_EN, FSL_SAI_MCTL_MCLK_EN);
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}
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@ -201,9 +201,6 @@
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#define FSL_SAI_REC_SYN BIT(4)
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#define FSL_SAI_USE_I2S_SLAVE BIT(5)
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#define FSL_FMT_TRANSMITTER 0
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#define FSL_FMT_RECEIVER 1
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/* SAI clock sources */
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#define FSL_SAI_CLK_BUS 0
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#define FSL_SAI_CLK_MAST1 1
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@ -230,15 +227,13 @@ struct fsl_sai_soc_data {
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/**
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* struct fsl_sai_verid - version id data
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* @major: major version number
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* @minor: minor version number
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* @version: version number
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* @feature: feature specification number
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* 0000000000000000b - Standard feature set
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* 0000000000000000b - Standard feature set
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*/
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struct fsl_sai_verid {
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u32 major;
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u32 minor;
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u32 version;
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u32 feature;
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};
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