diff --git a/arch/arm/mach-mx1/Makefile b/arch/arm/mach-mx1/Makefile index 297d17210e11..fc2ddf82441b 100644 --- a/arch/arm/mach-mx1/Makefile +++ b/arch/arm/mach-mx1/Makefile @@ -4,6 +4,7 @@ # Object file lists. +EXTRA_CFLAGS += -DIMX_NEEDS_DEPRECATED_SYMBOLS obj-y += generic.o clock.o devices.o # Support for CMOS sensor interface diff --git a/arch/arm/mach-mx1/mach-mx1ads.c b/arch/arm/mach-mx1/mach-mx1ads.c index a39433afb512..69831aa274ff 100644 --- a/arch/arm/mach-mx1/mach-mx1ads.c +++ b/arch/arm/mach-mx1/mach-mx1ads.c @@ -147,7 +147,7 @@ MACHINE_START(MX1ADS, "Freescale MX1ADS") /* Maintainer: Sascha Hauer, Pengutronix */ .phys_io = IMX_IO_PHYS, .io_pg_offst = (IMX_IO_BASE >> 18) & 0xfffc, - .boot_params = PHYS_OFFSET + 0x100, + .boot_params = MX1_PHYS_OFFSET + 0x100, .map_io = mx1_map_io, .init_irq = mx1_init_irq, .timer = &mx1ads_timer, @@ -157,7 +157,7 @@ MACHINE_END MACHINE_START(MXLADS, "Freescale MXLADS") .phys_io = IMX_IO_PHYS, .io_pg_offst = (IMX_IO_BASE >> 18) & 0xfffc, - .boot_params = PHYS_OFFSET + 0x100, + .boot_params = MX1_PHYS_OFFSET + 0x100, .map_io = mx1_map_io, .init_irq = mx1_init_irq, .timer = &mx1ads_timer, diff --git a/arch/arm/mach-mx2/Makefile b/arch/arm/mach-mx2/Makefile index a9c94e39e321..e8910903b24f 100644 --- a/arch/arm/mach-mx2/Makefile +++ b/arch/arm/mach-mx2/Makefile @@ -7,7 +7,6 @@ obj-y := generic.o devices.o serial.o CFLAGS_generic.o = -DIMX_NEEDS_DEPRECATED_SYMBOLS CFLAGS_devices.o = -DIMX_NEEDS_DEPRECATED_SYMBOLS -CFLAGS_serial.o = -DIMX_NEEDS_DEPRECATED_SYMBOLS obj-$(CONFIG_MACH_MX21) += clock_imx21.o diff --git a/arch/arm/mach-mx2/mach-cpuimx27.c b/arch/arm/mach-mx2/mach-cpuimx27.c index 8e4f3d08e32c..92fd1bf7a638 100644 --- a/arch/arm/mach-mx2/mach-cpuimx27.c +++ b/arch/arm/mach-mx2/mach-cpuimx27.c @@ -226,7 +226,7 @@ static struct sys_timer eukrea_cpuimx27_timer = { MACHINE_START(CPUIMX27, "EUKREA CPUIMX27") .phys_io = MX27_AIPI_BASE_ADDR, .io_pg_offst = ((MX27_AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc, - .boot_params = PHYS_OFFSET + 0x100, + .boot_params = MX27_PHYS_OFFSET + 0x100, .map_io = mx27_map_io, .init_irq = mx27_init_irq, .init_machine = eukrea_cpuimx27_init, diff --git a/arch/arm/mach-mx2/mach-imx27lite.c b/arch/arm/mach-mx2/mach-imx27lite.c index ca6ab1265f3e..621c2c1046ea 100644 --- a/arch/arm/mach-mx2/mach-imx27lite.c +++ b/arch/arm/mach-mx2/mach-imx27lite.c @@ -87,7 +87,7 @@ static struct sys_timer mx27lite_timer = { MACHINE_START(IMX27LITE, "LogicPD i.MX27LITE") .phys_io = MX27_AIPI_BASE_ADDR, .io_pg_offst = ((MX27_AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc, - .boot_params = PHYS_OFFSET + 0x100, + .boot_params = MX27_PHYS_OFFSET + 0x100, .map_io = mx27_map_io, .init_irq = mx27_init_irq, .init_machine = mx27lite_init, diff --git a/arch/arm/mach-mx2/mach-mx21ads.c b/arch/arm/mach-mx2/mach-mx21ads.c index eb4a6e855595..d5eb8065df3e 100644 --- a/arch/arm/mach-mx2/mach-mx21ads.c +++ b/arch/arm/mach-mx2/mach-mx21ads.c @@ -286,7 +286,7 @@ MACHINE_START(MX21ADS, "Freescale i.MX21ADS") /* maintainer: Freescale Semiconductor, Inc. */ .phys_io = MX21_AIPI_BASE_ADDR, .io_pg_offst = ((MX21_AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc, - .boot_params = PHYS_OFFSET + 0x100, + .boot_params = MX21_PHYS_OFFSET + 0x100, .map_io = mx21ads_map_io, .init_irq = mx21_init_irq, .init_machine = mx21ads_board_init, diff --git a/arch/arm/mach-mx2/mach-mx27_3ds.c b/arch/arm/mach-mx2/mach-mx27_3ds.c index 595fea46b6f7..8c975f6514ad 100644 --- a/arch/arm/mach-mx2/mach-mx27_3ds.c +++ b/arch/arm/mach-mx2/mach-mx27_3ds.c @@ -87,7 +87,7 @@ MACHINE_START(MX27_3DS, "Freescale MX27PDK") /* maintainer: Freescale Semiconductor, Inc. */ .phys_io = MX27_AIPI_BASE_ADDR, .io_pg_offst = ((MX27_AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc, - .boot_params = PHYS_OFFSET + 0x100, + .boot_params = MX27_PHYS_OFFSET + 0x100, .map_io = mx27_map_io, .init_irq = mx27_init_irq, .init_machine = mx27pdk_init, diff --git a/arch/arm/mach-mx2/mach-mx27ads.c b/arch/arm/mach-mx2/mach-mx27ads.c index 385fc1c9ad38..808ca271a829 100644 --- a/arch/arm/mach-mx2/mach-mx27ads.c +++ b/arch/arm/mach-mx2/mach-mx27ads.c @@ -336,7 +336,7 @@ MACHINE_START(MX27ADS, "Freescale i.MX27ADS") /* maintainer: Freescale Semiconductor, Inc. */ .phys_io = MX27_AIPI_BASE_ADDR, .io_pg_offst = ((MX27_AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc, - .boot_params = PHYS_OFFSET + 0x100, + .boot_params = MX27_PHYS_OFFSET + 0x100, .map_io = mx27ads_map_io, .init_irq = mx27_init_irq, .init_machine = mx27ads_board_init, diff --git a/arch/arm/mach-mx2/mach-mxt_td60.c b/arch/arm/mach-mx2/mach-mxt_td60.c index 9ed4e492fc73..df954d879cc3 100644 --- a/arch/arm/mach-mx2/mach-mxt_td60.c +++ b/arch/arm/mach-mx2/mach-mxt_td60.c @@ -286,7 +286,7 @@ MACHINE_START(MXT_TD60, "Maxtrack i-MXT TD60") /* maintainer: Maxtrack Industrial */ .phys_io = MX27_AIPI_BASE_ADDR, .io_pg_offst = ((MX27_AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc, - .boot_params = PHYS_OFFSET + 0x100, + .boot_params = MX27_PHYS_OFFSET + 0x100, .map_io = mx27_map_io, .init_irq = mx27_init_irq, .init_machine = mxt_td60_board_init, diff --git a/arch/arm/mach-mx2/mach-pca100.c b/arch/arm/mach-mx2/mach-pca100.c index 55dbf5a64e00..9279b42b24b5 100644 --- a/arch/arm/mach-mx2/mach-pca100.c +++ b/arch/arm/mach-mx2/mach-pca100.c @@ -235,7 +235,7 @@ static struct sys_timer pca100_timer = { MACHINE_START(PCA100, "phyCARD-i.MX27") .phys_io = MX27_AIPI_BASE_ADDR, .io_pg_offst = ((MX27_AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc, - .boot_params = PHYS_OFFSET + 0x100, + .boot_params = MX27_PHYS_OFFSET + 0x100, .map_io = mx27_map_io, .init_irq = mx27_init_irq, .init_machine = pca100_init, diff --git a/arch/arm/mach-mx2/mach-pcm038.c b/arch/arm/mach-mx2/mach-pcm038.c index 9636bb82f1e9..e055d9dd6101 100644 --- a/arch/arm/mach-mx2/mach-pcm038.c +++ b/arch/arm/mach-mx2/mach-pcm038.c @@ -328,7 +328,7 @@ static struct sys_timer pcm038_timer = { MACHINE_START(PCM038, "phyCORE-i.MX27") .phys_io = MX27_AIPI_BASE_ADDR, .io_pg_offst = ((MX27_AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc, - .boot_params = PHYS_OFFSET + 0x100, + .boot_params = MX27_PHYS_OFFSET + 0x100, .map_io = mx27_map_io, .init_irq = mx27_init_irq, .init_machine = pcm038_init, diff --git a/arch/arm/mach-mx2/serial.c b/arch/arm/mach-mx2/serial.c index 40a485cdc10e..1c0c835b2252 100644 --- a/arch/arm/mach-mx2/serial.c +++ b/arch/arm/mach-mx2/serial.c @@ -26,12 +26,12 @@ static struct resource uart0[] = { { - .start = UART1_BASE_ADDR, - .end = UART1_BASE_ADDR + 0x0B5, + .start = MX2x_UART1_BASE_ADDR, + .end = MX2x_UART1_BASE_ADDR + 0x0B5, .flags = IORESOURCE_MEM, }, { - .start = MXC_INT_UART1, - .end = MXC_INT_UART1, + .start = MX2x_INT_UART1, + .end = MX2x_INT_UART1, .flags = IORESOURCE_IRQ, }, }; @@ -45,12 +45,12 @@ struct platform_device mxc_uart_device0 = { static struct resource uart1[] = { { - .start = UART2_BASE_ADDR, - .end = UART2_BASE_ADDR + 0x0B5, + .start = MX2x_UART2_BASE_ADDR, + .end = MX2x_UART2_BASE_ADDR + 0x0B5, .flags = IORESOURCE_MEM, }, { - .start = MXC_INT_UART2, - .end = MXC_INT_UART2, + .start = MX2x_INT_UART2, + .end = MX2x_INT_UART2, .flags = IORESOURCE_IRQ, }, }; @@ -64,12 +64,12 @@ struct platform_device mxc_uart_device1 = { static struct resource uart2[] = { { - .start = UART3_BASE_ADDR, - .end = UART3_BASE_ADDR + 0x0B5, + .start = MX2x_UART3_BASE_ADDR, + .end = MX2x_UART3_BASE_ADDR + 0x0B5, .flags = IORESOURCE_MEM, }, { - .start = MXC_INT_UART3, - .end = MXC_INT_UART3, + .start = MX2x_INT_UART3, + .end = MX2x_INT_UART3, .flags = IORESOURCE_IRQ, }, }; @@ -83,12 +83,12 @@ struct platform_device mxc_uart_device2 = { static struct resource uart3[] = { { - .start = UART4_BASE_ADDR, - .end = UART4_BASE_ADDR + 0x0B5, + .start = MX2x_UART4_BASE_ADDR, + .end = MX2x_UART4_BASE_ADDR + 0x0B5, .flags = IORESOURCE_MEM, }, { - .start = MXC_INT_UART4, - .end = MXC_INT_UART4, + .start = MX2x_INT_UART4, + .end = MX2x_INT_UART4, .flags = IORESOURCE_IRQ, }, }; @@ -103,12 +103,12 @@ struct platform_device mxc_uart_device3 = { #ifdef CONFIG_MACH_MX27 static struct resource uart4[] = { { - .start = UART5_BASE_ADDR, - .end = UART5_BASE_ADDR + 0x0B5, + .start = MX27_UART5_BASE_ADDR, + .end = MX27_UART5_BASE_ADDR + 0x0B5, .flags = IORESOURCE_MEM, }, { - .start = MXC_INT_UART5, - .end = MXC_INT_UART5, + .start = MX27_INT_UART5, + .end = MX27_INT_UART5, .flags = IORESOURCE_IRQ, }, }; @@ -122,12 +122,12 @@ struct platform_device mxc_uart_device4 = { static struct resource uart5[] = { { - .start = UART6_BASE_ADDR, - .end = UART6_BASE_ADDR + 0x0B5, + .start = MX27_UART6_BASE_ADDR, + .end = MX27_UART6_BASE_ADDR + 0x0B5, .flags = IORESOURCE_MEM, }, { - .start = MXC_INT_UART6, - .end = MXC_INT_UART6, + .start = MX27_INT_UART6, + .end = MX27_INT_UART6, .flags = IORESOURCE_IRQ, }, }; diff --git a/arch/arm/mach-mx25/Makefile b/arch/arm/mach-mx25/Makefile index fe23836a9f3d..10cebc5ced8c 100644 --- a/arch/arm/mach-mx25/Makefile +++ b/arch/arm/mach-mx25/Makefile @@ -1,3 +1,3 @@ obj-y := mm.o devices.o obj-$(CONFIG_ARCH_MX25) += clock.o -obj-$(CONFIG_MACH_MX25_3DS) += mx25pdk.o +obj-$(CONFIG_MACH_MX25_3DS) += mach-mx25pdk.o diff --git a/arch/arm/mach-mx25/mx25pdk.c b/arch/arm/mach-mx25/mach-mx25pdk.c similarity index 98% rename from arch/arm/mach-mx25/mx25pdk.c rename to arch/arm/mach-mx25/mach-mx25pdk.c index f4e8b984af72..10be38eb82a8 100644 --- a/arch/arm/mach-mx25/mx25pdk.c +++ b/arch/arm/mach-mx25/mach-mx25pdk.c @@ -110,7 +110,7 @@ MACHINE_START(MX25_3DS, "Freescale MX25PDK (3DS)") /* Maintainer: Freescale Semiconductor, Inc. */ .phys_io = MX25_AIPS1_BASE_ADDR, .io_pg_offst = ((MX25_AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc, - .boot_params = PHYS_OFFSET + 0x100, + .boot_params = MX25_PHYS_OFFSET + 0x100, .map_io = mx25_map_io, .init_irq = mx25_init_irq, .init_machine = mx25pdk_init, diff --git a/arch/arm/mach-mx3/mach-armadillo5x0.c b/arch/arm/mach-mx3/mach-armadillo5x0.c index 1fed146324f5..3d72b0b89705 100644 --- a/arch/arm/mach-mx3/mach-armadillo5x0.c +++ b/arch/arm/mach-mx3/mach-armadillo5x0.c @@ -408,7 +408,7 @@ MACHINE_START(ARMADILLO5X0, "Armadillo-500") /* Maintainer: Alberto Panizzo */ .phys_io = MX31_AIPS1_BASE_ADDR, .io_pg_offst = (MX31_AIPS1_BASE_ADDR_VIRT >> 18) & 0xfffc, - .boot_params = PHYS_OFFSET + 0x00000100, + .boot_params = MX3x_PHYS_OFFSET + 0x100, .map_io = mx31_map_io, .init_irq = mx31_init_irq, .timer = &armadillo5x0_timer, diff --git a/arch/arm/mach-mx3/mach-kzm_arm11_01.c b/arch/arm/mach-mx3/mach-kzm_arm11_01.c index 2484dddca549..f085d5d1a6de 100644 --- a/arch/arm/mach-mx3/mach-kzm_arm11_01.c +++ b/arch/arm/mach-mx3/mach-kzm_arm11_01.c @@ -265,7 +265,7 @@ static struct sys_timer kzm_timer = { MACHINE_START(KZM_ARM11_01, "Kyoto Microcomputer Co., Ltd. KZM-ARM11-01") .phys_io = MX31_AIPS1_BASE_ADDR, .io_pg_offst = (MX31_AIPS1_BASE_ADDR_VIRT >> 18) & 0xfffc, - .boot_params = PHYS_OFFSET + 0x100, + .boot_params = MX3x_PHYS_OFFSET + 0x100, .map_io = kzm_map_io, .init_irq = mx31_init_irq, .init_machine = kzm_board_init, diff --git a/arch/arm/mach-mx3/mach-mx31_3ds.c b/arch/arm/mach-mx3/mach-mx31_3ds.c index 88af58514a76..b88c18ad7698 100644 --- a/arch/arm/mach-mx3/mach-mx31_3ds.c +++ b/arch/arm/mach-mx3/mach-mx31_3ds.c @@ -258,7 +258,7 @@ MACHINE_START(MX31_3DS, "Freescale MX31PDK (3DS)") /* Maintainer: Freescale Semiconductor, Inc. */ .phys_io = MX31_AIPS1_BASE_ADDR, .io_pg_offst = (MX31_AIPS1_BASE_ADDR_VIRT >> 18) & 0xfffc, - .boot_params = PHYS_OFFSET + 0x100, + .boot_params = MX3x_PHYS_OFFSET + 0x100, .map_io = mx31pdk_map_io, .init_irq = mx31_init_irq, .init_machine = mxc_board_init, diff --git a/arch/arm/mach-mx3/mach-mx31ads.c b/arch/arm/mach-mx3/mach-mx31ads.c index 59de37887f33..2f02df212b66 100644 --- a/arch/arm/mach-mx3/mach-mx31ads.c +++ b/arch/arm/mach-mx3/mach-mx31ads.c @@ -537,7 +537,7 @@ MACHINE_START(MX31ADS, "Freescale MX31ADS") /* Maintainer: Freescale Semiconductor, Inc. */ .phys_io = MX31_AIPS1_BASE_ADDR, .io_pg_offst = (MX31_AIPS1_BASE_ADDR_VIRT >> 18) & 0xfffc, - .boot_params = PHYS_OFFSET + 0x100, + .boot_params = MX3x_PHYS_OFFSET + 0x100, .map_io = mx31ads_map_io, .init_irq = mx31ads_init_irq, .init_machine = mxc_board_init, diff --git a/arch/arm/mach-mx3/mach-mx31lilly.c b/arch/arm/mach-mx3/mach-mx31lilly.c index 9225cb72dd01..80847b04c063 100644 --- a/arch/arm/mach-mx3/mach-mx31lilly.c +++ b/arch/arm/mach-mx3/mach-mx31lilly.c @@ -197,7 +197,7 @@ static struct sys_timer mx31lilly_timer = { MACHINE_START(LILLY1131, "INCO startec LILLY-1131") .phys_io = MX31_AIPS1_BASE_ADDR, .io_pg_offst = (MX31_AIPS1_BASE_ADDR_VIRT >> 18) & 0xfffc, - .boot_params = PHYS_OFFSET + 0x100, + .boot_params = MX3x_PHYS_OFFSET + 0x100, .map_io = mx31_map_io, .init_irq = mx31_init_irq, .init_machine = mx31lilly_board_init, diff --git a/arch/arm/mach-mx3/mach-mx31lite.c b/arch/arm/mach-mx3/mach-mx31lite.c index 8589e3d1dada..2b6d11400877 100644 --- a/arch/arm/mach-mx3/mach-mx31lite.c +++ b/arch/arm/mach-mx3/mach-mx31lite.c @@ -289,7 +289,7 @@ MACHINE_START(MX31LITE, "LogicPD i.MX31 SOM") /* Maintainer: Freescale Semiconductor, Inc. */ .phys_io = MX31_AIPS1_BASE_ADDR, .io_pg_offst = (MX31_AIPS1_BASE_ADDR_VIRT >> 18) & 0xfffc, - .boot_params = PHYS_OFFSET + 0x100, + .boot_params = MX3x_PHYS_OFFSET + 0x100, .map_io = mx31lite_map_io, .init_irq = mx31_init_irq, .init_machine = mxc_board_init, diff --git a/arch/arm/mach-mx3/mach-mx31moboard.c b/arch/arm/mach-mx3/mach-mx31moboard.c index 63f991f8817f..fe18cd513cd7 100644 --- a/arch/arm/mach-mx3/mach-mx31moboard.c +++ b/arch/arm/mach-mx3/mach-mx31moboard.c @@ -571,7 +571,7 @@ MACHINE_START(MX31MOBOARD, "EPFL Mobots mx31moboard") /* Maintainer: Valentin Longchamp, EPFL Mobots group */ .phys_io = MX31_AIPS1_BASE_ADDR, .io_pg_offst = (MX31_AIPS1_BASE_ADDR_VIRT >> 18) & 0xfffc, - .boot_params = PHYS_OFFSET + 0x100, + .boot_params = MX3x_PHYS_OFFSET + 0x100, .map_io = mx31_map_io, .init_irq = mx31_init_irq, .init_machine = mxc_board_init, diff --git a/arch/arm/mach-mx3/mach-mx35pdk.c b/arch/arm/mach-mx3/mach-mx35pdk.c index 2d11bf053c78..bcac84d4dca4 100644 --- a/arch/arm/mach-mx3/mach-mx35pdk.c +++ b/arch/arm/mach-mx3/mach-mx35pdk.c @@ -108,7 +108,7 @@ MACHINE_START(MX35_3DS, "Freescale MX35PDK") /* Maintainer: Freescale Semiconductor, Inc */ .phys_io = MX35_AIPS1_BASE_ADDR, .io_pg_offst = ((MX35_AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc, - .boot_params = PHYS_OFFSET + 0x100, + .boot_params = MX3x_PHYS_OFFSET + 0x100, .map_io = mx35_map_io, .init_irq = mx35_init_irq, .init_machine = mxc_board_init, diff --git a/arch/arm/mach-mx3/mach-pcm037.c b/arch/arm/mach-mx3/mach-pcm037.c index d9bd7d2b0ade..21f54811a630 100644 --- a/arch/arm/mach-mx3/mach-pcm037.c +++ b/arch/arm/mach-mx3/mach-pcm037.c @@ -638,7 +638,7 @@ MACHINE_START(PCM037, "Phytec Phycore pcm037") /* Maintainer: Pengutronix */ .phys_io = MX31_AIPS1_BASE_ADDR, .io_pg_offst = (MX31_AIPS1_BASE_ADDR_VIRT >> 18) & 0xfffc, - .boot_params = PHYS_OFFSET + 0x100, + .boot_params = MX3x_PHYS_OFFSET + 0x100, .map_io = mx31_map_io, .init_irq = mx31_init_irq, .init_machine = mxc_board_init, diff --git a/arch/arm/mach-mx3/mach-pcm043.c b/arch/arm/mach-mx3/mach-pcm043.c index 1212194fb9c2..25942b8e8bed 100644 --- a/arch/arm/mach-mx3/mach-pcm043.c +++ b/arch/arm/mach-mx3/mach-pcm043.c @@ -250,7 +250,7 @@ MACHINE_START(PCM043, "Phytec Phycore pcm043") /* Maintainer: Pengutronix */ .phys_io = MX35_AIPS1_BASE_ADDR, .io_pg_offst = ((MX35_AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc, - .boot_params = PHYS_OFFSET + 0x100, + .boot_params = MX3x_PHYS_OFFSET + 0x100, .map_io = mx35_map_io, .init_irq = mx35_init_irq, .init_machine = mxc_board_init, diff --git a/arch/arm/mach-mx3/mach-qong.c b/arch/arm/mach-mx3/mach-qong.c index fdb819ae0e60..e5b5b8323a17 100644 --- a/arch/arm/mach-mx3/mach-qong.c +++ b/arch/arm/mach-mx3/mach-qong.c @@ -275,7 +275,7 @@ MACHINE_START(QONG, "Dave/DENX QongEVB-LITE") /* Maintainer: DENX Software Engineering GmbH */ .phys_io = MX31_AIPS1_BASE_ADDR, .io_pg_offst = (MX31_AIPS1_BASE_ADDR_VIRT >> 18) & 0xfffc, - .boot_params = PHYS_OFFSET + 0x100, + .boot_params = MX3x_PHYS_OFFSET + 0x100, .map_io = mx31_map_io, .init_irq = mx31_init_irq, .init_machine = mxc_board_init, diff --git a/arch/arm/mach-mxc91231/magx-zn5.c b/arch/arm/mach-mxc91231/magx-zn5.c index 7dbe4ca12efd..69816ba82930 100644 --- a/arch/arm/mach-mxc91231/magx-zn5.c +++ b/arch/arm/mach-mxc91231/magx-zn5.c @@ -55,7 +55,7 @@ struct sys_timer zn5_timer = { MACHINE_START(MAGX_ZN5, "Motorola Zn5") .phys_io = MXC91231_AIPS1_BASE_ADDR, .io_pg_offst = ((MXC91231_AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc, - .boot_params = PHYS_OFFSET + 0x100, + .boot_params = MXC91231_PHYS_OFFSET + 0x100, .map_io = mxc91231_map_io, .init_irq = mxc91231_init_irq, .timer = &zn5_timer, diff --git a/arch/arm/plat-mxc/clock.c b/arch/arm/plat-mxc/clock.c index 9e8fbd57495c..323ff8ccc877 100644 --- a/arch/arm/plat-mxc/clock.c +++ b/arch/arm/plat-mxc/clock.c @@ -56,6 +56,7 @@ static void __clk_disable(struct clk *clk) __clk_disable(clk->parent); __clk_disable(clk->secondary); + WARN_ON(!clk->usecount); if (!(--clk->usecount) && clk->disable) clk->disable(clk); } diff --git a/arch/arm/plat-mxc/include/mach/debug-macro.S b/arch/arm/plat-mxc/include/mach/debug-macro.S index 21e0f077268c..916d4fcb2ef2 100644 --- a/arch/arm/plat-mxc/include/mach/debug-macro.S +++ b/arch/arm/plat-mxc/include/mach/debug-macro.S @@ -51,7 +51,7 @@ #endif #include #define UART_PADDR MXC91231_UART2_BASE_ADDR -#define UART_VADDR MXC91231_AIPS1_IO_ADDRESS(MXC91231_UART2_BASE_ADDR) +#define UART_VADDR MXC91231_IO_ADDRESS(MXC91231_UART2_BASE_ADDR) #endif .macro addruart,rx mrc p15, 0, \rx, c1, c0 diff --git a/arch/arm/plat-mxc/include/mach/memory.h b/arch/arm/plat-mxc/include/mach/memory.h index d3afafdcc0e5..002eb91ab235 100644 --- a/arch/arm/plat-mxc/include/mach/memory.h +++ b/arch/arm/plat-mxc/include/mach/memory.h @@ -11,21 +11,27 @@ #ifndef __ASM_ARCH_MXC_MEMORY_H__ #define __ASM_ARCH_MXC_MEMORY_H__ -#if defined CONFIG_ARCH_MX1 -#define PHYS_OFFSET UL(0x08000000) -#elif defined CONFIG_ARCH_MX2 -#ifdef CONFIG_MACH_MX21 -#define PHYS_OFFSET UL(0xC0000000) -#endif -#ifdef CONFIG_MACH_MX27 -#define PHYS_OFFSET UL(0xA0000000) -#endif -#elif defined CONFIG_ARCH_MX3 -#define PHYS_OFFSET UL(0x80000000) -#elif defined CONFIG_ARCH_MX25 -#define PHYS_OFFSET UL(0x80000000) -#elif defined CONFIG_ARCH_MXC91231 -#define PHYS_OFFSET UL(0x90000000) +#define MX1_PHYS_OFFSET UL(0x08000000) +#define MX21_PHYS_OFFSET UL(0xc0000000) +#define MX25_PHYS_OFFSET UL(0x80000000) +#define MX27_PHYS_OFFSET UL(0xa0000000) +#define MX3x_PHYS_OFFSET UL(0x80000000) +#define MXC91231_PHYS_OFFSET UL(0x90000000) + +#if !defined(CONFIG_RUNTIME_PHYS_OFFSET) +# if defined CONFIG_ARCH_MX1 +# define PHYS_OFFSET MX1_PHYS_OFFSET +# elif defined CONFIG_MACH_MX21 +# define PHYS_OFFSET MX21_PHYS_OFFSET +# elif defined CONFIG_ARCH_MX25 +# define PHYS_OFFSET MX25_PHYS_OFFSET +# elif defined CONFIG_MACH_MX27 +# define PHYS_OFFSET MX27_PHYS_OFFSET +# elif defined CONFIG_ARCH_MX3 +# define PHYS_OFFSET MX3x_PHYS_OFFSET +# elif defined CONFIG_ARCH_MXC91231 +# define PHYS_OFFSET MXC91231_PHYS_OFFSET +# endif #endif #if defined(CONFIG_MX1_VIDEO) diff --git a/arch/arm/plat-mxc/include/mach/mx1.h b/arch/arm/plat-mxc/include/mach/mx1.h index b652a9c25865..5eba7e6785de 100644 --- a/arch/arm/plat-mxc/include/mach/mx1.h +++ b/arch/arm/plat-mxc/include/mach/mx1.h @@ -17,148 +17,281 @@ /* * Memory map */ -#define IMX_IO_PHYS 0x00200000 -#define IMX_IO_SIZE 0x00100000 -#define IMX_IO_BASE VMALLOC_END +#define MX1_IO_BASE_ADDR 0x00200000 +#define MX1_IO_SIZE SZ_1M +#define MX1_IO_BASE_ADDR_VIRT VMALLOC_END -#define IMX_CS0_PHYS 0x10000000 -#define IMX_CS0_SIZE 0x02000000 +#define MX1_CS0_PHYS 0x10000000 +#define MX1_CS0_SIZE 0x02000000 -#define IMX_CS1_PHYS 0x12000000 -#define IMX_CS1_SIZE 0x01000000 +#define MX1_CS1_PHYS 0x12000000 +#define MX1_CS1_SIZE 0x01000000 -#define IMX_CS2_PHYS 0x13000000 -#define IMX_CS2_SIZE 0x01000000 +#define MX1_CS2_PHYS 0x13000000 +#define MX1_CS2_SIZE 0x01000000 -#define IMX_CS3_PHYS 0x14000000 -#define IMX_CS3_SIZE 0x01000000 +#define MX1_CS3_PHYS 0x14000000 +#define MX1_CS3_SIZE 0x01000000 -#define IMX_CS4_PHYS 0x15000000 -#define IMX_CS4_SIZE 0x01000000 +#define MX1_CS4_PHYS 0x15000000 +#define MX1_CS4_SIZE 0x01000000 -#define IMX_CS5_PHYS 0x16000000 -#define IMX_CS5_SIZE 0x01000000 +#define MX1_CS5_PHYS 0x16000000 +#define MX1_CS5_SIZE 0x01000000 /* * Register BASEs, based on OFFSETs */ -#define AIPI1_BASE_ADDR (0x00000 + IMX_IO_PHYS) -#define WDT_BASE_ADDR (0x01000 + IMX_IO_PHYS) -#define TIM1_BASE_ADDR (0x02000 + IMX_IO_PHYS) -#define TIM2_BASE_ADDR (0x03000 + IMX_IO_PHYS) -#define RTC_BASE_ADDR (0x04000 + IMX_IO_PHYS) -#define LCDC_BASE_ADDR (0x05000 + IMX_IO_PHYS) -#define UART1_BASE_ADDR (0x06000 + IMX_IO_PHYS) -#define UART2_BASE_ADDR (0x07000 + IMX_IO_PHYS) -#define PWM_BASE_ADDR (0x08000 + IMX_IO_PHYS) -#define DMA_BASE_ADDR (0x09000 + IMX_IO_PHYS) -#define AIPI2_BASE_ADDR (0x10000 + IMX_IO_PHYS) -#define SIM_BASE_ADDR (0x11000 + IMX_IO_PHYS) -#define USBD_BASE_ADDR (0x12000 + IMX_IO_PHYS) -#define SPI1_BASE_ADDR (0x13000 + IMX_IO_PHYS) -#define MMC_BASE_ADDR (0x14000 + IMX_IO_PHYS) -#define ASP_BASE_ADDR (0x15000 + IMX_IO_PHYS) -#define BTA_BASE_ADDR (0x16000 + IMX_IO_PHYS) -#define I2C_BASE_ADDR (0x17000 + IMX_IO_PHYS) -#define SSI_BASE_ADDR (0x18000 + IMX_IO_PHYS) -#define SPI2_BASE_ADDR (0x19000 + IMX_IO_PHYS) -#define MSHC_BASE_ADDR (0x1A000 + IMX_IO_PHYS) -#define CCM_BASE_ADDR (0x1B000 + IMX_IO_PHYS) -#define SCM_BASE_ADDR (0x1B804 + IMX_IO_PHYS) -#define GPIO_BASE_ADDR (0x1C000 + IMX_IO_PHYS) -#define EIM_BASE_ADDR (0x20000 + IMX_IO_PHYS) -#define SDRAMC_BASE_ADDR (0x21000 + IMX_IO_PHYS) -#define MMA_BASE_ADDR (0x22000 + IMX_IO_PHYS) -#define AVIC_BASE_ADDR (0x23000 + IMX_IO_PHYS) -#define CSI_BASE_ADDR (0x24000 + IMX_IO_PHYS) +#define MX1_AIPI1_BASE_ADDR (0x00000 + MX1_IO_BASE_ADDR) +#define MX1_WDT_BASE_ADDR (0x01000 + MX1_IO_BASE_ADDR) +#define MX1_TIM1_BASE_ADDR (0x02000 + MX1_IO_BASE_ADDR) +#define MX1_TIM2_BASE_ADDR (0x03000 + MX1_IO_BASE_ADDR) +#define MX1_RTC_BASE_ADDR (0x04000 + MX1_IO_BASE_ADDR) +#define MX1_LCDC_BASE_ADDR (0x05000 + MX1_IO_BASE_ADDR) +#define MX1_UART1_BASE_ADDR (0x06000 + MX1_IO_BASE_ADDR) +#define MX1_UART2_BASE_ADDR (0x07000 + MX1_IO_BASE_ADDR) +#define MX1_PWM_BASE_ADDR (0x08000 + MX1_IO_BASE_ADDR) +#define MX1_DMA_BASE_ADDR (0x09000 + MX1_IO_BASE_ADDR) +#define MX1_AIPI2_BASE_ADDR (0x10000 + MX1_IO_BASE_ADDR) +#define MX1_SIM_BASE_ADDR (0x11000 + MX1_IO_BASE_ADDR) +#define MX1_USBD_BASE_ADDR (0x12000 + MX1_IO_BASE_ADDR) +#define MX1_SPI1_BASE_ADDR (0x13000 + MX1_IO_BASE_ADDR) +#define MX1_MMC_BASE_ADDR (0x14000 + MX1_IO_BASE_ADDR) +#define MX1_ASP_BASE_ADDR (0x15000 + MX1_IO_BASE_ADDR) +#define MX1_BTA_BASE_ADDR (0x16000 + MX1_IO_BASE_ADDR) +#define MX1_I2C_BASE_ADDR (0x17000 + MX1_IO_BASE_ADDR) +#define MX1_SSI_BASE_ADDR (0x18000 + MX1_IO_BASE_ADDR) +#define MX1_SPI2_BASE_ADDR (0x19000 + MX1_IO_BASE_ADDR) +#define MX1_MSHC_BASE_ADDR (0x1A000 + MX1_IO_BASE_ADDR) +#define MX1_CCM_BASE_ADDR (0x1B000 + MX1_IO_BASE_ADDR) +#define MX1_SCM_BASE_ADDR (0x1B804 + MX1_IO_BASE_ADDR) +#define MX1_GPIO_BASE_ADDR (0x1C000 + MX1_IO_BASE_ADDR) +#define MX1_EIM_BASE_ADDR (0x20000 + MX1_IO_BASE_ADDR) +#define MX1_SDRAMC_BASE_ADDR (0x21000 + MX1_IO_BASE_ADDR) +#define MX1_MMA_BASE_ADDR (0x22000 + MX1_IO_BASE_ADDR) +#define MX1_AVIC_BASE_ADDR (0x23000 + MX1_IO_BASE_ADDR) +#define MX1_CSI_BASE_ADDR (0x24000 + MX1_IO_BASE_ADDR) /* macro to get at IO space when running virtually */ -#define IO_ADDRESS(x) ((x) - IMX_IO_PHYS + IMX_IO_BASE) - -/* define macros needed for entry-macro.S */ -#define AVIC_IO_ADDRESS(x) IO_ADDRESS(x) +#define MX1_IO_ADDRESS(x) ( \ + IMX_IO_ADDRESS(x, MX1_IO)) /* fixed interrput numbers */ -#define INT_SOFTINT 0 -#define CSI_INT 6 -#define DSPA_MAC_INT 7 -#define DSPA_INT 8 -#define COMP_INT 9 -#define MSHC_XINT 10 -#define GPIO_INT_PORTA 11 -#define GPIO_INT_PORTB 12 -#define GPIO_INT_PORTC 13 -#define LCDC_INT 14 -#define SIM_INT 15 -#define SIM_DATA_INT 16 -#define RTC_INT 17 -#define RTC_SAMINT 18 -#define UART2_MINT_PFERR 19 -#define UART2_MINT_RTS 20 -#define UART2_MINT_DTR 21 -#define UART2_MINT_UARTC 22 -#define UART2_MINT_TX 23 -#define UART2_MINT_RX 24 -#define UART1_MINT_PFERR 25 -#define UART1_MINT_RTS 26 -#define UART1_MINT_DTR 27 -#define UART1_MINT_UARTC 28 -#define UART1_MINT_TX 29 -#define UART1_MINT_RX 30 -#define VOICE_DAC_INT 31 -#define VOICE_ADC_INT 32 -#define PEN_DATA_INT 33 -#define PWM_INT 34 -#define SDHC_INT 35 -#define I2C_INT 39 -#define CSPI_INT 41 -#define SSI_TX_INT 42 -#define SSI_TX_ERR_INT 43 -#define SSI_RX_INT 44 -#define SSI_RX_ERR_INT 45 -#define TOUCH_INT 46 -#define USBD_INT0 47 -#define USBD_INT1 48 -#define USBD_INT2 49 -#define USBD_INT3 50 -#define USBD_INT4 51 -#define USBD_INT5 52 -#define USBD_INT6 53 -#define BTSYS_INT 55 -#define BTTIM_INT 56 -#define BTWUI_INT 57 -#define TIM2_INT 58 -#define TIM1_INT 59 -#define DMA_ERR 60 -#define DMA_INT 61 -#define GPIO_INT_PORTD 62 -#define WDT_INT 63 +#define MX1_INT_SOFTINT 0 +#define MX1_CSI_INT 6 +#define MX1_DSPA_MAC_INT 7 +#define MX1_DSPA_INT 8 +#define MX1_COMP_INT 9 +#define MX1_MSHC_XINT 10 +#define MX1_GPIO_INT_PORTA 11 +#define MX1_GPIO_INT_PORTB 12 +#define MX1_GPIO_INT_PORTC 13 +#define MX1_LCDC_INT 14 +#define MX1_SIM_INT 15 +#define MX1_SIM_DATA_INT 16 +#define MX1_RTC_INT 17 +#define MX1_RTC_SAMINT 18 +#define MX1_UART2_MINT_PFERR 19 +#define MX1_UART2_MINT_RTS 20 +#define MX1_UART2_MINT_DTR 21 +#define MX1_UART2_MINT_UARTC 22 +#define MX1_UART2_MINT_TX 23 +#define MX1_UART2_MINT_RX 24 +#define MX1_UART1_MINT_PFERR 25 +#define MX1_UART1_MINT_RTS 26 +#define MX1_UART1_MINT_DTR 27 +#define MX1_UART1_MINT_UARTC 28 +#define MX1_UART1_MINT_TX 29 +#define MX1_UART1_MINT_RX 30 +#define MX1_VOICE_DAC_INT 31 +#define MX1_VOICE_ADC_INT 32 +#define MX1_PEN_DATA_INT 33 +#define MX1_PWM_INT 34 +#define MX1_SDHC_INT 35 +#define MX1_I2C_INT 39 +#define MX1_CSPI_INT 41 +#define MX1_SSI_TX_INT 42 +#define MX1_SSI_TX_ERR_INT 43 +#define MX1_SSI_RX_INT 44 +#define MX1_SSI_RX_ERR_INT 45 +#define MX1_TOUCH_INT 46 +#define MX1_USBD_INT0 47 +#define MX1_USBD_INT1 48 +#define MX1_USBD_INT2 49 +#define MX1_USBD_INT3 50 +#define MX1_USBD_INT4 51 +#define MX1_USBD_INT5 52 +#define MX1_USBD_INT6 53 +#define MX1_BTSYS_INT 55 +#define MX1_BTTIM_INT 56 +#define MX1_BTWUI_INT 57 +#define MX1_TIM2_INT 58 +#define MX1_TIM1_INT 59 +#define MX1_DMA_ERR 60 +#define MX1_DMA_INT 61 +#define MX1_GPIO_INT_PORTD 62 +#define MX1_WDT_INT 63 /* DMA */ -#define DMA_REQ_UART3_T 2 -#define DMA_REQ_UART3_R 3 -#define DMA_REQ_SSI2_T 4 -#define DMA_REQ_SSI2_R 5 -#define DMA_REQ_CSI_STAT 6 -#define DMA_REQ_CSI_R 7 -#define DMA_REQ_MSHC 8 -#define DMA_REQ_DSPA_DCT_DOUT 9 -#define DMA_REQ_DSPA_DCT_DIN 10 -#define DMA_REQ_DSPA_MAC 11 -#define DMA_REQ_EXT 12 -#define DMA_REQ_SDHC 13 -#define DMA_REQ_SPI1_R 14 -#define DMA_REQ_SPI1_T 15 -#define DMA_REQ_SSI_T 16 -#define DMA_REQ_SSI_R 17 -#define DMA_REQ_ASP_DAC 18 -#define DMA_REQ_ASP_ADC 19 -#define DMA_REQ_USP_EP(x) (20 + (x)) -#define DMA_REQ_SPI2_R 26 -#define DMA_REQ_SPI2_T 27 -#define DMA_REQ_UART2_T 28 -#define DMA_REQ_UART2_R 29 -#define DMA_REQ_UART1_T 30 -#define DMA_REQ_UART1_R 31 +#define MX1_DMA_REQ_UART3_T 2 +#define MX1_DMA_REQ_UART3_R 3 +#define MX1_DMA_REQ_SSI2_T 4 +#define MX1_DMA_REQ_SSI2_R 5 +#define MX1_DMA_REQ_CSI_STAT 6 +#define MX1_DMA_REQ_CSI_R 7 +#define MX1_DMA_REQ_MSHC 8 +#define MX1_DMA_REQ_DSPA_DCT_DOUT 9 +#define MX1_DMA_REQ_DSPA_DCT_DIN 10 +#define MX1_DMA_REQ_DSPA_MAC 11 +#define MX1_DMA_REQ_EXT 12 +#define MX1_DMA_REQ_SDHC 13 +#define MX1_DMA_REQ_SPI1_R 14 +#define MX1_DMA_REQ_SPI1_T 15 +#define MX1_DMA_REQ_SSI_T 16 +#define MX1_DMA_REQ_SSI_R 17 +#define MX1_DMA_REQ_ASP_DAC 18 +#define MX1_DMA_REQ_ASP_ADC 19 +#define MX1_DMA_REQ_USP_EP(x) (20 + (x)) +#define MX1_DMA_REQ_SPI2_R 26 +#define MX1_DMA_REQ_SPI2_T 27 +#define MX1_DMA_REQ_UART2_T 28 +#define MX1_DMA_REQ_UART2_R 29 +#define MX1_DMA_REQ_UART1_T 30 +#define MX1_DMA_REQ_UART1_R 31 + +/* + * This doesn't depend on IMX_NEEDS_DEPRECATED_SYMBOLS + * to not break drivers/usb/gadget/imx_udc. Should go + * away after this driver uses the new name. + */ +#define USBD_INT0 MX1_USBD_INT0 + +#ifdef IMX_NEEDS_DEPRECATED_SYMBOLS +/* these should go away */ +#define IMX_IO_PHYS MX1_IO_BASE_ADDR +#define IMX_IO_SIZE MX1_IO_SIZE +#define IMX_IO_BASE MX1_IO_BASE_ADDR_VIRT +#define IMX_CS0_PHYS MX1_CS0_PHYS +#define IMX_CS0_SIZE MX1_CS0_SIZE +#define IMX_CS1_PHYS MX1_CS1_PHYS +#define IMX_CS1_SIZE MX1_CS1_SIZE +#define IMX_CS2_PHYS MX1_CS2_PHYS +#define IMX_CS2_SIZE MX1_CS2_SIZE +#define IMX_CS3_PHYS MX1_CS3_PHYS +#define IMX_CS3_SIZE MX1_CS3_SIZE +#define IMX_CS4_PHYS MX1_CS4_PHYS +#define IMX_CS4_SIZE MX1_CS4_SIZE +#define IMX_CS5_PHYS MX1_CS5_PHYS +#define IMX_CS5_SIZE MX1_CS5_SIZE +#define AIPI1_BASE_ADDR MX1_AIPI1_BASE_ADDR +#define WDT_BASE_ADDR MX1_WDT_BASE_ADDR +#define TIM1_BASE_ADDR MX1_TIM1_BASE_ADDR +#define TIM2_BASE_ADDR MX1_TIM2_BASE_ADDR +#define RTC_BASE_ADDR MX1_RTC_BASE_ADDR +#define LCDC_BASE_ADDR MX1_LCDC_BASE_ADDR +#define UART1_BASE_ADDR MX1_UART1_BASE_ADDR +#define UART2_BASE_ADDR MX1_UART2_BASE_ADDR +#define PWM_BASE_ADDR MX1_PWM_BASE_ADDR +#define DMA_BASE_ADDR MX1_DMA_BASE_ADDR +#define AIPI2_BASE_ADDR MX1_AIPI2_BASE_ADDR +#define SIM_BASE_ADDR MX1_SIM_BASE_ADDR +#define USBD_BASE_ADDR MX1_USBD_BASE_ADDR +#define SPI1_BASE_ADDR MX1_SPI1_BASE_ADDR +#define MMC_BASE_ADDR MX1_MMC_BASE_ADDR +#define ASP_BASE_ADDR MX1_ASP_BASE_ADDR +#define BTA_BASE_ADDR MX1_BTA_BASE_ADDR +#define I2C_BASE_ADDR MX1_I2C_BASE_ADDR +#define SSI_BASE_ADDR MX1_SSI_BASE_ADDR +#define SPI2_BASE_ADDR MX1_SPI2_BASE_ADDR +#define MSHC_BASE_ADDR MX1_MSHC_BASE_ADDR +#define CCM_BASE_ADDR MX1_CCM_BASE_ADDR +#define SCM_BASE_ADDR MX1_SCM_BASE_ADDR +#define GPIO_BASE_ADDR MX1_GPIO_BASE_ADDR +#define EIM_BASE_ADDR MX1_EIM_BASE_ADDR +#define SDRAMC_BASE_ADDR MX1_SDRAMC_BASE_ADDR +#define MMA_BASE_ADDR MX1_MMA_BASE_ADDR +#define AVIC_BASE_ADDR MX1_AVIC_BASE_ADDR +#define CSI_BASE_ADDR MX1_CSI_BASE_ADDR +#define IO_ADDRESS(x) MX1_IO_ADDRESS(x) +#define AVIC_IO_ADDRESS(x) IO_ADDRESS(x) +#define INT_SOFTINT MX1_INT_SOFTINT +#define CSI_INT MX1_CSI_INT +#define DSPA_MAC_INT MX1_DSPA_MAC_INT +#define DSPA_INT MX1_DSPA_INT +#define COMP_INT MX1_COMP_INT +#define MSHC_XINT MX1_MSHC_XINT +#define GPIO_INT_PORTA MX1_GPIO_INT_PORTA +#define GPIO_INT_PORTB MX1_GPIO_INT_PORTB +#define GPIO_INT_PORTC MX1_GPIO_INT_PORTC +#define LCDC_INT MX1_LCDC_INT +#define SIM_INT MX1_SIM_INT +#define SIM_DATA_INT MX1_SIM_DATA_INT +#define RTC_INT MX1_RTC_INT +#define RTC_SAMINT MX1_RTC_SAMINT +#define UART2_MINT_PFERR MX1_UART2_MINT_PFERR +#define UART2_MINT_RTS MX1_UART2_MINT_RTS +#define UART2_MINT_DTR MX1_UART2_MINT_DTR +#define UART2_MINT_UARTC MX1_UART2_MINT_UARTC +#define UART2_MINT_TX MX1_UART2_MINT_TX +#define UART2_MINT_RX MX1_UART2_MINT_RX +#define UART1_MINT_PFERR MX1_UART1_MINT_PFERR +#define UART1_MINT_RTS MX1_UART1_MINT_RTS +#define UART1_MINT_DTR MX1_UART1_MINT_DTR +#define UART1_MINT_UARTC MX1_UART1_MINT_UARTC +#define UART1_MINT_TX MX1_UART1_MINT_TX +#define UART1_MINT_RX MX1_UART1_MINT_RX +#define VOICE_DAC_INT MX1_VOICE_DAC_INT +#define VOICE_ADC_INT MX1_VOICE_ADC_INT +#define PEN_DATA_INT MX1_PEN_DATA_INT +#define PWM_INT MX1_PWM_INT +#define SDHC_INT MX1_SDHC_INT +#define I2C_INT MX1_I2C_INT +#define CSPI_INT MX1_CSPI_INT +#define SSI_TX_INT MX1_SSI_TX_INT +#define SSI_TX_ERR_INT MX1_SSI_TX_ERR_INT +#define SSI_RX_INT MX1_SSI_RX_INT +#define SSI_RX_ERR_INT MX1_SSI_RX_ERR_INT +#define TOUCH_INT MX1_TOUCH_INT +#define USBD_INT1 MX1_USBD_INT1 +#define USBD_INT2 MX1_USBD_INT2 +#define USBD_INT3 MX1_USBD_INT3 +#define USBD_INT4 MX1_USBD_INT4 +#define USBD_INT5 MX1_USBD_INT5 +#define USBD_INT6 MX1_USBD_INT6 +#define BTSYS_INT MX1_BTSYS_INT +#define BTTIM_INT MX1_BTTIM_INT +#define BTWUI_INT MX1_BTWUI_INT +#define TIM2_INT MX1_TIM2_INT +#define TIM1_INT MX1_TIM1_INT +#define DMA_ERR MX1_DMA_ERR +#define DMA_INT MX1_DMA_INT +#define GPIO_INT_PORTD MX1_GPIO_INT_PORTD +#define WDT_INT MX1_WDT_INT +#define DMA_REQ_UART3_T MX1_DMA_REQ_UART3_T +#define DMA_REQ_UART3_R MX1_DMA_REQ_UART3_R +#define DMA_REQ_SSI2_T MX1_DMA_REQ_SSI2_T +#define DMA_REQ_SSI2_R MX1_DMA_REQ_SSI2_R +#define DMA_REQ_CSI_STAT MX1_DMA_REQ_CSI_STAT +#define DMA_REQ_CSI_R MX1_DMA_REQ_CSI_R +#define DMA_REQ_MSHC MX1_DMA_REQ_MSHC +#define DMA_REQ_DSPA_DCT_DOUT MX1_DMA_REQ_DSPA_DCT_DOUT +#define DMA_REQ_DSPA_DCT_DIN MX1_DMA_REQ_DSPA_DCT_DIN +#define DMA_REQ_DSPA_MAC MX1_DMA_REQ_DSPA_MAC +#define DMA_REQ_EXT MX1_DMA_REQ_EXT +#define DMA_REQ_SDHC MX1_DMA_REQ_SDHC +#define DMA_REQ_SPI1_R MX1_DMA_REQ_SPI1_R +#define DMA_REQ_SPI1_T MX1_DMA_REQ_SPI1_T +#define DMA_REQ_SSI_T MX1_DMA_REQ_SSI_T +#define DMA_REQ_SSI_R MX1_DMA_REQ_SSI_R +#define DMA_REQ_ASP_DAC MX1_DMA_REQ_ASP_DAC +#define DMA_REQ_ASP_ADC MX1_DMA_REQ_ASP_ADC +#define DMA_REQ_USP_EP(x) MX1_DMA_REQ_USP_EP(x) +#define DMA_REQ_SPI2_R MX1_DMA_REQ_SPI2_R +#define DMA_REQ_SPI2_T MX1_DMA_REQ_SPI2_T +#define DMA_REQ_UART2_T MX1_DMA_REQ_UART2_T +#define DMA_REQ_UART2_R MX1_DMA_REQ_UART2_R +#define DMA_REQ_UART1_T MX1_DMA_REQ_UART1_T +#define DMA_REQ_UART1_R MX1_DMA_REQ_UART1_R +#endif /* ifdef IMX_NEEDS_DEPRECATED_SYMBOLS */ #endif /* ifndef __MACH_MX1_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/mx25.h b/arch/arm/plat-mxc/include/mach/mx25.h index 61052a33979c..4ef9d5332b4a 100644 --- a/arch/arm/plat-mxc/include/mach/mx25.h +++ b/arch/arm/plat-mxc/include/mach/mx25.h @@ -27,8 +27,8 @@ IMX_IO_ADDRESS(x, MX25_AIPS2) ?: \ IMX_IO_ADDRESS(x, MX25_AVIC)) -#define UART1_BASE_ADDR 0x43f90000 -#define UART2_BASE_ADDR 0x43f94000 +#define MX25_UART1_BASE_ADDR 0x43f90000 +#define MX25_UART2_BASE_ADDR 0x43f94000 #define MX25_FEC_BASE_ADDR 0x50038000 #define MX25_NFC_BASE_ADDR 0xbb000000 @@ -38,4 +38,9 @@ #define MX25_INT_FEC 57 #define MX25_INT_NANDFC 33 +#if defined(IMX_NEEDS_DEPRECATED_SYMBOLS) +#define UART1_BASE_ADDR MX25_UART1_BASE_ADDR +#define UART2_BASE_ADDR MX25_UART2_BASE_ADDR +#endif + #endif /* ifndef __MACH_MX25_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/mxc91231.h b/arch/arm/plat-mxc/include/mach/mxc91231.h index 81484d1ef232..5182b986b785 100644 --- a/arch/arm/plat-mxc/include/mach/mxc91231.h +++ b/arch/arm/plat-mxc/include/mach/mxc91231.h @@ -184,60 +184,22 @@ #define MXC91231_CS4_BASE_ADDR 0xB4000000 #define MXC91231_CS5_BASE_ADDR 0xB6000000 -/* Is given address belongs to the specified memory region? */ -#define ADDRESS_IN_REGION(addr, start, size) \ - (((addr) >= (start)) && ((addr) < (start)+(size))) - -/* Is given address belongs to the specified named `module'? */ -#define MXC91231_IS_MODULE(addr, module) \ - ADDRESS_IN_REGION(addr, MXC91231_ ## module ## _BASE_ADDR, \ - MXC91231_ ## module ## _SIZE) /* * This macro defines the physical to virtual address mapping for all the * peripheral modules. It is used by passing in the physical address as x * and returning the virtual address. If the physical address is not mapped, - * it returns 0xDEADBEEF + * it returns 0. */ -#define MXC91231_IO_ADDRESS(x) \ - (void __iomem *) \ - (MXC91231_IS_MODULE(x, L2CC) ? MXC91231_L2CC_IO_ADDRESS(x) : \ - MXC91231_IS_MODULE(x, AIPS1) ? MXC91231_AIPS1_IO_ADDRESS(x) : \ - MXC91231_IS_MODULE(x, AIPS2) ? MXC91231_AIPS2_IO_ADDRESS(x) : \ - MXC91231_IS_MODULE(x, SPBA0) ? MXC91231_SPBA0_IO_ADDRESS(x) : \ - MXC91231_IS_MODULE(x, SPBA1) ? MXC91231_SPBA1_IO_ADDRESS(x) : \ - MXC91231_IS_MODULE(x, ROMP) ? MXC91231_ROMP_IO_ADDRESS(x) : \ - MXC91231_IS_MODULE(x, AVIC) ? MXC91231_AVIC_IO_ADDRESS(x) : \ - MXC91231_IS_MODULE(x, X_MEMC) ? MXC91231_X_MEMC_IO_ADDRESS(x) : \ - 0xDEADBEEF) - - -/* - * define the address mapping macros: in physical address order - */ -#define MXC91231_L2CC_IO_ADDRESS(x) \ - (((x) - MXC91231_L2CC_BASE_ADDR) + MXC91231_L2CC_BASE_ADDR_VIRT) - -#define MXC91231_AIPS1_IO_ADDRESS(x) \ - (((x) - MXC91231_AIPS1_BASE_ADDR) + MXC91231_AIPS1_BASE_ADDR_VIRT) - -#define MXC91231_SPBA0_IO_ADDRESS(x) \ - (((x) - MXC91231_SPBA0_BASE_ADDR) + MXC91231_SPBA0_BASE_ADDR_VIRT) - -#define MXC91231_SPBA1_IO_ADDRESS(x) \ - (((x) - MXC91231_SPBA1_BASE_ADDR) + MXC91231_SPBA1_BASE_ADDR_VIRT) - -#define MXC91231_AIPS2_IO_ADDRESS(x) \ - (((x) - MXC91231_AIPS2_BASE_ADDR) + MXC91231_AIPS2_BASE_ADDR_VIRT) - -#define MXC91231_ROMP_IO_ADDRESS(x) \ - (((x) - MXC91231_ROMP_BASE_ADDR) + MXC91231_ROMP_BASE_ADDR_VIRT) - -#define MXC91231_AVIC_IO_ADDRESS(x) \ - (((x) - MXC91231_AVIC_BASE_ADDR) + MXC91231_AVIC_BASE_ADDR_VIRT) - -#define MXC91231_X_MEMC_IO_ADDRESS(x) \ - (((x) - MXC91231_X_MEMC_BASE_ADDR) + MXC91231_X_MEMC_BASE_ADDR_VIRT) +#define MXC91231_IO_ADDRESS(x) ( \ + IMX_IO_ADDRESS(x, MXC91231_L2CC) ?: \ + IMX_IO_ADDRESS(x, MXC91231_X_MEMC) ?: \ + IMX_IO_ADDRESS(x, MXC91231_ROMP) ?: \ + IMX_IO_ADDRESS(x, MXC91231_AVIC) ?: \ + IMX_IO_ADDRESS(x, MXC91231_AIPS1) ?: \ + IMX_IO_ADDRESS(x, MXC91231_SPBA0) ?: \ + IMX_IO_ADDRESS(x, MXC91231_SPBA1) ?: \ + IMX_IO_ADDRESS(x, MXC91231_AIPS2)) /* * Interrupt numbers