net: atlantic: MACSec ingress offload implementation
This patch adds support for MACSec ingress HW offloading on Atlantic network cards. Signed-off-by: Mark Starovoytov <mstarovoitov@marvell.com> Signed-off-by: Igor Russkikh <irusskikh@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Mark Starovoytov
David S. Miller
Родитель
b8f8a0b7b5
Коммит
9ff40a751a
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@ -25,6 +25,10 @@ static int aq_clear_txsc(struct aq_nic_s *nic, const int txsc_idx,
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enum aq_clear_type clear_type);
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static int aq_clear_txsa(struct aq_nic_s *nic, struct aq_macsec_txsc *aq_txsc,
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const int sa_num, enum aq_clear_type clear_type);
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static int aq_clear_rxsc(struct aq_nic_s *nic, const int rxsc_idx,
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enum aq_clear_type clear_type);
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static int aq_clear_rxsa(struct aq_nic_s *nic, struct aq_macsec_rxsc *aq_rxsc,
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const int sa_num, enum aq_clear_type clear_type);
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static int aq_clear_secy(struct aq_nic_s *nic, const struct macsec_secy *secy,
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enum aq_clear_type clear_type);
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static int aq_apply_macsec_cfg(struct aq_nic_s *nic);
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@ -57,6 +61,22 @@ static int aq_get_txsc_idx_from_secy(struct aq_macsec_cfg *macsec_cfg,
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return -1;
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}
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static int aq_get_rxsc_idx_from_rxsc(struct aq_macsec_cfg *macsec_cfg,
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const struct macsec_rx_sc *rxsc)
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{
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int i;
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if (unlikely(!rxsc))
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return -1;
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for (i = 0; i < AQ_MACSEC_MAX_SC; i++) {
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if (macsec_cfg->aq_rxsc[i].sw_rxsc == rxsc)
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return i;
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}
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return -1;
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}
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static int aq_get_txsc_idx_from_sc_idx(const enum aq_macsec_sc_sa sc_sa,
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const int sc_idx)
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{
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@ -506,34 +526,351 @@ static int aq_mdo_del_txsa(struct macsec_context *ctx)
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return ret;
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}
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static int aq_rxsc_validate_frames(const enum macsec_validation_type validate)
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{
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switch (validate) {
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case MACSEC_VALIDATE_DISABLED:
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return 2;
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case MACSEC_VALIDATE_CHECK:
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return 1;
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case MACSEC_VALIDATE_STRICT:
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return 0;
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default:
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WARN_ONCE(true, "Invalid validation type");
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}
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return 0;
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}
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static int aq_set_rxsc(struct aq_nic_s *nic, const u32 rxsc_idx)
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{
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const struct aq_macsec_rxsc *aq_rxsc =
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&nic->macsec_cfg->aq_rxsc[rxsc_idx];
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struct aq_mss_ingress_preclass_record pre_class_record;
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const struct macsec_rx_sc *rx_sc = aq_rxsc->sw_rxsc;
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const struct macsec_secy *secy = aq_rxsc->sw_secy;
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const u32 hw_sc_idx = aq_rxsc->hw_sc_idx;
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struct aq_mss_ingress_sc_record sc_record;
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struct aq_hw_s *hw = nic->aq_hw;
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int ret = 0;
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memset(&pre_class_record, 0, sizeof(pre_class_record));
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put_unaligned_be64((__force u64)rx_sc->sci, pre_class_record.sci);
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pre_class_record.sci_mask = 0xff;
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/* match all MACSEC ethertype packets */
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pre_class_record.eth_type = ETH_P_MACSEC;
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pre_class_record.eth_type_mask = 0x3;
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aq_ether_addr_to_mac(pre_class_record.mac_sa, (char *)&rx_sc->sci);
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pre_class_record.sa_mask = 0x3f;
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pre_class_record.an_mask = nic->macsec_cfg->sc_sa;
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pre_class_record.sc_idx = hw_sc_idx;
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/* strip SecTAG & forward for decryption */
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pre_class_record.action = 0x0;
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pre_class_record.valid = 1;
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ret = aq_mss_set_ingress_preclass_record(hw, &pre_class_record,
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2 * rxsc_idx + 1);
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if (ret)
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return ret;
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/* If SCI is absent, then match by SA alone */
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pre_class_record.sci_mask = 0;
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pre_class_record.sci_from_table = 1;
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ret = aq_mss_set_ingress_preclass_record(hw, &pre_class_record,
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2 * rxsc_idx);
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if (ret)
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return ret;
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memset(&sc_record, 0, sizeof(sc_record));
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sc_record.validate_frames =
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aq_rxsc_validate_frames(secy->validate_frames);
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if (secy->replay_protect) {
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sc_record.replay_protect = 1;
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sc_record.anti_replay_window = secy->replay_window;
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}
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sc_record.valid = 1;
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sc_record.fresh = 1;
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ret = aq_mss_set_ingress_sc_record(hw, &sc_record, hw_sc_idx);
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if (ret)
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return ret;
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return ret;
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}
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static int aq_mdo_add_rxsc(struct macsec_context *ctx)
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{
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return -EOPNOTSUPP;
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struct aq_nic_s *nic = netdev_priv(ctx->netdev);
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struct aq_macsec_cfg *cfg = nic->macsec_cfg;
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const u32 rxsc_idx_max = aq_sc_idx_max(cfg->sc_sa);
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u32 rxsc_idx;
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int ret = 0;
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if (hweight32(cfg->rxsc_idx_busy) >= rxsc_idx_max)
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return -ENOSPC;
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rxsc_idx = ffz(cfg->rxsc_idx_busy);
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if (rxsc_idx >= rxsc_idx_max)
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return -ENOSPC;
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if (ctx->prepare)
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return 0;
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cfg->aq_rxsc[rxsc_idx].hw_sc_idx = aq_to_hw_sc_idx(rxsc_idx,
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cfg->sc_sa);
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cfg->aq_rxsc[rxsc_idx].sw_secy = ctx->secy;
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cfg->aq_rxsc[rxsc_idx].sw_rxsc = ctx->rx_sc;
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if (netif_carrier_ok(nic->ndev) && netif_running(ctx->secy->netdev))
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ret = aq_set_rxsc(nic, rxsc_idx);
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if (ret < 0)
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return ret;
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set_bit(rxsc_idx, &cfg->rxsc_idx_busy);
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return 0;
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}
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static int aq_mdo_upd_rxsc(struct macsec_context *ctx)
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{
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return -EOPNOTSUPP;
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struct aq_nic_s *nic = netdev_priv(ctx->netdev);
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int rxsc_idx;
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int ret = 0;
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rxsc_idx = aq_get_rxsc_idx_from_rxsc(nic->macsec_cfg, ctx->rx_sc);
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if (rxsc_idx < 0)
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return -ENOENT;
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if (ctx->prepare)
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return 0;
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if (netif_carrier_ok(nic->ndev) && netif_running(ctx->secy->netdev))
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ret = aq_set_rxsc(nic, rxsc_idx);
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return ret;
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}
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static int aq_clear_rxsc(struct aq_nic_s *nic, const int rxsc_idx,
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enum aq_clear_type clear_type)
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{
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struct aq_macsec_rxsc *rx_sc = &nic->macsec_cfg->aq_rxsc[rxsc_idx];
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struct aq_hw_s *hw = nic->aq_hw;
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int ret = 0;
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int sa_num;
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for_each_set_bit (sa_num, &rx_sc->rx_sa_idx_busy, AQ_MACSEC_MAX_SA) {
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ret = aq_clear_rxsa(nic, rx_sc, sa_num, clear_type);
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if (ret)
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return ret;
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}
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if (clear_type & AQ_CLEAR_HW) {
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struct aq_mss_ingress_preclass_record pre_class_record;
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struct aq_mss_ingress_sc_record sc_record;
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memset(&pre_class_record, 0, sizeof(pre_class_record));
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memset(&sc_record, 0, sizeof(sc_record));
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ret = aq_mss_set_ingress_preclass_record(hw, &pre_class_record,
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2 * rxsc_idx);
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if (ret)
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return ret;
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ret = aq_mss_set_ingress_preclass_record(hw, &pre_class_record,
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2 * rxsc_idx + 1);
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if (ret)
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return ret;
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sc_record.fresh = 1;
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ret = aq_mss_set_ingress_sc_record(hw, &sc_record,
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rx_sc->hw_sc_idx);
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if (ret)
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return ret;
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}
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if (clear_type & AQ_CLEAR_SW) {
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clear_bit(rxsc_idx, &nic->macsec_cfg->rxsc_idx_busy);
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rx_sc->sw_secy = NULL;
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rx_sc->sw_rxsc = NULL;
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}
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return ret;
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}
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static int aq_mdo_del_rxsc(struct macsec_context *ctx)
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{
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return -EOPNOTSUPP;
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struct aq_nic_s *nic = netdev_priv(ctx->netdev);
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enum aq_clear_type clear_type = AQ_CLEAR_SW;
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int rxsc_idx;
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int ret = 0;
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rxsc_idx = aq_get_rxsc_idx_from_rxsc(nic->macsec_cfg, ctx->rx_sc);
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if (rxsc_idx < 0)
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return -ENOENT;
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if (ctx->prepare)
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return 0;
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if (netif_carrier_ok(nic->ndev))
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clear_type = AQ_CLEAR_ALL;
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ret = aq_clear_rxsc(nic, rxsc_idx, clear_type);
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return ret;
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}
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static int aq_update_rxsa(struct aq_nic_s *nic, const unsigned int sc_idx,
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const struct macsec_secy *secy,
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const struct macsec_rx_sa *rx_sa,
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const unsigned char *key, const unsigned char an)
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{
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struct aq_mss_ingress_sakey_record sa_key_record;
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struct aq_mss_ingress_sa_record sa_record;
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struct aq_hw_s *hw = nic->aq_hw;
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const int sa_idx = sc_idx | an;
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int ret = 0;
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memset(&sa_record, 0, sizeof(sa_record));
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sa_record.valid = rx_sa->active;
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sa_record.fresh = 1;
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sa_record.next_pn = rx_sa->next_pn;
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ret = aq_mss_set_ingress_sa_record(hw, &sa_record, sa_idx);
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if (ret)
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return ret;
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if (!key)
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return ret;
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memset(&sa_key_record, 0, sizeof(sa_key_record));
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memcpy(&sa_key_record.key, key, secy->key_len);
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switch (secy->key_len) {
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case AQ_MACSEC_KEY_LEN_128_BIT:
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sa_key_record.key_len = 0;
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break;
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case AQ_MACSEC_KEY_LEN_192_BIT:
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sa_key_record.key_len = 1;
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break;
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case AQ_MACSEC_KEY_LEN_256_BIT:
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sa_key_record.key_len = 2;
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break;
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default:
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return -1;
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}
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aq_rotate_keys(&sa_key_record.key, secy->key_len);
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ret = aq_mss_set_ingress_sakey_record(hw, &sa_key_record, sa_idx);
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return ret;
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}
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static int aq_mdo_add_rxsa(struct macsec_context *ctx)
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{
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return -EOPNOTSUPP;
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const struct macsec_rx_sc *rx_sc = ctx->sa.rx_sa->sc;
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struct aq_nic_s *nic = netdev_priv(ctx->netdev);
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const struct macsec_secy *secy = ctx->secy;
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struct aq_macsec_rxsc *aq_rxsc;
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int rxsc_idx;
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int ret = 0;
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rxsc_idx = aq_get_rxsc_idx_from_rxsc(nic->macsec_cfg, rx_sc);
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if (rxsc_idx < 0)
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return -EINVAL;
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if (ctx->prepare)
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return 0;
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aq_rxsc = &nic->macsec_cfg->aq_rxsc[rxsc_idx];
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set_bit(ctx->sa.assoc_num, &aq_rxsc->rx_sa_idx_busy);
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memcpy(aq_rxsc->rx_sa_key[ctx->sa.assoc_num], ctx->sa.key,
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secy->key_len);
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if (netif_carrier_ok(nic->ndev) && netif_running(secy->netdev))
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ret = aq_update_rxsa(nic, aq_rxsc->hw_sc_idx, secy,
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ctx->sa.rx_sa, ctx->sa.key,
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ctx->sa.assoc_num);
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return ret;
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}
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static int aq_mdo_upd_rxsa(struct macsec_context *ctx)
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{
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return -EOPNOTSUPP;
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const struct macsec_rx_sc *rx_sc = ctx->sa.rx_sa->sc;
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struct aq_nic_s *nic = netdev_priv(ctx->netdev);
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struct aq_macsec_cfg *cfg = nic->macsec_cfg;
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const struct macsec_secy *secy = ctx->secy;
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int rxsc_idx;
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int ret = 0;
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rxsc_idx = aq_get_rxsc_idx_from_rxsc(cfg, rx_sc);
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if (rxsc_idx < 0)
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return -EINVAL;
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if (ctx->prepare)
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return 0;
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if (netif_carrier_ok(nic->ndev) && netif_running(secy->netdev))
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ret = aq_update_rxsa(nic, cfg->aq_rxsc[rxsc_idx].hw_sc_idx,
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secy, ctx->sa.rx_sa, NULL,
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ctx->sa.assoc_num);
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return ret;
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}
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static int aq_clear_rxsa(struct aq_nic_s *nic, struct aq_macsec_rxsc *aq_rxsc,
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const int sa_num, enum aq_clear_type clear_type)
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{
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int sa_idx = aq_rxsc->hw_sc_idx | sa_num;
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struct aq_hw_s *hw = nic->aq_hw;
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int ret = 0;
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if (clear_type & AQ_CLEAR_SW)
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clear_bit(sa_num, &aq_rxsc->rx_sa_idx_busy);
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if ((clear_type & AQ_CLEAR_HW) && netif_carrier_ok(nic->ndev)) {
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struct aq_mss_ingress_sakey_record sa_key_record;
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struct aq_mss_ingress_sa_record sa_record;
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memset(&sa_key_record, 0, sizeof(sa_key_record));
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memset(&sa_record, 0, sizeof(sa_record));
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sa_record.fresh = 1;
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ret = aq_mss_set_ingress_sa_record(hw, &sa_record, sa_idx);
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if (ret)
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return ret;
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return aq_mss_set_ingress_sakey_record(hw, &sa_key_record,
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sa_idx);
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}
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return ret;
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}
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static int aq_mdo_del_rxsa(struct macsec_context *ctx)
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{
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return -EOPNOTSUPP;
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const struct macsec_rx_sc *rx_sc = ctx->sa.rx_sa->sc;
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struct aq_nic_s *nic = netdev_priv(ctx->netdev);
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struct aq_macsec_cfg *cfg = nic->macsec_cfg;
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int rxsc_idx;
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int ret = 0;
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rxsc_idx = aq_get_rxsc_idx_from_rxsc(cfg, rx_sc);
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if (rxsc_idx < 0)
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return -EINVAL;
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if (ctx->prepare)
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return 0;
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ret = aq_clear_rxsa(nic, &cfg->aq_rxsc[rxsc_idx], ctx->sa.assoc_num,
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AQ_CLEAR_ALL);
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return ret;
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}
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static int apply_txsc_cfg(struct aq_nic_s *nic, const int txsc_idx)
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@ -564,10 +901,40 @@ static int apply_txsc_cfg(struct aq_nic_s *nic, const int txsc_idx)
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return ret;
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}
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static int apply_rxsc_cfg(struct aq_nic_s *nic, const int rxsc_idx)
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{
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struct aq_macsec_rxsc *aq_rxsc = &nic->macsec_cfg->aq_rxsc[rxsc_idx];
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const struct macsec_secy *secy = aq_rxsc->sw_secy;
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struct macsec_rx_sa *rx_sa;
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int ret = 0;
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int i;
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if (!netif_running(secy->netdev))
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return ret;
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ret = aq_set_rxsc(nic, rxsc_idx);
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if (ret)
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return ret;
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for (i = 0; i < MACSEC_NUM_AN; i++) {
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rx_sa = rcu_dereference_bh(aq_rxsc->sw_rxsc->sa[i]);
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if (rx_sa) {
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ret = aq_update_rxsa(nic, aq_rxsc->hw_sc_idx, secy,
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rx_sa, aq_rxsc->rx_sa_key[i], i);
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if (ret)
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return ret;
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}
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}
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return ret;
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}
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static int aq_clear_secy(struct aq_nic_s *nic, const struct macsec_secy *secy,
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enum aq_clear_type clear_type)
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{
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struct macsec_rx_sc *rx_sc;
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int txsc_idx;
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int rxsc_idx;
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int ret = 0;
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||||
|
||||
txsc_idx = aq_get_txsc_idx_from_secy(nic->macsec_cfg, secy);
|
||||
|
|
@ -577,19 +944,43 @@ static int aq_clear_secy(struct aq_nic_s *nic, const struct macsec_secy *secy,
|
|||
return ret;
|
||||
}
|
||||
|
||||
for (rx_sc = rcu_dereference_bh(secy->rx_sc); rx_sc;
|
||||
rx_sc = rcu_dereference_bh(rx_sc->next)) {
|
||||
rxsc_idx = aq_get_rxsc_idx_from_rxsc(nic->macsec_cfg, rx_sc);
|
||||
if (rxsc_idx < 0)
|
||||
continue;
|
||||
|
||||
ret = aq_clear_rxsc(nic, rxsc_idx, clear_type);
|
||||
if (ret)
|
||||
return ret;
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int aq_apply_secy_cfg(struct aq_nic_s *nic,
|
||||
const struct macsec_secy *secy)
|
||||
{
|
||||
struct macsec_rx_sc *rx_sc;
|
||||
int txsc_idx;
|
||||
int rxsc_idx;
|
||||
int ret = 0;
|
||||
|
||||
txsc_idx = aq_get_txsc_idx_from_secy(nic->macsec_cfg, secy);
|
||||
if (txsc_idx >= 0)
|
||||
apply_txsc_cfg(nic, txsc_idx);
|
||||
|
||||
for (rx_sc = rcu_dereference_bh(secy->rx_sc); rx_sc && rx_sc->active;
|
||||
rx_sc = rcu_dereference_bh(rx_sc->next)) {
|
||||
rxsc_idx = aq_get_rxsc_idx_from_rxsc(nic->macsec_cfg, rx_sc);
|
||||
if (unlikely(rxsc_idx < 0))
|
||||
continue;
|
||||
|
||||
ret = apply_rxsc_cfg(nic, rxsc_idx);
|
||||
if (ret)
|
||||
return ret;
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
|
|
@ -606,6 +997,14 @@ static int aq_apply_macsec_cfg(struct aq_nic_s *nic)
|
|||
}
|
||||
}
|
||||
|
||||
for (i = 0; i < AQ_MACSEC_MAX_SC; i++) {
|
||||
if (nic->macsec_cfg->rxsc_idx_busy & BIT(i)) {
|
||||
ret = apply_rxsc_cfg(nic, i);
|
||||
if (ret)
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
|
|
@ -781,6 +1180,7 @@ int aq_macsec_enable(struct aq_nic_s *nic)
|
|||
|
||||
/* Init Ethertype bypass filters */
|
||||
for (index = 0; index < ARRAY_SIZE(ctl_ether_types); index++) {
|
||||
struct aq_mss_ingress_prectlf_record rx_prectlf_rec;
|
||||
struct aq_mss_egress_ctlf_record tx_ctlf_rec;
|
||||
|
||||
if (ctl_ether_types[index] == 0)
|
||||
|
|
@ -794,6 +1194,15 @@ int aq_macsec_enable(struct aq_nic_s *nic)
|
|||
tbl_idx = NUMROWS_EGRESSCTLFRECORD - num_ctl_ether_types - 1;
|
||||
aq_mss_set_egress_ctlf_record(hw, &tx_ctlf_rec, tbl_idx);
|
||||
|
||||
memset(&rx_prectlf_rec, 0, sizeof(rx_prectlf_rec));
|
||||
rx_prectlf_rec.eth_type = ctl_ether_types[index];
|
||||
rx_prectlf_rec.match_type = 4; /* Match eth_type only */
|
||||
rx_prectlf_rec.match_mask = 0xf; /* match for eth_type */
|
||||
rx_prectlf_rec.action = 0; /* Bypass MACSEC modules */
|
||||
tbl_idx =
|
||||
NUMROWS_INGRESSPRECTLFRECORD - num_ctl_ether_types - 1;
|
||||
aq_mss_set_ingress_prectlf_record(hw, &rx_prectlf_rec, tbl_idx);
|
||||
|
||||
num_ctl_ether_types++;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -31,6 +31,11 @@ struct aq_macsec_txsc {
|
|||
};
|
||||
|
||||
struct aq_macsec_rxsc {
|
||||
u32 hw_sc_idx;
|
||||
unsigned long rx_sa_idx_busy;
|
||||
const struct macsec_secy *sw_secy;
|
||||
const struct macsec_rx_sc *sw_rxsc;
|
||||
u8 rx_sa_key[MACSEC_NUM_AN][MACSEC_KEYID_LEN];
|
||||
};
|
||||
|
||||
struct aq_macsec_cfg {
|
||||
|
|
|
|||
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