mxc: TrustZone interrupt controller (TZIC) for Freescale i.MX5 family
Freescale i.MX51 processor uses a new interrupt controller. Add driver for TrustZone Interrupt Controller Signed-off-by: Amit Kucheria <amit.kucheria@canonical.com>
This commit is contained in:
Amit Kucheria
Родитель
cb2dc111b1
Коммит
a003708ad4
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@ -62,6 +62,14 @@ config MXC_IRQ_PRIOR
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requirements for timing.
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Say N here, unless you have a specialized requirement.
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config MXC_TZIC
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bool "Enable TrustZone Interrupt Controller"
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depends on ARCH_MX51
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help
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This will be automatically selected for all processors
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containing this interrupt controller.
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Say N here only if you are really sure.
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config MXC_PWM
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tristate "Enable PWM driver"
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depends on ARCH_MXC
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@ -5,6 +5,9 @@
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# Common support
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obj-y := irq.o clock.o gpio.o time.o devices.o cpu.o system.o
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# MX51 uses the TZIC interrupt controller, older platforms use AVIC (irq.o)
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obj-$(CONFIG_MXC_TZIC) += tzic.o
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obj-$(CONFIG_ARCH_MX1) += iomux-mx1-mx2.o dma-mx1-mx2.o
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obj-$(CONFIG_ARCH_MX2) += iomux-mx1-mx2.o dma-mx1-mx2.o
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CFLAGS_iomux-mx1-mx2.o = -DIMX_NEEDS_DEPRECATED_SYMBOLS
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@ -22,6 +22,7 @@ extern void mx31_map_io(void);
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extern void mx35_map_io(void);
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extern void mxc91231_map_io(void);
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extern void mxc_init_irq(void __iomem *);
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extern void tzic_init_irq(void __iomem *);
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extern void mx1_init_irq(void);
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extern void mx21_init_irq(void);
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extern void mx25_init_irq(void);
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@ -1,6 +1,6 @@
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/*
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* Copyright (C) 2007 Lennert Buytenhek <buytenh@wantstofly.org>
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* Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
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* Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved.
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*/
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/*
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@ -18,11 +18,16 @@
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.endm
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.macro get_irqnr_preamble, base, tmp
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#ifndef CONFIG_MXC_TZIC
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ldr \base, =avic_base
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ldr \base, [\base]
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#ifdef CONFIG_MXC_IRQ_PRIOR
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ldr r4, [\base, #AVIC_NIMASK]
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#endif
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#elif defined CONFIG_MXC_TZIC
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ldr \base, =tzic_base
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ldr \base, [\base]
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#endif /* CONFIG_MXC_TZIC */
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.endm
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.macro arch_ret_to_user, tmp1, tmp2
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@ -32,6 +37,7 @@
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@ and returns its number in irqnr
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@ and returns if an interrupt occured in irqstat
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.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
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#ifndef CONFIG_MXC_TZIC
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@ Load offset & priority of the highest priority
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@ interrupt pending from AVIC_NIVECSR
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ldr \irqstat, [\base, #0x40]
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@ -44,6 +50,32 @@
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bicne \tmp, \irqstat, #0xFFFFFFE0
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strne \tmp, [\base, #AVIC_NIMASK]
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streq r4, [\base, #AVIC_NIMASK]
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#endif
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#elif defined CONFIG_MXC_TZIC
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@ Load offset & priority of the highest priority
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@ interrupt pending.
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@ 0xD80 is HIPND0 register
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mov \irqnr, #0
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mov \irqstat, #0x0D80
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1000:
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ldr \tmp, [\irqstat, \base]
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cmp \tmp, #0
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bne 1001f
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addeq \irqnr, \irqnr, #32
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addeq \irqstat, \irqstat, #4
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cmp \irqnr, #128
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blo 1000b
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b 2001f
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1001: mov \irqstat, #1
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1002: tst \tmp, \irqstat
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bne 2002f
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movs \tmp, \tmp, lsr #1
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addne \irqnr, \irqnr, #1
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bne 1002b
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2001:
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mov \irqnr, #0
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2002:
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movs \irqnr, \irqnr
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#endif
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.endm
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@ -12,9 +12,13 @@
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#define __ASM_ARCH_MXC_IRQS_H__
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/*
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* So far all i.MX SoCs have 64 internal interrupts
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* SoCs with TZIC interrupt controller have 128 IRQs, those with AVIC have 64
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*/
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#ifdef CONFIG_MXC_TZIC
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#define MXC_INTERNAL_IRQS 128
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#else
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#define MXC_INTERNAL_IRQS 64
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#endif
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#define MXC_GPIO_IRQ_START MXC_INTERNAL_IRQS
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@ -0,0 +1,172 @@
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/*
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* Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved.
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*
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* The code contained herein is licensed under the GNU General Public
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* License. You may obtain a copy of the GNU General Public License
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* Version 2 or later at the following locations:
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*
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* http://www.opensource.org/licenses/gpl-license.html
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* http://www.gnu.org/copyleft/gpl.html
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*/
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#include <linux/module.h>
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#include <linux/moduleparam.h>
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#include <linux/init.h>
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#include <linux/device.h>
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#include <linux/errno.h>
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#include <linux/io.h>
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#include <asm/mach/irq.h>
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#include <mach/hardware.h>
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/*
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*****************************************
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* TZIC Registers *
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*****************************************
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*/
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#define TZIC_INTCNTL 0x0000 /* Control register */
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#define TZIC_INTTYPE 0x0004 /* Controller Type register */
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#define TZIC_IMPID 0x0008 /* Distributor Implementer Identification */
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#define TZIC_PRIOMASK 0x000C /* Priority Mask Reg */
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#define TZIC_SYNCCTRL 0x0010 /* Synchronizer Control register */
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#define TZIC_DSMINT 0x0014 /* DSM interrupt Holdoffregister */
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#define TZIC_INTSEC0(i) (0x0080 + ((i) << 2)) /* Interrupt Security Reg 0 */
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#define TZIC_ENSET0(i) (0x0100 + ((i) << 2)) /* Enable Set Reg 0 */
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#define TZIC_ENCLEAR0(i) (0x0180 + ((i) << 2)) /* Enable Clear Reg 0 */
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#define TZIC_SRCSET0 0x0200 /* Source Set Register 0 */
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#define TZIC_SRCCLAR0 0x0280 /* Source Clear Register 0 */
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#define TZIC_PRIORITY0 0x0400 /* Priority Register 0 */
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#define TZIC_PND0 0x0D00 /* Pending Register 0 */
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#define TZIC_HIPND0 0x0D80 /* High Priority Pending Register */
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#define TZIC_WAKEUP0(i) (0x0E00 + ((i) << 2)) /* Wakeup Config Register */
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#define TZIC_SWINT 0x0F00 /* Software Interrupt Rigger Register */
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#define TZIC_ID0 0x0FD0 /* Indentification Register 0 */
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void __iomem *tzic_base; /* Used as irq controller base in entry-macro.S */
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/**
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* tzic_mask_irq() - Disable interrupt number "irq" in the TZIC
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*
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* @param irq interrupt source number
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*/
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static void tzic_mask_irq(unsigned int irq)
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{
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int index, off;
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index = irq >> 5;
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off = irq & 0x1F;
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__raw_writel(1 << off, tzic_base + TZIC_ENCLEAR0(index));
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}
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/**
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* tzic_unmask_irq() - Enable interrupt number "irq" in the TZIC
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*
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* @param irq interrupt source number
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*/
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static void tzic_unmask_irq(unsigned int irq)
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{
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int index, off;
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index = irq >> 5;
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off = irq & 0x1F;
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__raw_writel(1 << off, tzic_base + TZIC_ENSET0(index));
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}
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static unsigned int wakeup_intr[4];
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/**
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* tzic_set_wake_irq() - Set interrupt number "irq" in the TZIC as a wake-up source.
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*
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* @param irq interrupt source number
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* @param enable enable as wake-up if equal to non-zero
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* disble as wake-up if equal to zero
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*
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* @return This function returns 0 on success.
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*/
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static int tzic_set_wake_irq(unsigned int irq, unsigned int enable)
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{
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unsigned int index, off;
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index = irq >> 5;
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off = irq & 0x1F;
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if (index > 3)
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return -EINVAL;
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if (enable)
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wakeup_intr[index] |= (1 << off);
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else
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wakeup_intr[index] &= ~(1 << off);
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return 0;
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}
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static struct irq_chip mxc_tzic_chip = {
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.name = "MXC_TZIC",
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.ack = tzic_mask_irq,
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.mask = tzic_mask_irq,
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.unmask = tzic_unmask_irq,
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.set_wake = tzic_set_wake_irq,
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};
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/*
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* This function initializes the TZIC hardware and disables all the
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* interrupts. It registers the interrupt enable and disable functions
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* to the kernel for each interrupt source.
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*/
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void __init tzic_init_irq(void __iomem *irqbase)
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{
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int i;
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tzic_base = irqbase;
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/* put the TZIC into the reset value with
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* all interrupts disabled
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*/
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i = __raw_readl(tzic_base + TZIC_INTCNTL);
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__raw_writel(0x80010001, tzic_base + TZIC_INTCNTL);
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__raw_writel(0x1f, tzic_base + TZIC_PRIOMASK);
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__raw_writel(0x02, tzic_base + TZIC_SYNCCTRL);
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for (i = 0; i < 4; i++)
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__raw_writel(0xFFFFFFFF, tzic_base + TZIC_INTSEC0(i));
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/* disable all interrupts */
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for (i = 0; i < 4; i++)
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__raw_writel(0xFFFFFFFF, tzic_base + TZIC_ENCLEAR0(i));
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/* all IRQ no FIQ Warning :: No selection */
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for (i = 0; i < MXC_INTERNAL_IRQS; i++) {
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set_irq_chip(i, &mxc_tzic_chip);
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set_irq_handler(i, handle_level_irq);
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set_irq_flags(i, IRQF_VALID);
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}
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pr_info("TrustZone Interrupt Controller (TZIC) initialized\n");
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}
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/**
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* tzic_enable_wake() - enable wakeup interrupt
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*
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* @param is_idle 1 if called in idle loop (ENSET0 register);
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* 0 to be used when called from low power entry
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* @return 0 if successful; non-zero otherwise
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*/
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int tzic_enable_wake(int is_idle)
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{
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unsigned int i, v;
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__raw_writel(1, tzic_base + TZIC_DSMINT);
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if (unlikely(__raw_readl(tzic_base + TZIC_DSMINT) == 0))
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return -EAGAIN;
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for (i = 0; i < 4; i++) {
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v = is_idle ? __raw_readl(TZIC_ENSET0(i)) : wakeup_intr[i];
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__raw_writel(v, TZIC_WAKEUP0(i));
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}
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return 0;
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}
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