pinctrl: tegra: correct bank for pingroup and drv pingroup
Cc: stable@kernel.org Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com> Acked-by: Stephen Warren <swarren@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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@ -3345,10 +3345,10 @@ static const struct tegra_function tegra30_functions[] = {
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FUNCTION(vi_alt3),
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};
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#define MUXCTL_REG_A 0x3000
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#define PINGROUP_REG_A 0x868
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#define DRV_PINGROUP_REG_A 0x868 /* bank 0 */
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#define PINGROUP_REG_A 0x3000 /* bank 1 */
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#define PINGROUP_REG_Y(r) ((r) - MUXCTL_REG_A)
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#define PINGROUP_REG_Y(r) ((r) - PINGROUP_REG_A)
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#define PINGROUP_REG_N(r) -1
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#define PINGROUP(pg_name, f0, f1, f2, f3, f_safe, r, od, ior) \
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@ -3364,25 +3364,25 @@ static const struct tegra_function tegra30_functions[] = {
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}, \
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.func_safe = TEGRA_MUX_ ## f_safe, \
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.mux_reg = PINGROUP_REG_Y(r), \
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.mux_bank = 0, \
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.mux_bank = 1, \
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.mux_bit = 0, \
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.pupd_reg = PINGROUP_REG_Y(r), \
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.pupd_bank = 0, \
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.pupd_bank = 1, \
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.pupd_bit = 2, \
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.tri_reg = PINGROUP_REG_Y(r), \
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.tri_bank = 0, \
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.tri_bank = 1, \
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.tri_bit = 4, \
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.einput_reg = PINGROUP_REG_Y(r), \
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.einput_bank = 0, \
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.einput_bank = 1, \
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.einput_bit = 5, \
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.odrain_reg = PINGROUP_REG_##od(r), \
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.odrain_bank = 0, \
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.odrain_bank = 1, \
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.odrain_bit = 6, \
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.lock_reg = PINGROUP_REG_Y(r), \
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.lock_bank = 0, \
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.lock_bank = 1, \
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.lock_bit = 7, \
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.ioreset_reg = PINGROUP_REG_##ior(r), \
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.ioreset_bank = 0, \
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.ioreset_bank = 1, \
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.ioreset_bit = 8, \
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.drv_reg = -1, \
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}
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@ -3401,8 +3401,8 @@ static const struct tegra_function tegra30_functions[] = {
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.odrain_reg = -1, \
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.lock_reg = -1, \
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.ioreset_reg = -1, \
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.drv_reg = ((r) - PINGROUP_REG_A), \
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.drv_bank = 1, \
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.drv_reg = ((r) - DRV_PINGROUP_REG_A), \
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.drv_bank = 0, \
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.hsm_bit = hsm_b, \
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.schmitt_bit = schmitt_b, \
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.lpmd_bit = lpmd_b, \
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