From aecc72b14d11327804f7ca1fc76ca88a22cc1136 Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Sat, 20 Jun 2020 18:10:08 +0200 Subject: [PATCH 1/6] ARM: dts: meson8: add power domain controller The Meson8 SoCs have a power domain controller which can turn on/off various register areas (such as: Ethernet, VPU, etc.). Add the main "pwrc" controller and configure the Ethernet power domain. Signed-off-by: Martin Blumenstingl Signed-off-by: Kevin Hilman Reviewed-by: Neil Armstrong Link: https://lore.kernel.org/r/20200620161010.23171-2-martin.blumenstingl@googlemail.com --- arch/arm/boot/dts/meson8.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi index eedb92526968..d09d19d4423a 100644 --- a/arch/arm/boot/dts/meson8.dtsi +++ b/arch/arm/boot/dts/meson8.dtsi @@ -6,6 +6,7 @@ #include #include #include +#include #include #include #include "meson.dtsi" @@ -454,6 +455,8 @@ ðmac { clocks = <&clkc CLKID_ETH>; clock-names = "stmmaceth"; + + power-domains = <&pwrc PWRC_MESON8_ETHERNET_MEM_ID>; }; &gpio_intc { @@ -469,6 +472,16 @@ #clock-cells = <1>; #reset-cells = <1>; }; + + pwrc: power-controller { + compatible = "amlogic,meson8-pwrc"; + #power-domain-cells = <1>; + amlogic,ao-sysctrl = <&pmu>; + clocks = <&clkc CLKID_VPU>; + clock-names = "vpu"; + assigned-clocks = <&clkc CLKID_VPU>; + assigned-clock-rates = <364285714>; + }; }; &hwrng { From c5d3d3cf00d5ed74359e71f7b5d003cf34ba014c Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Sat, 20 Jun 2020 18:10:09 +0200 Subject: [PATCH 2/6] ARM: dts: meson8m2: add resets for the power domain controller The Meson8m2 SoCs has introduced additional reset lines for the VPU compared to Meson8. Also it uses a slightly different VPU clock frequency compared to Meson8 since it can now achieve 364MHz thanks to the addition of the GP_PLL. Add the reset lines, VPU clock configuration and update the compatible string so the implementation differences can be managed. Signed-off-by: Martin Blumenstingl Signed-off-by: Kevin Hilman Reviewed-by: Neil Armstrong Link: https://lore.kernel.org/r/20200620161010.23171-3-martin.blumenstingl@googlemail.com --- arch/arm/boot/dts/meson8m2.dtsi | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm/boot/dts/meson8m2.dtsi b/arch/arm/boot/dts/meson8m2.dtsi index 2397ba06d608..c7ddbb210366 100644 --- a/arch/arm/boot/dts/meson8m2.dtsi +++ b/arch/arm/boot/dts/meson8m2.dtsi @@ -61,6 +61,25 @@ }; }; +&pwrc { + compatible = "amlogic,meson8m2-pwrc"; + resets = <&reset RESET_DBLK>, + <&reset RESET_PIC_DC>, + <&reset RESET_HDMI_APB>, + <&reset RESET_HDMI_SYSTEM_RESET>, + <&reset RESET_VENCI>, + <&reset RESET_VENCP>, + <&reset RESET_VDAC_4>, + <&reset RESET_VENCL>, + <&reset RESET_VIU>, + <&reset RESET_VENC>, + <&reset RESET_RDMA>; + reset-names = "dblk", "pic_dc", "hdmi_apb", "hdmi_system", "venci", + "vencp", "vdac", "vencl", "viu", "venc", "rdma"; + assigned-clocks = <&clkc CLKID_VPU>; + assigned-clock-rates = <364000000>; +}; + &saradc { compatible = "amlogic,meson8m2-saradc", "amlogic,meson-saradc"; }; From 9960cacbaeb1ccc1b2d9840cadb18844d48a337b Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Sat, 20 Jun 2020 18:10:10 +0200 Subject: [PATCH 3/6] ARM: dts: meson8b: add power domain controller The Meson8b SoCs have a power domain controller which can turn on/off various register areas (such as: Ethernet, VPU, etc.). Add the main "pwrc" controller and configure the Ethernet power domain. Signed-off-by: Martin Blumenstingl Signed-off-by: Kevin Hilman Reviewed-by: Neil Armstrong Link: https://lore.kernel.org/r/20200620161010.23171-4-martin.blumenstingl@googlemail.com --- arch/arm/boot/dts/meson8b.dtsi | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/arch/arm/boot/dts/meson8b.dtsi b/arch/arm/boot/dts/meson8b.dtsi index ba36168b9c1b..2069c57343e5 100644 --- a/arch/arm/boot/dts/meson8b.dtsi +++ b/arch/arm/boot/dts/meson8b.dtsi @@ -7,6 +7,7 @@ #include #include #include +#include #include #include #include "meson.dtsi" @@ -433,6 +434,8 @@ resets = <&reset RESET_ETHERNET>; reset-names = "stmmaceth"; + + power-domains = <&pwrc PWRC_MESON8_ETHERNET_MEM_ID>; }; &gpio_intc { @@ -449,6 +452,30 @@ #clock-cells = <1>; #reset-cells = <1>; }; + + pwrc: power-controller { + compatible = "amlogic,meson8b-pwrc"; + #power-domain-cells = <1>; + amlogic,ao-sysctrl = <&pmu>; + resets = <&reset RESET_DBLK>, + <&reset RESET_PIC_DC>, + <&reset RESET_HDMI_APB>, + <&reset RESET_HDMI_SYSTEM_RESET>, + <&reset RESET_VENCI>, + <&reset RESET_VENCP>, + <&reset RESET_VDAC_4>, + <&reset RESET_VENCL>, + <&reset RESET_VIU>, + <&reset RESET_VENC>, + <&reset RESET_RDMA>; + reset-names = "dblk", "pic_dc", "hdmi_apb", "hdmi_system", + "venci", "vencp", "vdac", "vencl", "viu", + "venc", "rdma"; + clocks = <&clkc CLKID_VPU>; + clock-names = "vpu"; + assigned-clocks = <&clkc CLKID_VPU>; + assigned-clock-rates = <182142857>; + }; }; &hwrng { From 73106f75bf9498ff5d50f1052ad3cf03730d806d Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Sat, 20 Jun 2020 18:36:52 +0200 Subject: [PATCH 4/6] ARM: dts: meson: add the SDHC MMC controller Meson6, Meson8, Meson8b and Meson8m2 are using a similar SDHC controller IP which typically connects to an eMMC chip (because unlike the SDIO controller the SDHC controller has an 8-bit bus interface). On Meson8, Meson8b and Meson8m2 the clock inputs are all the same. However, Meson8m2 seems to have an improved version of the SHDC controller IP which doesn't require the driver to wait manually for a flush of a DMA transfer. Thus every SoC has it's own compatible string so if more difference are discovered they can be implemented. Signed-off-by: Martin Blumenstingl Signed-off-by: Kevin Hilman Link: https://lore.kernel.org/r/20200620163654.37207-2-martin.blumenstingl@googlemail.com --- arch/arm/boot/dts/meson.dtsi | 7 +++++++ arch/arm/boot/dts/meson8.dtsi | 19 +++++++++++++++++++ arch/arm/boot/dts/meson8b.dtsi | 20 ++++++++++++++++++++ arch/arm/boot/dts/meson8m2.dtsi | 4 ++++ 4 files changed, 50 insertions(+) diff --git a/arch/arm/boot/dts/meson.dtsi b/arch/arm/boot/dts/meson.dtsi index ae89deaa8c9c..464057989572 100644 --- a/arch/arm/boot/dts/meson.dtsi +++ b/arch/arm/boot/dts/meson.dtsi @@ -140,6 +140,13 @@ status = "disabled"; }; + sdhc: mmc@8e00 { + compatible = "amlogic,meson-mx-sdhc"; + reg = <0x8e00 0x42>; + interrupts = ; + status = "disabled"; + }; + gpio_intc: interrupt-controller@9880 { compatible = "amlogic,meson-gpio-intc"; reg = <0x9880 0x10>; diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi index d09d19d4423a..277c0bb10453 100644 --- a/arch/arm/boot/dts/meson8.dtsi +++ b/arch/arm/boot/dts/meson8.dtsi @@ -386,6 +386,15 @@ }; }; + sdxc_b_pins: sdxc-b { + mux { + groups = "sdxc_d0_b", "sdxc_d13_b", + "sdxc_clk_b", "sdxc_cmd_b"; + function = "sdxc_b"; + bias-pull-up; + }; + }; + spi_nor_pins: nor { mux { groups = "nor_d", "nor_q", "nor_c", "nor_cs"; @@ -560,6 +569,16 @@ nvmem-cell-names = "temperature_calib"; }; +&sdhc { + compatible = "amlogic,meson8-sdhc", "amlogic,meson-mx-sdhc"; + clocks = <&xtal>, + <&clkc CLKID_FCLK_DIV4>, + <&clkc CLKID_FCLK_DIV3>, + <&clkc CLKID_FCLK_DIV5>, + <&clkc CLKID_SDHC>; + clock-names = "clkin0", "clkin1", "clkin2", "clkin3", "pclk"; +}; + &sdio { compatible = "amlogic,meson8-sdio", "amlogic,meson-mx-sdio"; clocks = <&clkc CLKID_SDIO>, <&clkc CLKID_CLK81>; diff --git a/arch/arm/boot/dts/meson8b.dtsi b/arch/arm/boot/dts/meson8b.dtsi index 2069c57343e5..2401cdf5f751 100644 --- a/arch/arm/boot/dts/meson8b.dtsi +++ b/arch/arm/boot/dts/meson8b.dtsi @@ -363,6 +363,16 @@ }; }; + sdxc_c_pins: sdxc-c { + mux { + groups = "sdxc_d0_c", "sdxc_d13_c", + "sdxc_d47_c", "sdxc_clk_c", + "sdxc_cmd_c"; + function = "sdxc_c"; + bias-pull-up; + }; + }; + pwm_c1_pins: pwm-c1 { mux { groups = "pwm_c1"; @@ -554,6 +564,16 @@ nvmem-cell-names = "temperature_calib"; }; +&sdhc { + compatible = "amlogic,meson8-sdhc", "amlogic,meson-mx-sdhc"; + clocks = <&xtal>, + <&clkc CLKID_FCLK_DIV4>, + <&clkc CLKID_FCLK_DIV3>, + <&clkc CLKID_FCLK_DIV5>, + <&clkc CLKID_SDHC>; + clock-names = "clkin0", "clkin1", "clkin2", "clkin3", "pclk"; +}; + &sdio { compatible = "amlogic,meson8b-sdio", "amlogic,meson-mx-sdio"; clocks = <&clkc CLKID_SDIO>, <&clkc CLKID_CLK81>; diff --git a/arch/arm/boot/dts/meson8m2.dtsi b/arch/arm/boot/dts/meson8m2.dtsi index c7ddbb210366..6725dd9fd825 100644 --- a/arch/arm/boot/dts/meson8m2.dtsi +++ b/arch/arm/boot/dts/meson8m2.dtsi @@ -84,6 +84,10 @@ compatible = "amlogic,meson8m2-saradc", "amlogic,meson-saradc"; }; +&sdhc { + compatible = "amlogic,meson8m2-sdhc", "amlogic,meson-mx-sdhc"; +}; + &usb0_phy { compatible = "amlogic,meson8m2-usb2-phy", "amlogic,meson-mx-usb2-phy"; }; From 73501b890a6f15460613878b463319d0e0cd1632 Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Sat, 20 Jun 2020 18:36:53 +0200 Subject: [PATCH 5/6] ARM: dts: meson8b: ec100: enable the SDHC controller EC-100 has built-in eMMC flash which is hard-wired to 3.3V VCC (which means it's limited to high-speed MMC modes). Enable the SDHC controller to access the contents of the eMMC flash. Signed-off-by: Martin Blumenstingl Signed-off-by: Kevin Hilman Link: https://lore.kernel.org/r/20200620163654.37207-3-martin.blumenstingl@googlemail.com --- arch/arm/boot/dts/meson8b-ec100.dts | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/arch/arm/boot/dts/meson8b-ec100.dts b/arch/arm/boot/dts/meson8b-ec100.dts index 163a200d5a7b..ed06102a4014 100644 --- a/arch/arm/boot/dts/meson8b-ec100.dts +++ b/arch/arm/boot/dts/meson8b-ec100.dts @@ -27,6 +27,11 @@ reg = <0x40000000 0x40000000>; }; + emmc_pwrseq: emmc-pwrseq { + compatible = "mmc-pwrseq-emmc"; + reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>; + }; + gpio-keys { compatible = "gpio-keys-polled"; #address-cells = <1>; @@ -299,6 +304,26 @@ vref-supply = <&vcc_1v8>; }; +&sdhc { + status = "okay"; + + pinctrl-0 = <&sdxc_c_pins>; + pinctrl-names = "default"; + + bus-width = <8>; + max-frequency = <50000000>; + + cap-mmc-highspeed; + disable-wp; + non-removable; + no-sdio; + + mmc-pwrseq = <&emmc_pwrseq>; + + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&vcc_3v3>; +}; + &sdio { status = "okay"; From d6a3873c7be6d58914ea5584dc7875f2045d6721 Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Sat, 20 Jun 2020 18:36:54 +0200 Subject: [PATCH 6/6] ARM: dts: meson8b: odroidc1: enable the SDHC controller Odroid-C1 has an eMMC connector where users can optionally install an eMMC module. The eMMC modules run off a 1.8V VQMMC supply which means that HS-200 mode can be used (this is the highest mode that the SDHC controller supports). Enable the SDHC controller so eMMC modules can be accessed. Signed-off-by: Martin Blumenstingl Signed-off-by: Kevin Hilman Link: https://lore.kernel.org/r/20200620163654.37207-4-martin.blumenstingl@googlemail.com --- arch/arm/boot/dts/meson8b-odroidc1.dts | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/arch/arm/boot/dts/meson8b-odroidc1.dts b/arch/arm/boot/dts/meson8b-odroidc1.dts index cb21ac9f517c..0c26467de4d0 100644 --- a/arch/arm/boot/dts/meson8b-odroidc1.dts +++ b/arch/arm/boot/dts/meson8b-odroidc1.dts @@ -15,6 +15,7 @@ aliases { serial0 = &uart_AO; mmc0 = &sd_card_slot; + mmc1 = &sdhc; }; chosen { @@ -26,6 +27,11 @@ reg = <0x40000000 0x40000000>; }; + emmc_pwrseq: emmc-pwrseq { + compatible = "mmc-pwrseq-emmc"; + reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>; + }; + leds { compatible = "gpio-leds"; blue { @@ -310,6 +316,26 @@ vref-supply = <&vcc_1v8>; }; +&sdhc { + status = "okay"; + + pinctrl-0 = <&sdxc_c_pins>; + pinctrl-names = "default"; + + bus-width = <8>; + max-frequency = <100000000>; + + disable-wp; + cap-mmc-highspeed; + mmc-hs200-1_8v; + no-sdio; + + mmc-pwrseq = <&emmc_pwrseq>; + + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&vcc_1v8>; +}; + &sdio { status = "okay";