OMAP: DSS2: Use dss_features framework on DSS2 code
Calls init functions of dss_features during dss_probe, and the following
features are made omapxxxx independent:
- number of managers, overlays
- supported color modes for each overlay
- supported displays for each manager
- global aplha, and restriction of global alpha for video1 pipeline
- The register field ranges : FIRHINC, FIRVINC, FIFOHIGHTHRESHOLD
FIFOLOWTHRESHOLD and FIFOSIZE
Signed-off-by: Archit Taneja <archit@ti.com>
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
This commit is contained in:
Archit Taneja
Tomi Valkeinen
Родитель
e1ef4d236f
Коммит
a0acb5574b
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@ -81,37 +81,6 @@ enum omap_color_mode {
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OMAP_DSS_COLOR_ARGB32 = 1 << 11, /* ARGB32 */
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OMAP_DSS_COLOR_RGBA32 = 1 << 12, /* RGBA32 */
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OMAP_DSS_COLOR_RGBX32 = 1 << 13, /* RGBx32 */
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OMAP_DSS_COLOR_GFX_OMAP2 =
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OMAP_DSS_COLOR_CLUT1 | OMAP_DSS_COLOR_CLUT2 |
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OMAP_DSS_COLOR_CLUT4 | OMAP_DSS_COLOR_CLUT8 |
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OMAP_DSS_COLOR_RGB12U | OMAP_DSS_COLOR_RGB16 |
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OMAP_DSS_COLOR_RGB24U | OMAP_DSS_COLOR_RGB24P,
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OMAP_DSS_COLOR_VID_OMAP2 =
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OMAP_DSS_COLOR_RGB16 | OMAP_DSS_COLOR_RGB24U |
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OMAP_DSS_COLOR_RGB24P | OMAP_DSS_COLOR_YUV2 |
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OMAP_DSS_COLOR_UYVY,
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OMAP_DSS_COLOR_GFX_OMAP3 =
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OMAP_DSS_COLOR_CLUT1 | OMAP_DSS_COLOR_CLUT2 |
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OMAP_DSS_COLOR_CLUT4 | OMAP_DSS_COLOR_CLUT8 |
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OMAP_DSS_COLOR_RGB12U | OMAP_DSS_COLOR_ARGB16 |
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OMAP_DSS_COLOR_RGB16 | OMAP_DSS_COLOR_RGB24U |
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OMAP_DSS_COLOR_RGB24P | OMAP_DSS_COLOR_ARGB32 |
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OMAP_DSS_COLOR_RGBA32 | OMAP_DSS_COLOR_RGBX32,
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OMAP_DSS_COLOR_VID1_OMAP3 =
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OMAP_DSS_COLOR_RGB12U | OMAP_DSS_COLOR_RGB16 |
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OMAP_DSS_COLOR_RGB24U | OMAP_DSS_COLOR_RGB24P |
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OMAP_DSS_COLOR_YUV2 | OMAP_DSS_COLOR_UYVY,
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OMAP_DSS_COLOR_VID2_OMAP3 =
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OMAP_DSS_COLOR_RGB12U | OMAP_DSS_COLOR_ARGB16 |
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OMAP_DSS_COLOR_RGB16 | OMAP_DSS_COLOR_RGB24U |
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OMAP_DSS_COLOR_RGB24P | OMAP_DSS_COLOR_YUV2 |
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OMAP_DSS_COLOR_UYVY | OMAP_DSS_COLOR_ARGB32 |
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OMAP_DSS_COLOR_RGBA32 | OMAP_DSS_COLOR_RGBX32,
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};
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enum omap_lcd_display_type {
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@ -37,6 +37,7 @@
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#include <plat/clock.h>
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#include "dss.h"
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#include "dss_features.h"
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static struct {
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struct platform_device *pdev;
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@ -502,6 +503,8 @@ static int omap_dss_probe(struct platform_device *pdev)
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core.pdev = pdev;
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dss_features_init();
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dss_init_overlay_managers(pdev);
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dss_init_overlays(pdev);
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@ -39,6 +39,7 @@
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#include <plat/display.h>
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#include "dss.h"
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#include "dss_features.h"
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/* DISPC */
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#define DISPC_BASE 0x48050400
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@ -774,12 +775,12 @@ static void _dispc_set_vid_size(enum omap_plane plane, int width, int height)
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static void _dispc_setup_global_alpha(enum omap_plane plane, u8 global_alpha)
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{
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BUG_ON(plane == OMAP_DSS_VIDEO1);
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if (cpu_is_omap24xx())
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if (!dss_has_feature(FEAT_GLOBAL_ALPHA))
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return;
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BUG_ON(!dss_has_feature(FEAT_GLOBAL_ALPHA_VID1) &&
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plane == OMAP_DSS_VIDEO1);
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if (plane == OMAP_DSS_GFX)
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REG_FLD_MOD(DISPC_GLOBAL_ALPHA, global_alpha, 7, 0);
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else if (plane == OMAP_DSS_VIDEO2)
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@ -949,17 +950,14 @@ static void dispc_read_plane_fifo_sizes(void)
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DISPC_VID_FIFO_SIZE_STATUS(1) };
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u32 size;
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int plane;
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u8 start, end;
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enable_clocks(1);
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for (plane = 0; plane < ARRAY_SIZE(dispc.fifo_size); ++plane) {
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if (cpu_is_omap24xx())
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size = FLD_GET(dispc_read_reg(fsz_reg[plane]), 8, 0);
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else if (cpu_is_omap34xx())
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size = FLD_GET(dispc_read_reg(fsz_reg[plane]), 10, 0);
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else
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BUG();
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dss_feat_get_reg_field(FEAT_REG_FIFOSIZE, &start, &end);
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for (plane = 0; plane < ARRAY_SIZE(dispc.fifo_size); ++plane) {
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size = FLD_GET(dispc_read_reg(fsz_reg[plane]), start, end);
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dispc.fifo_size[plane] = size;
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}
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@ -976,6 +974,8 @@ void dispc_setup_plane_fifo(enum omap_plane plane, u32 low, u32 high)
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const struct dispc_reg ftrs_reg[] = { DISPC_GFX_FIFO_THRESHOLD,
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DISPC_VID_FIFO_THRESHOLD(0),
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DISPC_VID_FIFO_THRESHOLD(1) };
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u8 hi_start, hi_end, lo_start, lo_end;
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enable_clocks(1);
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DSSDBG("fifo(%d) low/high old %u/%u, new %u/%u\n",
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@ -984,12 +984,12 @@ void dispc_setup_plane_fifo(enum omap_plane plane, u32 low, u32 high)
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REG_GET(ftrs_reg[plane], 27, 16),
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low, high);
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if (cpu_is_omap24xx())
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dispc_write_reg(ftrs_reg[plane],
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FLD_VAL(high, 24, 16) | FLD_VAL(low, 8, 0));
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else
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dispc_write_reg(ftrs_reg[plane],
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FLD_VAL(high, 27, 16) | FLD_VAL(low, 11, 0));
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dss_feat_get_reg_field(FEAT_REG_FIFOHIGHTHRESHOLD, &hi_start, &hi_end);
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dss_feat_get_reg_field(FEAT_REG_FIFOLOWTHRESHOLD, &lo_start, &lo_end);
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dispc_write_reg(ftrs_reg[plane],
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FLD_VAL(high, hi_start, hi_end) |
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FLD_VAL(low, lo_start, lo_end));
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enable_clocks(0);
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}
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@ -1009,13 +1009,16 @@ static void _dispc_set_fir(enum omap_plane plane, int hinc, int vinc)
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u32 val;
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const struct dispc_reg fir_reg[] = { DISPC_VID_FIR(0),
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DISPC_VID_FIR(1) };
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u8 hinc_start, hinc_end, vinc_start, vinc_end;
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BUG_ON(plane == OMAP_DSS_GFX);
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if (cpu_is_omap24xx())
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val = FLD_VAL(vinc, 27, 16) | FLD_VAL(hinc, 11, 0);
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else
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val = FLD_VAL(vinc, 28, 16) | FLD_VAL(hinc, 12, 0);
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dss_feat_get_reg_field(FEAT_REG_FIRHINC, &hinc_start, &hinc_end);
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dss_feat_get_reg_field(FEAT_REG_FIRVINC, &vinc_start, &vinc_end);
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val = FLD_VAL(vinc, vinc_start, vinc_end) |
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FLD_VAL(hinc, hinc_start, hinc_end);
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dispc_write_reg(fir_reg[plane-1], val);
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}
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@ -1541,6 +1544,8 @@ static int _dispc_setup_plane(enum omap_plane plane,
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case OMAP_DSS_COLOR_ARGB16:
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case OMAP_DSS_COLOR_ARGB32:
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case OMAP_DSS_COLOR_RGBA32:
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if (!dss_has_feature(FEAT_GLOBAL_ALPHA))
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return -EINVAL;
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case OMAP_DSS_COLOR_RGBX32:
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if (cpu_is_omap24xx())
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return -EINVAL;
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@ -1581,9 +1586,10 @@ static int _dispc_setup_plane(enum omap_plane plane,
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case OMAP_DSS_COLOR_ARGB16:
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case OMAP_DSS_COLOR_ARGB32:
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case OMAP_DSS_COLOR_RGBA32:
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if (cpu_is_omap24xx())
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if (!dss_has_feature(FEAT_GLOBAL_ALPHA))
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return -EINVAL;
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if (plane == OMAP_DSS_VIDEO1)
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if (!dss_has_feature(FEAT_GLOBAL_ALPHA_VID1) &&
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plane == OMAP_DSS_VIDEO1)
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return -EINVAL;
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break;
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@ -1976,7 +1982,7 @@ void dispc_enable_trans_key(enum omap_channel ch, bool enable)
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}
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void dispc_enable_alpha_blending(enum omap_channel ch, bool enable)
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{
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if (cpu_is_omap24xx())
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if (!dss_has_feature(FEAT_GLOBAL_ALPHA))
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return;
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enable_clocks(1);
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@ -1990,7 +1996,7 @@ bool dispc_alpha_blending_enabled(enum omap_channel ch)
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{
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bool enabled;
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if (cpu_is_omap24xx())
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if (!dss_has_feature(FEAT_GLOBAL_ALPHA))
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return false;
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enable_clocks(1);
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@ -33,6 +33,7 @@
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#include <plat/cpu.h>
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#include "dss.h"
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#include "dss_features.h"
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static int num_managers;
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static struct list_head manager_list;
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@ -448,8 +449,8 @@ struct manager_cache_data {
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static struct {
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spinlock_t lock;
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struct overlay_cache_data overlay_cache[3];
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struct manager_cache_data manager_cache[2];
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struct overlay_cache_data overlay_cache[MAX_DSS_OVERLAYS];
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struct manager_cache_data manager_cache[MAX_DSS_MANAGERS];
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bool irq_enabled;
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} dss_cache;
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@ -882,12 +883,12 @@ static int configure_dispc(void)
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{
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struct overlay_cache_data *oc;
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struct manager_cache_data *mc;
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const int num_ovls = ARRAY_SIZE(dss_cache.overlay_cache);
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const int num_mgrs = ARRAY_SIZE(dss_cache.manager_cache);
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const int num_ovls = dss_feat_get_num_ovls();
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const int num_mgrs = dss_feat_get_num_mgrs();
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int i;
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int r;
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bool mgr_busy[2];
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bool mgr_go[2];
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bool mgr_busy[MAX_DSS_MANAGERS];
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bool mgr_go[MAX_DSS_MANAGERS];
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bool busy;
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r = 0;
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@ -989,7 +990,7 @@ void dss_setup_partial_planes(struct omap_dss_device *dssdev,
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{
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struct overlay_cache_data *oc;
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struct manager_cache_data *mc;
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const int num_ovls = ARRAY_SIZE(dss_cache.overlay_cache);
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const int num_ovls = dss_feat_get_num_ovls();
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struct omap_overlay_manager *mgr;
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int i;
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u16 x, y, w, h;
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@ -1121,8 +1122,8 @@ void dss_start_update(struct omap_dss_device *dssdev)
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{
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struct manager_cache_data *mc;
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struct overlay_cache_data *oc;
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const int num_ovls = ARRAY_SIZE(dss_cache.overlay_cache);
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const int num_mgrs = ARRAY_SIZE(dss_cache.manager_cache);
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const int num_ovls = dss_feat_get_num_ovls();
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const int num_mgrs = dss_feat_get_num_mgrs();
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struct omap_overlay_manager *mgr;
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int i;
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@ -1151,10 +1152,10 @@ static void dss_apply_irq_handler(void *data, u32 mask)
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{
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struct manager_cache_data *mc;
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struct overlay_cache_data *oc;
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const int num_ovls = ARRAY_SIZE(dss_cache.overlay_cache);
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const int num_mgrs = ARRAY_SIZE(dss_cache.manager_cache);
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const int num_ovls = dss_feat_get_num_ovls();
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const int num_mgrs = dss_feat_get_num_mgrs();
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int i, r;
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bool mgr_busy[2];
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bool mgr_busy[MAX_DSS_MANAGERS];
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mgr_busy[0] = dispc_go_busy(0);
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mgr_busy[1] = dispc_go_busy(1);
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@ -1461,7 +1462,7 @@ int dss_init_overlay_managers(struct platform_device *pdev)
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num_managers = 0;
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for (i = 0; i < 2; ++i) {
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for (i = 0; i < dss_feat_get_num_mgrs(); ++i) {
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struct omap_overlay_manager *mgr;
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mgr = kzalloc(sizeof(*mgr), GFP_KERNEL);
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@ -1471,14 +1472,10 @@ int dss_init_overlay_managers(struct platform_device *pdev)
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case 0:
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mgr->name = "lcd";
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mgr->id = OMAP_DSS_CHANNEL_LCD;
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mgr->supported_displays =
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OMAP_DISPLAY_TYPE_DPI | OMAP_DISPLAY_TYPE_DBI |
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OMAP_DISPLAY_TYPE_SDI | OMAP_DISPLAY_TYPE_DSI;
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break;
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case 1:
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mgr->name = "tv";
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mgr->id = OMAP_DSS_CHANNEL_DIGIT;
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mgr->supported_displays = OMAP_DISPLAY_TYPE_VENC;
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break;
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}
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@ -1494,6 +1491,8 @@ int dss_init_overlay_managers(struct platform_device *pdev)
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mgr->disable = &dss_mgr_disable;
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mgr->caps = OMAP_DSS_OVL_MGR_CAP_DISPC;
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mgr->supported_displays =
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dss_feat_get_supported_displays(mgr->id);
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dss_overlay_setup_dispc_manager(mgr);
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@ -35,6 +35,7 @@
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#include <plat/cpu.h>
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#include "dss.h"
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#include "dss_features.h"
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static int num_overlays;
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static struct list_head overlay_list;
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@ -237,7 +238,8 @@ static ssize_t overlay_global_alpha_store(struct omap_overlay *ovl,
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/* Video1 plane does not support global alpha
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* to always make it 255 completely opaque
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*/
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if (ovl->id == OMAP_DSS_VIDEO1)
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if (!dss_has_feature(FEAT_GLOBAL_ALPHA_VID1) &&
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ovl->id == OMAP_DSS_VIDEO1)
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info.global_alpha = 255;
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else
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info.global_alpha = simple_strtoul(buf, NULL, 10);
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@ -510,11 +512,11 @@ static void omap_dss_add_overlay(struct omap_overlay *overlay)
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list_add_tail(&overlay->list, &overlay_list);
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}
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static struct omap_overlay *dispc_overlays[3];
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static struct omap_overlay *dispc_overlays[MAX_DSS_OVERLAYS];
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void dss_overlay_setup_dispc_manager(struct omap_overlay_manager *mgr)
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{
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mgr->num_overlays = 3;
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mgr->num_overlays = dss_feat_get_num_ovls();
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mgr->overlays = dispc_overlays;
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}
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@ -535,7 +537,7 @@ void dss_init_overlays(struct platform_device *pdev)
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num_overlays = 0;
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for (i = 0; i < 3; ++i) {
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for (i = 0; i < dss_feat_get_num_ovls(); ++i) {
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struct omap_overlay *ovl;
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ovl = kzalloc(sizeof(*ovl), GFP_KERNEL);
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@ -545,18 +547,12 @@ void dss_init_overlays(struct platform_device *pdev)
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case 0:
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ovl->name = "gfx";
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ovl->id = OMAP_DSS_GFX;
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ovl->supported_modes = cpu_is_omap34xx() ?
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OMAP_DSS_COLOR_GFX_OMAP3 :
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OMAP_DSS_COLOR_GFX_OMAP2;
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ovl->caps = OMAP_DSS_OVL_CAP_DISPC;
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ovl->info.global_alpha = 255;
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break;
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case 1:
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ovl->name = "vid1";
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ovl->id = OMAP_DSS_VIDEO1;
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ovl->supported_modes = cpu_is_omap34xx() ?
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OMAP_DSS_COLOR_VID1_OMAP3 :
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OMAP_DSS_COLOR_VID_OMAP2;
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ovl->caps = OMAP_DSS_OVL_CAP_SCALE |
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OMAP_DSS_OVL_CAP_DISPC;
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ovl->info.global_alpha = 255;
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@ -564,9 +560,6 @@ void dss_init_overlays(struct platform_device *pdev)
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case 2:
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ovl->name = "vid2";
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ovl->id = OMAP_DSS_VIDEO2;
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ovl->supported_modes = cpu_is_omap34xx() ?
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OMAP_DSS_COLOR_VID2_OMAP3 :
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OMAP_DSS_COLOR_VID_OMAP2;
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ovl->caps = OMAP_DSS_OVL_CAP_SCALE |
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OMAP_DSS_OVL_CAP_DISPC;
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ovl->info.global_alpha = 255;
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@ -579,6 +572,9 @@ void dss_init_overlays(struct platform_device *pdev)
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ovl->get_overlay_info = &dss_ovl_get_overlay_info;
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ovl->wait_for_go = &dss_ovl_wait_for_go;
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ovl->supported_modes =
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dss_feat_get_supported_color_modes(ovl->id);
|
||||
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omap_dss_add_overlay(ovl);
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||||
r = kobject_init_and_add(&ovl->kobj, &overlay_ktype,
|
||||
|
|
@ -651,7 +647,7 @@ void dss_recheck_connections(struct omap_dss_device *dssdev, bool force)
|
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}
|
||||
|
||||
if (mgr) {
|
||||
for (i = 0; i < 3; i++) {
|
||||
for (i = 0; i < dss_feat_get_num_ovls(); i++) {
|
||||
struct omap_overlay *ovl;
|
||||
ovl = omap_dss_get_overlay(i);
|
||||
if (!ovl->manager || force) {
|
||||
|
|
|
|||
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